DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 7 and 10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claims 7 and 10 recite the limitation “wherein the first output circuit is a circuit having a characteristic impedance equal to a load at a time of saturation output of the first amplifier, the second output circuit is a circuit having a characteristic impedance equal to a load at a time of saturation output of the second amplifier, the third output circuit is a circuit having a characteristic impedance equal to a load at a time of saturation output of the third amplifier, the fourth output circuit is a circuit having a characteristic impedance equal to a load at a time of saturation output of the fourth amplifier, and the large branch synthesis circuit includes a fifth output circuit connected to an output side of the first small branch synthesis circuit and having a characteristic impedance equal to half of the load at the time of saturation output of the first amplifier and a sixth output circuit connected to an output side of the second small branch synthesis circuit and having a characteristic impedance equal to half of the load at the time of saturation output of the third amplifier.”
The specification does not teach one of ordinary skill in the art how to make and use the claimed invention. The disclosure lacks sufficient technical detail explaining how to implement the output circuit whose characteristics impedance equal the load impedance specifically at the time the amplifier reaches saturation. While the specification discloses output circuitry, load modulation and amplifier operation, it does not disclose characteristics impedance values equal to the load and any condition to saturation output, therefore fails to enable the full scope of the claim.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, recites “synthesis circuit to synthesize outputs of the amplifiers”. It is unclear to the Examiner what “synthesis circuit” applicant refer.
Claim 2, recites “a synthesis circuit that is a tournament type synthesis circuit”. It is unclear to the Examiner what “tournament type synthesis circuit” applicant refer.
Claim 3-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being depended on claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Nakatani et al. (US 2020/0244227 and Nakatani hereinafter) in view of Schmidt (US 2013/0314162).
Regarding claim 1, Nakatani discloses a Doherty amplifier [fig. 7] in which the number of amplifiers contributing to an amplification operation changes depending on power of an input signal [input signal], the Doherty amplifier comprising: at least four or more amplifiers [5 and 6 in 41 and 42]; and a synthesis circuit [7 and 8] to synthesize outputs of the amplifiers, wherein the amplifiers are connected in parallel with each other, the amplifiers include a first amplifier [5 in 41], a second amplifier [6 in 41], a third amplifier [5 in 42], and a fourth amplifier [6 in 42], order in which the amplifiers contribute to the amplification operation differs depending on a frequency of the input signal, the synthesis circuit includes: a first output circuit [7 in 41] connected to an output terminal of the first amplifier [5b] and having an electrical length of 90 degrees at a center frequency [f0, par. 0042]; a second output circuit [8] connected to an output terminal of the second amplifier [6b] and having an electrical length of 180 degrees at a center frequency [par. 0044]; a third output circuit [7 in 42] connected to an output terminal of the third amplifier [5b] and having an electrical length of 90 degrees at a center frequency [par. 0042]; and a fourth output circuit [8 in 42] connected to an output terminal of the fourth amplifier [6b] and having an electrical length of 180 degrees at a center frequency [par. 0044], Nakatani does not explicitly disclose the amplification operation is performed in such a manner that: at a center frequency, the third amplifier operates when the input signal has low power, the first amplifier joins the operation when the input signal has medium power, and the second amplifier and the fourth amplifier join the operation when the input signal has high power, in a first frequency group, the first amplifier operates when the input signal has low power, the third amplifier joins the operation when the input signal has medium power, and the second amplifier and the fourth amplifier join the operation when the input signal has high power, in a second frequency group, the second amplifier operates when the input signal has low power, the fourth amplifier joins the operation when the input signal has medium power, and the first amplifier and the third amplifier join the operation when the input signal has high power, and in a third frequency group, the fourth amplifier operates when the input signal has low power, the second amplifier joins the operation when the input signal has medium power, and the first amplifier and the third amplifier join the operation when the input signal has high power.
However, Schmidt discloses an amplifier arrangement [see fig. 3 and par. 0045-0048] including multiple amplifier devices [e.g., 313/314/323/324] and switching logic [590] configure to activate a selected number of amplifiers based on the input signal power level in order to provide the desired output power with the minimal overall supply power consumption [par. 0048]. Schmidt teaches the switching logic determines which amplifier devices are switched on and off depending on the input signal and the required output power.
However, Schmidt does not explicitly disclose the particular sequence recited in the claim (i.e., at a center frequency, the third amplifier operates when the input signal has low power, the first amplifier joins the operation when the input signal has medium power, and the second amplifier and the fourth amplifier join the operation when the input signal has high power), (in a first frequency group, the first amplifier operates when the input signal has low power, the third amplifier joins the operation when the input signal has medium power, and the second amplifier and the fourth amplifier join the operation when the input signal has high power), (in a second frequency group, the second amplifier operates when the input signal has low power, the fourth amplifier joins the operation when the input signal has medium power, and the first amplifier and the third amplifier join the operation when the input signal has high power) and (in a third frequency group, the fourth amplifier operates when the input signal has low power, the second amplifier joins the operation when the input signal has medium power, and the first amplifier and the third amplifier join the operation when the input signal has high power).
However, the selection of the specific amplifier device activated at low, medium or high input power is considered a matter of obvious design choice. Schimdt already teaches activating any number of amplifier devices as needed to meet output power requirement while minimizing supply consumption. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify Nakatani Doherty amplifier by incorporating rearranging the activation order of the amplifier device to use in the sequence as claimed, since the claimed sequence does not produce a new or unexpected results beyond the power activation already taught by Schmidt.
Moreover, in the absence of any criticality (i.e. unobvious and/or unexpected result(s)), the parameter set forth above would have been obvious to a person having ordinary skill in the art at the time the invention was made, In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 2, Nakatani in view of Schmidt discloses further comprising a synthesis circuit [7/8, fig. 7 or 315/325/420, fig. 3] that is a tournament type synthesis circuit to stepwisely synthesize outputs of the amplifiers, the synthesis circuit having an asymmetric configuration as viewed from each of synthesis points.
Regarding claim 3, Nakatani in view of Schmidt discloses [fig. 7] further comprising a plurality of signal sources [signal sources from 2a and 2b] connected to the amplifiers, wherein biases of the amplifiers are fixed to threshold voltages of the amplifiers, respectively.
Regarding claim 5, Nakatani in view of Schmidt discloses wherein the synthesis circuit includes: a first small branch synthesis circuit [7/8/9, fig. 7 or a first module signal combiner 315, fig. 3] to bundle and output an output of the first amplifier and an output of the second amplifier; a second small branch synthesis circuit [7/8/9, fig. 7 or a second module signal combiner 325, fig. 3] to bundle and output an output of the third amplifier and an output of the fourth amplifier; and a large branch synthesis circuit [52, fig. 7 or 420] to bundle and output an output of the first small branch synthesis circuit and an output of the second small branch synthesis circuit.
Regarding claim 6, Nakatani in view of Schmidt discloses [fig. 7] wherein the first small branch synthesis circuit includes: the first output circuit [7 in 41] connected to the first amplifier and having an electrical length of 90 degrees [par. 0042] at a center frequency [f0]; and the second output circuit [8 in 41] connected to the second amplifier and having an electrical length of 180 degrees [par. 0044] at a center frequency, and the second small branch synthesis circuit includes: the third output circuit [7 in 42] connected to the third amplifier and having an electrical length of 90 degrees [par. 0042] at a center frequency; and the fourth output circuit [8 in 42] connected to the fourth amplifier and having an electrical length of 180 degrees [par, 0044] at a center frequency.
5. Claims 4, 8-9 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Nakatani et al. in view of Schmidt further in view of Marbell et al. (US 11967936 and Marbell hereinafter).
Regarding claim 4, Nakatani in view of Schmidt discloses all the features with respect to claim 2 as outlined above. Nakatani in view of Schmidt further comprising: one signal source [input signal, fig. 7]; a distribution circuit [51] to distribute a signal from the signal source to the first amplifier, the second amplifier, the third amplifier, and the fourth amplifier. Nakatani in view of Schmidt does not explicitly disclose a bias setting circuit to set biases of the first amplifier, the second amplifier, the third amplifier, and the fourth amplifier depending on the power and the frequency of the input signal.
However, Marbel discloses a bias setting circuit [BIAS, fig. 4A] to set biases of the first amplifier [114, fig. 5A], the second amplifier [115, fig. 5A], the third amplifier [115, fig. 5A], and the fourth amplifier [114, fig. 5A] depending on the power and the frequency of the input signal. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Nakatani in view of Schmidt by incorporating the bias control as taught in Marbel in order to bias the amplifiers of the respective circuit.
Regarding claim 8, Nakatani in view of Schmidt further in view of Marbel discloses wherein the synthesis circuit [fig. 3] includes: a first small branch synthesis circuit [315] to bundle and output an output of the first amplifier [313] and an output of the second amplifier [314]; a second small branch synthesis circuit [325] to bundle and output an output of the third amplifier [323] and an output of the fourth amplifier [324]; and a large branch synthesis circuit [420] to bundle and output an output of the first small branch synthesis circuit [output 315] and an output of the second small branch synthesis circuit [output 325].
Regarding claim 9, Nakatani in view of Schmidt further in view of Marbel discloses wherein the first small branch synthesis circuit [fig. 7] includes: the first output circuit [7 in 41] connected to the first amplifier and having an electrical length of 90 degrees at a center frequency [par. 0042]; and the second output circuit [8 in 41] connected to the second amplifier and having an electrical length of 180 degrees at a center frequency [par. 0044], and the second small branch synthesis circuit includes: the third output circuit [7 in 42] connected to the third amplifier and having an electrical length of 90 degrees at a center frequency [par. 0042]; and the fourth output circuit [8 in 42] connected to the fourth amplifier and having an electrical length of 180 degrees at a center frequency [par. 0044].
Regarding claim 11, Nakatani in view of Schmidt discloses all the features with respect to claim 1 as outlined above. Nakatani in view of Schmidt does not explicitly disclose comprising a bias control circuit to control a gate bias of the first amplifier, a gate bias of the second amplifier, a gate bias of the third amplifier, and a gate bias of the fourth amplifier depending on the power of the input signal.
However, Marbel discloses a bias control circuit [BIAS, fig. 4A] to control a gate bias of the first amplifier [114, fig. 5A], a gate bias of the second amplifier [115, fig. 5A], a gate bias of the third amplifier [115], and a gate bias of the fourth amplifier [115] depending on the power of the input signal. transistor. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Nakatani in view of Schmidt by incorporating the bias control as taught in Marbel in order to bias the amplifiers of the respective circuit.
Regarding claim 12, Nakatani in view of Schmidt discloses all the features with respect to claim 1 as outlined above. Nakatani in view of Schmidt does not explicitly disclose comprising a bias control circuit to control a drain bias of the first amplifier, a drain bias of the second amplifier, a drain bias of the third amplifier, and a drain bias of the fourth amplifier depending on the power of the input signal.
However, Marbel discloses a bias control circuit [BIAS, fig. 4A] to control a drain bias of the first amplifier [114, fig. 5A], a drain bias of the second amplifier [115, fig. 5A], a drain bias of the third amplifier [115, fig. 5A], and a drain bias of the fourth amplifier [115, fig. 5A] depending on the power of the input signal. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Nakatani in view of Schmidt by incorporating the bias control as taught in Marbel in order to bias the amplifiers of the respective circuit.
Conclusion
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/METASEBIA T RETEBO/ Primary Examiner, Art Unit 2836
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