DETAILED ACTION
Claims 1-20 are pending. Claims 1, 8, and 16 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Long!, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321 (c) or 1.321 (d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321 (b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit https://www.uspto.gov/patent/forms/forms-patent-applications-filed-or-after-september-16-2012. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to https://www.uspto.gov/patents-application-process/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-6, 8, and 10-19 of U.S. Patent No. 12,106,813 (‘813 patent). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims under examination are anticipated by claims 1-6, 8, and 10-19 of the ‘813 patent. Every limitation in the application under examination claims is recited in the conflicting reference patent claims, and the differences between the claims will be addressed below.
For example, the elements of claim 1 of the present application are patentably indistinct from the elements of claim 1 of the ‘813 patent. The proceeding table maps representative claim 1 from the instant application and the ‘813 patent.
Claim 1 of the Instant Application
Claim 1 of the ‘813 Patent
1. A method, comprising:
determining quality characteristics of a memory die, wherein the quality characteristics include a distance between a particular location on a wafer and a location at which the memory die was fabricated; and
performing a select gate scan operation by applying signaling to a select gate of the memory die, the signaling being altered based on the determined quality characteristics of the memory die.
1. A method, comprising:
determining, for a memory die, quality characteristics of the memory die, including:
determining a distance from a particular location on a wafer to a location at which the memory die was fabricated;
altering a threshold voltage applied to the memory die in performance of a select gate scan operation based, at least in part, on the determined quality characteristics of the memory die; and
performing the select gate scan operation by applying signaling having the altered threshold voltage to a select gate of the memory die.
As shown in the mapping above, claim 1 of the ‘813 patent includes all the limitations of claim 1 of the instant application, while also reciting further limitations. Thus, claim 1 of the ‘813 patent anticipates claim 1 of the instant application.
For example, the elements of claim 2 of the present application are patentably indistinct from the elements of claims 1 and 2 of the ‘813 patent. The proceeding table maps representative claim 2 from the instant application and claims 1 and 2 of the ‘813 patent.
Claim 2 of the Instant Application
Claims 1 and 2 of the ‘813 Patent
2. The method of claim 1, wherein the method includes performing the select gate scan operation according to a particular frequency.
1. A method, comprising:
determining, for a memory die, quality characteristics of the memory die, including:
determining a distance from a particular location on a wafer to a location at which the memory die was fabricated;
altering a threshold voltage applied to the memory die in performance of a select gate scan operation based, at least in part, on the determined quality characteristics of the memory die; and
performing the select gate scan operation by applying signaling having the altered threshold voltage to a select gate of the memory die.2. The method of claim 1, further comprising altering how frequently the select gate scan operation is performed based, at least in part, on the determined quality characteristics of the memory die.
As shown in the mapping above, claims 1 and 2 of the ‘813 patent includes all the limitations of claim 2 of the instant application, while also reciting further limitations. Thus, claims 1 and 2 of the ‘813 patent anticipates claim 2 of the instant application.
For example, the elements of claim 3 of the present application are patentably indistinct from the elements of claim 2 of the ‘813 patent. The proceeding table maps representative claim 3 from the instant application and claim 2 of the ‘813 patent.
Claim 3 of the Instant Application
Claim 2 of the ‘813 Patent
3. The method of claim 2, wherein the method includes altering the particular frequency based, at least in part, on the determined quality characteristics of the memory die.
2. The method of claim 1, further comprising altering how frequently the select gate scan operation is performed based, at least in part, on the determined quality characteristics of the memory die.
As shown in the mapping above, claim 2 of the ‘813 patent includes all the limitations of claim 3 of the instant application, while also reciting further limitations. Thus, claim 2 of the ‘813 patent anticipates claim 3 of the instant application.
For example, the elements of claim 4 of the present application are patentably indistinct from the elements of claim 3 of the ‘813 patent. The proceeding table maps representative claim 4 from the instant application and claim 3 the ‘813 patent.
Claim 4 of the Instant Application
Claim 3 of the ‘813 Patent
4. The method of claim 1, wherein the method includes:
determining, based on application of a modulated check failure byte signal, a fail bit criteria corresponding to the memory die;
determining the quality characteristics of the memory die based, at least in part, on the determined fail bit criteria; and
altering the signaling applied to the select gate in performance of the select gate scan operation or how frequently the select gate scan operation is performed, or both, based, at least in part, on the determined quality characteristics of the memory die.
3. The method of claim 1, further comprising:
determining, based on application of a modulated check failure byte signal, a fail bit criteria corresponding to the memory die;
determining the quality characteristics of the memory die based, at least in part, on the determined fail bit criteria; and
altering the threshold voltage applied to the memory die in performance of the select gate scan operation or how frequently the select gate scan operation is performed, or both, based, at least in part, on the determined quality characteristics of the memory die.
As shown in the mapping above, claim 3 of the ‘813 patent includes all the limitations of claim 4 of the instant application, while also reciting further limitations. Thus, claim 3 of the ‘813 patent anticipates claim 4 of the instant application.
For example, the elements of claim 5 of the present application are patentably indistinct from the elements of claim 4 of the ‘813 patent. The proceeding table maps representative claim 5 from the instant application and claim 4 the ‘813 patent.
Claim 5 of the Instant Application
Claim 4 of the ‘813 Patent
5. The method of claim 1, wherein the method includes:
determining, based on application of a modulated read level signal, characteristics associated with a tail region of a voltage threshold corresponding to the select gate of the memory die;
determining the quality characteristics of the memory die based, at least in part, on the characteristics associated with the tail region of a threshold voltage distribution corresponding to the select gate; and
altering the signaling applied to the select gate in performance of the select gate scan operation or how frequently the select gate scan operation is performed, or both, based, at least in part, on the determined quality characteristics of the memory die.
4. The method of claim 1, further comprising:
determining, based on application of a modulated read level signal, characteristics associated with a tail region of a voltage threshold corresponding to the select gate of the memory die;
determining the quality characteristics of the memory die based, at least in part, on the characteristics associated with the tail region of the voltage threshold corresponding to the select gate; and
altering the threshold voltage applied to the memory die in performance of the select gate scan operation or how frequently the select gate scan operation is performed, or both, based, at least in part, on the determined quality characteristics of the memory die.
As shown in the mapping above, claim 4 of the ‘813 patent includes all the limitations of claim 5 of the instant application, while also reciting further limitations. Thus, claim 4 of the ‘813 patent anticipates claim 5 of the instant application.
For example, the elements of claim 6 of the present application are patentably indistinct from the elements of claim 5 of the ‘813 patent. The proceeding table maps representative claim 6 from the instant application and claim 5 of the ‘813 patent.
Claim 6 of the Instant Application
Claim 5 of the ‘813 Patent
6. The method of claim 1, wherein the method includes determining the quality characteristics of the memory die during runtime of a memory device associated with the memory die.
5. The method of claim 1, further comprising determining the quality characteristics of the memory die during runtime of a memory device associated with the memory die.
As shown in the mapping above, claim 5 of the ‘813 patent includes all the limitations of claim 6 of the instant application, while also reciting further limitations. Thus, claim 5 of the ‘813 patent anticipates claim 6 of the instant application.
For example, the elements of claim 7 of the present application are patentably indistinct from the elements of claim 6 of the ‘813patent. The proceeding table maps representative claim 7 from the instant application and claim 6 of the ‘813 patent.
Claim 7 of the Instant Application
Claim 6 of the ‘813 Patent
7. The method of claim 1, further comprising:
determining a quantity of program erase cycles experienced by the memory die;
altering the signaling applied to the select gate in performance of the select gate scan operation or how frequently the select gate scan operation is performed, or both, based, at least in part, on the determined quantity of program erase cycles experienced by the memory die; and
performing the select gate scan operation by applying the altered signaling to the select gate of the memory die or altering the frequency at which the select gate scan operation is performed, or both, based, at least in part, on the determined quantity of program erase cycles experienced by the memory die.
6. The method of claim 1, further comprising:
determining a quantity of program erase cycles experienced by the memory die;
altering the threshold voltage applied to the memory die in performance of the select gate scan operation or how frequently the select gate scan operation is performed, or both, based, at least in part, on the determined quantity of program erase cycles experienced by the memory die; and
performing the select gate scan operation by applying the signaling having the altered threshold voltage to the select gate of the memory die or altering the frequency at which the select gate scan operation is performed, or both, based, at least in part, on the determined quantity of program erase cycles experienced by the memory die.
As shown in the mapping above, claim 6 of the ‘813 patent includes all the limitations of claim 7 of the instant application, while also reciting further limitations. Thus, claim 6 of the ‘813 patent anticipates claim 7 of the instant application.
For example, the elements of claim 8 of the present application are patentably indistinct from the elements of claim 8 of the ‘813 patent. The proceeding table maps representative claim 8 from the instant application and the ‘813 patent.
Claim 8 of the Instant Application
Claim 8 of the ‘813 Patent
8. An apparatus, comprising:
a memory device including a memory die;
a select gate coupled to at least one string of memory cells of the memory die; and
a processor coupled to the memory device, wherein the processor is configured to:
determine quality characteristics of the memory die;
based, at least in part, on the determined quality characteristics of the memory die, alter signaling applied to the select gate in performance of a select gate scan operation such that a frequency of performance of the select gate scan operation is altered; and
perform the select gate scan operation using the altered signaling.
8. An apparatus, comprising:
a memory die resident on a memory device;
a select gate coupled to at least one string of memory cells of the memory die; and
a processor coupled to the memory device, wherein the processor is configured to:
determine quality characteristics of the memory die;
alter signaling applied to the select gate in performance of a select gate scan operation based, at least in part, on the determined quality characteristics of the memory die, wherein the signaling is altered such that the select gate scan operation is performed more frequently or less frequently than prior to the signaling being altered; and
perform the select gate scan operation using the altered signaling.
As shown in the mapping above, claim 8 of the ‘813 patent includes all the limitations of claim 8 of the instant application, while also reciting further limitations. Thus, claim 8 of the ‘813 patent anticipates claim 8 of the instant application.
For example, the elements of claim 9 of the present application are patentably indistinct from the elements of claim 8 of the ‘813 patent. The proceeding table maps representative claim 9 from the instant application and claim 8 of the ‘813 patent.
Claim 9 of the Instant Application
Claim 8 of the ‘813 Patent
9. The apparatus of claim 8, wherein the signaling is altered such that the select gate scan operation is performed at a greater frequency than prior to the signaling being altered.
8. An apparatus, comprising:
a memory die resident on a memory device;
a select gate coupled to at least one string of memory cells of the memory die; and
a processor coupled to the memory device, wherein the processor is configured to:
determine quality characteristics of the memory die;
alter signaling applied to the select gate in performance of a select gate scan operation based, at least in part, on the determined quality characteristics of the memory die, wherein the signaling is altered such that the select gate scan operation is performed more frequently or less frequently than prior to the signaling being altered; and
perform the select gate scan operation using the altered signaling.
As shown in the mapping above, claim 8 of the ‘813 patent includes all the limitations of claim 9 of the instant application, while also reciting further limitations. Thus, claim 8 of the ‘813 patent anticipates claim 9 of the instant application.
For example, the elements of claim 10 of the present application are patentably indistinct from the elements of claim 8 of the ‘813 patent. The proceeding table maps representative claim 10 from the instant application and claim 8 of the ‘813 patent.
Claim 10 of the Instant Application
Claim 8 of the ‘813 Patent
10. The apparatus of claim 8, wherein the signaling is altered such that the select gate scan operation is performed at a lesser frequency than prior to the signaling being altered.
8. An apparatus, comprising:
a memory die resident on a memory device;
a select gate coupled to at least one string of memory cells of the memory die; and
a processor coupled to the memory device, wherein the processor is configured to:
determine quality characteristics of the memory die;
alter signaling applied to the select gate in performance of a select gate scan operation based, at least in part, on the determined quality characteristics of the memory die, wherein the signaling is altered such that the select gate scan operation is performed more frequently or less frequently than prior to the signaling being altered; and
perform the select gate scan operation using the altered signaling.
As shown in the mapping above, claim 8 of the ‘813 patent includes all the limitations of claim 10 of the instant application, while also reciting further limitations. Thus, claim 8 of the ‘813 patent anticipates claim 10 of the instant application.
For example, the elements of claim 11 of the present application are patentably indistinct from the elements of claim 10 of the ‘813 patent. The proceeding table maps representative claim 11 from the instant application and claim 10 the ‘813 patent.
Claim 11 of the Instant Application
Claim 10 of the ‘813 Patent
11. The apparatus of claim 8, wherein the quality characteristics include a physical location at which the memory die was fabricated on a wafer.
10. The apparatus of claim 8, wherein the quality characteristics are based, at least in part, on a physical location at which the memory die was fabricated on a wafer.
As shown in the mapping above, claim 10 of the ‘813 patent includes all the limitations of claim 2 of the instant application, while also reciting further limitations. Thus, claim 2 of the ‘813 patent anticipates claim 2 of the instant application.
For example, the elements of claim 12 of the present application are patentably indistinct from the elements of claim 11 of the ‘813 patent. The proceeding table maps representative claim 12 from the instant application and claim 11 of the ‘813 patent.
Claim 12 of the Instant Application
Claim 11 of the ‘813 Patent
12. The apparatus of claim 8, wherein the quality characteristics include doping profile variations associated with the memory die resulting from memory die fabrication processes.
11. The apparatus of claim 8, wherein the quality characteristics are based, at least in part, on doping profile variations associated with the memory die as a result of memory die fabrication processes.
As shown in the mapping above, claim 11 of the ‘813 patent includes all the limitations of claim 12 of the instant application, while also reciting further limitations. Thus, claim 11 of the ‘813 patent anticipates claim 12 of the instant application.
For example, the elements of claim 13 of the present application are patentably indistinct from the elements of claim 12 of the ‘813patent. The proceeding table maps representative claim 13 from the instant application and claim 12 of the ‘813 patent.
Claim 13 of the Instant Application
Claim 12 of the ‘813 Patent
13. The apparatus of claim 8, wherein the processor is configured to:
determine a slope of a portion of a voltage threshold exhibited by the select gate during operation of the memory device; and
alter the signaling applied to the select gate in performance of the select gate scan operation based, at least in part, on the determined slope.
12. The apparatus of claim 8, wherein the processor is further configured to:
determine a slope of a portion of a voltage threshold exhibited by the select gate during operation of the memory device; and
alter the signaling applied to the select gate in performance of the select gate scan operation based, at least in part, on the determined slope of the portion of the voltage threshold exhibited by the select gate during operation of the memory device.
As shown in the mapping above, claim 12 of the ‘813 patent includes all the limitations of claim 13 of the instant application, while also reciting further limitations. Thus, claim 12 of the ‘813 patent anticipates claim 13 of the instant application.
For example, the elements of claim 14 of the present application are patentably indistinct from the elements of claim 13 of the ‘813 patent. The proceeding table maps representative claim 14 from the instant application and claim 13 of the ‘813 patent.
Claim 14 of the Instant Application
Claim 13 of the ‘813 Patent
14. The apparatus of claim 8, wherein the processor is configured to alter the signaling applied to the select gate in performance of the select gate scan operation based, at least in part, on a fail bit criteria exhibited by the select gate during operation of the memory device.
13. The apparatus of claim 8, wherein the processor is further configured to:
determine a slope of a portion of a voltage threshold exhibited by the select gate during operation of the memory device; and
alter the signaling applied to the select gate in performance of the select gate scan operation based, at least in part, on a fail bit criteria exhibited by the select gate during operation of the memory device.
As shown in the mapping above, claim 13 of the ‘813 patent includes all the limitations of claim 14 of the instant application, while also reciting further limitations. Thus, claim 13 of the ‘813 patent anticipates claim 14 of the instant application.
For example, the elements of claim 15 of the present application are patentably indistinct from the elements of claim 14 of the ‘813 patent. The proceeding table maps representative claim 15 from the instant application and claim 14 of the ‘813 patent.
Claim 15 of the Instant Application
Claim 14 of the ‘813 Patent
15. The apparatus of claim 8, wherein the processor is configured to:
determine a quantity of bit failures exhibited by the select gate during operation of the memory device; and
alter the signaling applied to the select gate in performance of the select gate scan operation based, at least in part, on the determined quantity of bit failures.
14. The apparatus of claim 8, wherein the processor is further configured to:
determine a quantity of bit failures exhibited by the select gate during operation of the memory device; and
alter the signaling applied to the select gate in performance of the select gate scan operation based, at least in part, on the determined quantity of bit failures exhibited by the select gate during operation of the memory device.
As shown in the mapping above, claim 14 of the ‘813 patent includes all the limitations of claim 15 of the instant application, while also reciting further limitations. Thus, claim 14 of the ‘813 patent anticipates claim 15 of the instant application.
For example, the elements of claim 16 of the present application are patentably indistinct from the elements of claim 15 of the ‘813 patent. The proceeding table maps representative claim 16 from the instant application and claim 15 of the ‘813 patent.
Claim 16 of the Instant Application
Claim 15 of the ‘813 Patent
16. A system, comprising:
a plurality of memory dice resident on a memory device;
select gates respectively coupled to strings of memory cells of respective memory dice of the plurality of memory dice; and
a processor coupled to the plurality of memory dice, wherein the processor is configured to:
determine quality characteristics of each memory die of the plurality of memory dice based, at least in part, on a physical location on a wafer at which each memory die was fabricated;
assign a ranking value to each memory die of the plurality of memory dice based on the determined quality characteristics;
alter a select gate scan operation involving one of the select gates based, at least in part, on the assigned ranking values; and
cause performance of the altered select gate scan operation.
15. A system, comprising:
a plurality of memory dice resident on a memory device;
respective select gates coupled to respective strings of memory cells of respective memory dice of the plurality of memory dice; and
a processor coupled to the plurality of memory dice, wherein the processor is configured to:
determine quality characteristics of each memory die of the plurality of memory dice, wherein the quality characteristics are based, at least in part, on a physical location on a wafer at which each memory die was fabricated;
assign a ranking value to each memory die of the plurality of memory dice based on the determined quality characteristics of each memory die;
alter parameters associated with signaling indicative of a select gate scan operation involving at least one of the respective select gates based, at least in part, on the assigned ranking values; and
cause performance of the select gate scan operation involving the at least one of the respective select gates using the altered parameters associated with the signaling indicative of the select gate scan operation involving the at least one of the respective select gates.
As shown in the mapping above, claim 15 of the ‘813 patent includes all the limitations of claim 16 of the instant application, while also reciting further limitations. Thus, claim 15 of the ‘813 patent anticipates claim 16 of the instant application.
For example, the elements of claim 17 of the present application are patentably indistinct from the elements of claim 16 of the ‘813 patent. The proceeding table maps representative claim 17 from the instant application and claim 16 of the ‘813 patent.
Claim 17 of the Instant Application
Claim 16 of the ‘813 Patent
17. The system of claim 16, wherein the processor is configured to alter the select gate scan operation by altering how frequently the select gate scan operation is performed.
16. The system of claim 15, wherein the processor is configured to alter the parameters associated with the signaling indicative of the select gate scan operation by altering how frequently the select gate scan operation is performed involving the at least one the respective select gates.
As shown in the mapping above, claim 16 of the ‘813 patent includes all the limitations of claim 17 of the instant application, while also reciting further limitations. Thus, claim 16 of the ‘813 patent anticipates claim 17 of the instant application.
For example, the elements of claim 18 of the present application are patentably indistinct from the elements of claim 17 of the ‘813 patent. The proceeding table maps representative claim 18 from the instant application and claim 17 the ‘813 patent.
Claim 18 of the Instant Application
Claim 17 of the ‘813 Patent
18. The system of claim 16, wherein the processor is configured to alter the select gate scan operation by altering a voltage threshold applied to the one of the select gates during performance of the select gate scan operation.
17. The system of claim 15, wherein the processor is configured to alter the parameters associated with the signaling indicative of the select gate scan operation by altering a voltage threshold applied to the at least one the respective select gates during performance of the select gate scan operation.
As shown in the mapping above, claim 17 of the ‘813 patent includes all the limitations of claim 18 of the instant application, while also reciting further limitations. Thus, claim 17 of the ‘813 patent anticipates claim 18 of the instant application.
For example, the elements of claim 19 of the present application are patentably indistinct from the elements of claim 18 of the ‘813 patent. The proceeding table maps representative claim 19 from the instant application and claim 18 of the ‘813 patent.
Claim 19 of the Instant Application
Claim 18 of the ‘813 Patent
19. The system of claim 16, wherein the processor is configured to:
monitor a slope associated with a portion of a voltage distribution associated with a voltage threshold of the one of the select gates; and
alter the select gate scan operation based on the monitored slope.
18. The system of claim 15, wherein the processor is further configured to:
monitor a slope associated with a portion of a voltage distribution associated with a voltage threshold of the at least one of the respective select gates; and
alter the parameters associated with the signaling indicative of the select gate scan operation involving the at least one of the respective select gates based on the monitored slope of the portion of the voltage distribution associated with the voltage threshold of the at least one of the respective select gates.
As shown in the mapping above, claim 18 of the ‘813 patent includes all the limitations of claim 19 of the instant application, while also reciting further limitations. Thus, claim 18 of the ‘813 patent anticipates claim 19 of the instant application.
For example, the elements of claim 20 of the present application are patentably indistinct from the elements of claim 19 of the ‘813 patent. The proceeding table maps representative claim 20 from the instant application and claim 19 of the ‘813 patent.
Claim 20 of the Instant Application
Claim 19 of the ‘813 Patent
20. The system of claim 16, wherein the processor is configured to:
monitor a quantity of bit failures detected in a particular time period for the one of the select gates; and
alter the select gate scan operation based on the monitored quantity of bit failures detected.
19. The system of claim 15, wherein the processor is further configured to:
monitor a quantity of bit failures detected in a particular time period for the at least one of the respective select gates; and
alter the parameters associated with the signaling indicative of the select gate scan operation involving the at least one of the respective select gates based on the monitored quantity of bit failures detected in the particular time period for the at least one of the respective select gates.
As shown in the mapping above, claim 19 of the ‘813 patent includes all the limitations of claim 20 of the instant application, while also reciting further limitations. Thus, claim 19 of the ‘813 patent anticipates claim 20 of the instant application.
Claim Rejections - 35 USC § 103
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 6-7, 16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2004/0029306 to Subramanian (“Subramanian”) in view of U.S. Publication No. 2014/0226416 to Li et al. ("Li").
Regarding claim 1, Subramanian teaches:
A method, comprising:
determining quality characteristics of a memory die, wherein the quality characteristics include a distance between a particular location on a wafer and a location at which the memory die was fabricated (Subramanian: Paragraph [0003], “A wafer map is a set of information that is used by process equipment when handling a wafer at its workstation. The map data includes the coordinates of each die on a wafer, bin assignments for good dies and reject dies, wafer orientation or rotation, and the wafer identification that is used to associate the wafer map with the physical wafer”; Paragraphs [0038]-[0053], “Move the wafer table manually to the reference die location and teach the position. Read and Store the wafer table Reference die X and Y coordinates. Perform neighborhood learning. For neighborhood learning the following information is used to form the neighborhood matrix. See FIG. 1 1—Good pattern die and align 2—Good pattern die and align failed 3—Partial pattern die 4—Partial mirror die 5—Mirror die 6—Plug die 7—No die 8—Ink die 9—Exceed wafer diameter 10—Exceed wafer table limit 11—Edge of wafer 12—Edge of wafer table”; Paragraph [0059], “Move the wafer table one die up to a die to the left of the reference die and gather information and update the neighborhood matrix. It is a good die and so a 1 is recorded”; wherein Subramanian teaches that each die’s x,y coordinates are stored relative to a reference die location. Under BRI this establishes a distance metric which is x,y coordinate compared to a reference die so that will be physical distance compared to a particular location);
However, Subramanian does not appear to explicitly teach:
performing a select gate scan operation by applying signaling to a select gate of the memory die, the signaling being altered based on the determined quality characteristics of the memory die.
However, in the same field of endeavor, Li teaches:
performing a select gate scan operation by applying signaling to a select gate of the memory die, the signaling being altered based on the determined quality characteristics of the memory die (Li: Paragraph [0051], “the first step of the erase portion ramps nodes 1000 and 1008 from 0 V to Vsg. Node 1002 is set at a relatively high level which passes Vsg to nodes 1004 and 1006. The second step of the erase portion maintains Vsg at node 1000 and ramps the voltage at node 1008 from Vsg to Verase>Vsg. Vsg can be adjusted and synchronized relative to Vsl/Vbl and Vsgd/Vsgs. In this case, Vdg=Vbl-Vcg=Verase-Vsg. In case of multiple erase-verify iterations, Verase can be stepped up by a predefined step size, Verase-step. Moreover, Vsg can also be adjusted by a step size Vsg-step depending on the degradation of the select gates. In one approach, Vsg-step is higher when a number of program-erase cycles is higher”; Paragraph [0095], “select gate voltages for a selected sub-block in an erase operation in accordance with one embodiment of step 510 of FIG. 5A, where a level of the select gate voltages steps up for each erase-verify iteration. For example, the select gate voltages 561-568 are Vsg0-Vsg7, respectively. In one approach, the step size Vsg-step is the same as Verase-step, so that the drain-to-gate voltage of the select gate is constant in the different erase-verify iterations. By stepping up the select gate voltage with the erase voltage, increasingly higher drain-to-gate voltage differences across the select gates are avoided”; Paragraph [0052], “the step-up may begin based on a number of program-erase cycles which the memory device or portion thereof (e.g., block) has experienced”; wherein the scan is explicitly shown by a plurality of step ups in voltages which is equivalent to a gate scan and is particularly applied select gates; wherein the alteration is the manipulation of the voltage thresholds applied in the thresholds which is interpreted by the stepping/ramping of voltage; wherein this occurs based on a health status which would be obvious to be combined with Subramanian’s health/quality values which are based on the distances which by the transitive property makes the alteration based on the distances).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by Subramanian by altering a select gate scan signal, as taught by Li. One of ordinary skill in the art would have been motivated to use the methods of Li because it would eliminate higher drain-to-gate voltage differences across select gates. (Li: Paragraph [0095]).
Regarding claim 6, the Subramanian/Li combination teaches all of the elements of claim 1 and further teaches:
wherein the method includes determining the quality characteristics of the memory die during runtime of a memory device associated with the memory die (Li: Paragraph [0051], “the first step of the erase portion ramps nodes 1000 and 1008 from 0 V to Vsg. Node 1002 is set at a relatively high level which passes Vsg to nodes 1004 and 1006. The second step of the erase portion maintains Vsg at node 1000 and ramps the voltage at node 1008 from Vsg to Verase>Vsg. Vsg can be adjusted and synchronized relative to Vsl/Vbl and Vsgd/Vsgs. In this case, Vdg=Vbl-Vcg=Verase-Vsg. In case of multiple erase-verify iterations, Verase can be stepped up by a predefined step size, Verase-step. Moreover, Vsg can also be adjusted by a step size Vsg-step depending on the degradation of the select gates. In one approach, Vsg-step is higher when a number of program-erase cycles is higher”; Paragraph [0095], “select gate voltages for a selected sub-block in an erase operation in accordance with one embodiment of step 510 of FIG. 5A, where a level of the select gate voltages steps up for each erase-verify iteration. For example, the select gate voltages 561-568 are Vsg0-Vsg7, respectively. In one approach, the step size Vsg-step is the same as Verase-step, so that the drain-to-gate voltage of the select gate is constant in the different erase-verify iterations. By stepping up the select gate voltage with the erase voltage, increasingly higher drain-to-gate voltage differences across the select gates are avoided”; Paragraph [0052], “the step-up may begin based on a number of program-erase cycles which the memory device or portion thereof (e.g., block) has experienced”; wherein the increase in voltage is directly stemming from a quantity of program-erase cycles and because of this it must be done at runtime. Therefore, running a select gate scan despite the quality characteristics, but arguendo, health status would be obvious to be ran at runtime for the benefits as seen by program cycle erasure quantity).
Regarding claim 7, the Subramanian/Li combination teaches all of the elements of claim 1 and further teaches:
determining a quantity of program erase cycles experienced by the memory die (Li: Paragraph [0051], “the first step of the erase portion ramps nodes 1000 and 1008 from 0 V to Vsg. Node 1002 is set at a relatively high level which passes Vsg to nodes 1004 and 1006. The second step of the erase portion maintains Vsg at node 1000 and ramps the voltage at node 1008 from Vsg to Verase>Vsg. Vsg can be adjusted and synchronized relative to Vsl/Vbl and Vsgd/Vsgs. In this case, Vdg=Vbl-Vcg=Verase-Vsg. In case of multiple erase-verify iterations, Verase can be stepped up by a predefined step size, Verase-step. Moreover, Vsg can also be adjusted by a step size Vsg-step depending on the degradation of the select gates. In one approach, Vsg-step is higher when a number of program-erase cycles is higher”; Paragraph [0095], “select gate voltages for a selected sub-block in an erase operation in accordance with one embodiment of step 510 of FIG. 5A, where a level of the select gate voltages steps up for each erase-verify iteration. For example, the select gate voltages 561-568 are Vsg0-Vsg7, respectively. In one approach, the step size Vsg-step is the same as Verase-step, so that the drain-to-gate voltage of the select gate is constant in the different erase-verify iterations. By stepping up the select gate voltage with the erase voltage, increasingly higher drain-to-gate voltage differences across the select gates are avoided”; Paragraph [0052], “the step-up may begin based on a number of program-erase cycles which the memory device or portion thereof (e.g., block) has experienced”; wherein the increase in voltage is directly stemming from a quantity of program-erase cycles);
altering the signaling applied to the select gate in performance of the select gate scan operation or how frequently the select gate scan operation is performed, or both, based, at least in part, on the determined quantity of program erase cycles experienced by the memory die (Li: Paragraph [0051], “the first step of the erase portion ramps nodes 1000 and 1008 from 0 V to Vsg. Node 1002 is set at a relatively high level which passes Vsg to nodes 1004 and 1006. The second step of the erase portion maintains Vsg at node 1000 and ramps the voltage at node 1008 from Vsg to Verase>Vsg. Vsg can be adjusted and synchronized relative to Vsl/Vbl and Vsgd/Vsgs. In this case, Vdg=Vbl-Vcg=Verase-Vsg. In case of multiple erase-verify iterations, Verase can be stepped up by a predefined step size, Verase-step. Moreover, Vsg can also be adjusted by a step size Vsg-step depending on the degradation of the select gates. In one approach, Vsg-step is higher when a number of program-erase cycles is higher”; Paragraph [0095], “select gate voltages for a selected sub-block in an erase operation in accordance with one embodiment of step 510 of FIG. 5A, where a level of the select gate voltages steps up for each erase-verify iteration. For example, the select gate voltages 561-568 are Vsg0-Vsg7”; Paragraph [0052], “the step-up may begin based on a number of program-erase cycles which the memory device or portion thereof (e.g., block) has experienced”; wherein the increase in voltage is directly stemming from a quantity of program-erase cycles); and
performing the select gate scan operation by applying the altered signaling to the select gate of the memory die or altering the frequency at which the select gate scan operation is performed, or both, based, at least in part, on the determined quantity of program erase cycles experienced by the memory die (Li: Paragraph [0088], “An erase operation can be initiated by control circuitry of the memory device independently of an external host controller, or in response to an external host controller, for instance”; Paragraph [0095], “Paragraph [0095], “select gate voltages for a selected sub-block in an erase operation in accordance with one embodiment of step 510 of FIG. 5A, where a level of the select gate voltages steps up for each erase-verify iteration. For example, the select gate voltages 561-568 are Vsg0-Vsg7, respectively”; wherein the altered scan with dynamic voltage thresholds based on step increases of the program erase cycles isn’t just defined by the controller but it is actually executed using the stepped-vsg sequence; the based on program erase cycles fueled the alteration as seen in the element above as well).
Regarding claim 16, Subramanian teaches:
determine quality characteristics of each memory die of the plurality of memory dice based, at least in part, on a physical location on a wafer at which each memory die was fabricated (Subramanian: Paragraph [0003], “A wafer map is a set of information that is used by process equipment when handling a wafer at its workstation. The map data includes the coordinates of each die on a wafer, bin assignments for good dies and reject dies, wafer orientation or rotation, and the wafer identification that is used to associate the wafer map with the physical wafer”; Paragraphs [0039]-[0053], “Move the wafer table manually to the reference die location and teach the position. Read and Store the wafer table Reference die X and Y coordinates. Perform neighborhood learning. For neighborhood learning the following information is used to form the neighborhood matrix. See FIG. 1 1—Good pattern die and align 2—Good pattern die and align failed 3—Partial pattern die 4—Partial mirror die 5—Mirror die 6—Plug die 7—No die 8—Ink die 9—Exceed wafer diameter 10—Exceed wafer table limit 11—Edge of wafer 12—Edge of wafer table”; Paragraph [0059], “Move the wafer table one die up to a die to the left of the reference die and gather information and update the neighborhood matrix. It is a good die and so a 1 is recorded”; wherein a quality characteristic is based at least partially on the location in the wafer map (x,y coordinates));
assign a ranking value to each memory die of the plurality of memory dice based on the determined quality characteristics (Subramanian: Paragraph [0003], “A wafer map is a set of information that is used by process equipment when handling a wafer at its workstation. The map data includes the coordinates of each die on a wafer, bin assignments for good dies and reject dies, wafer orientation or rotation, and the wafer identification that is used to associate the wafer map with the physical wafer”; Paragraphs [0039]-[0053], “Move the wafer table manually to the reference die location and teach the position. Read and Store the wafer table Reference die X and Y coordinates. Perform neighborhood learning. For neighborhood learning the following information is used to form the neighborhood matrix. See FIG. 1 1—Good pattern die and align 2—Good pattern die and align failed 3—Partial pattern die 4—Partial mirror die 5—Mirror die 6—Plug die 7—No die 8—Ink die 9—Exceed wafer diameter 10—Exceed wafer table limit 11—Edge of wafer 12—Edge of wafer table”; Paragraph [0059], “Move the wafer table one die up to a die to the left of the reference die and gather information and update the neighborhood matrix. It is a good die and so a 1 is recorded”; wherein a quality characteristic is based on the location in the wafer map (x,y coordinates); wherein based on the status a numerical ranking value is assigned to each memory die, such as 1-12 based on quality);
However, Subramanian does not appear to explicitly teach:
a plurality of memory dice resident on a memory device;
select gates respectively coupled to strings of memory cells of respective memory dice of the plurality of memory dice; and
a processor coupled to the plurality of memory dice, wherein the processor is configured to:
alter a select gate scan operation involving one of the select gates based, at least in part, on the assigned ranking values; and
cause performance of the altered select gate scan operation.
However, in the same field of endeavor, Li teaches:
a plurality of memory dice resident on a memory device (Li: Paragraph [0056], “The memory device 100 may include one or more memory die 108. The memory die 108 includes a 3D (three-dimensional) memory array of storage elements 150”);
select gates respectively coupled to strings of memory cells of respective memory dice of the plurality of memory dice (Li: Paragraph [0048], “In one approach, the memory device includes NAND strings which have a drain-side select gate (SGD) on one end and a source-side select gate (SGS) on the other end”); and
a processor coupled to the plurality of memory dice (Li: Paragraph [0056], “Typically a controller 150 is included in the same memory device 100 (e.g., a removable storage card) as the one or more memory die 108. Commands and data are transferred between the host and controller 150 via lines 120 and between the controller and the one or more memory die 108 via lines 118”), wherein the processor is configured to:
alter a select gate scan operation involving one of the select gates based, at least in part, on the assigned ranking values (Li: Paragraph [0051], “the first step of the erase portion ramps nodes 1000 and 1008 from 0 V to Vsg. Node 1002 is set at a relatively high level which passes Vsg to nodes 1004 and 1006. The second step of the erase portion maintains Vsg at node 1000 and ramps the voltage at node 1008 from Vsg to Verase>Vsg. Vsg can be adjusted and synchronized relative to Vsl/Vbl and Vsgd/Vsgs. In this case, Vdg=Vbl-Vcg=Verase-Vsg. In case of multiple erase-verify iterations, Verase can be stepped up by a predefined step size, Verase-step. Moreover, Vsg can also be adjusted by a step size Vsg-step depending on the degradation of the select gates. In one approach, Vsg-step is higher when a number of program-erase cycles is higher”; Paragraph [0095], “select gate voltages for a selected sub-block in an erase operation in accordance with one embodiment of step 510 of FIG. 5A, where a level of the select gate voltages steps up for each erase-verify iteration. For example, the select gate voltages 561-568 are Vsg0-Vsg7, respectively. In one approach, the step size Vsg-step is the same as Verase-step, so that the drain-to-gate voltage of the select gate is constant in the different erase-verify iterations. By stepping up the select gate voltage with the erase voltage, increasingly higher drain-to-gate voltage differences across the select gates are avoided”; Paragraph [0052], “the step-up may begin based on a number of program-erase cycles which the memory device or portion thereof (e.g., block) has experienced”; wherein the scan is explicitly shown by a plurality of step ups in voltages which is equivalent to a gate scan and is particularly applied select gates; wherein the alteration is the manipulation of the voltage thresholds applied in the thresholds which is interpreted by the stepping/ramping of voltage; wherein this occurs based on a health status which would be obvious to be combined with Subramanian’s ranking values of health/quality); and
cause performance of the altered select gate scan operation (Li: Paragraph [0088], “An erase operation can be initiated by control circuitry of the memory device independently of an external host controller, or in response to an external host controller, for instance”; Paragraph [0095], “Paragraph [0095], “select gate voltages for a selected sub-block in an erase operation in accordance with one embodiment of step 510 of FIG. 5A, where a level of the select gate voltages steps up for each erase-verify iteration. For example, the select gate voltages 561-568 are Vsg0-Vsg7, respectively”; wherein the altered scan based on voltage thresholds isn’t just defined by the controller but it is actually executed using the stepped-vsg sequence).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by Subramanian by altering a select gate scan signal, as taught by Li. One of ordinary skill in the art would have been motivated to use the methods of Li because it would eliminate higher drain-to-gate voltage differences across select gates. (Li: Paragraph [0095]).
Regarding claim 18, the Subramanian/Li combination teaches all of the elements of claim 16 and further teaches:
wherein the processor is configured to alter the select gate scan operation by altering a voltage threshold applied to the one of the select gates during performance of the select gate scan operation (Li: Paragraph [0051], “the first step of the erase portion ramps nodes 1000 and 1008 from 0 V to Vsg. Node 1002 is set at a relatively high level which passes Vsg to nodes 1004 and 1006. The second step of the erase portion maintains Vsg at node 1000 and ramps the voltage at node 1008 from Vsg to Verase>Vsg. Vsg can be adjusted and synchronized relative to Vsl/Vbl and Vsgd/Vsgs. In this case, Vdg=Vbl-Vcg=Verase-Vsg. In case of multiple erase-verify iterations, Verase can be stepped up by a predefined step size, Verase-step. Moreover, Vsg can also be adjusted by a step size Vsg-step depending on the degradation of the select gates. In one approach, Vsg-step is higher when a number of program-erase cycles is higher”; Paragraph [0095], “select gate voltages for a selected sub-block in an erase operation in accordance with one embodiment of step 510 of FIG. 5A, where a level of the select gate voltages steps up for each erase-verify iteration. For example, the select gate voltages 561-568 are Vsg0-Vsg7, respectively. In one approach, the step size Vsg-step is the same as Verase-step, so that the drain-to-gate voltage of the select gate is constant in the different erase-verify iterations. By stepping up the select gate voltage with the erase voltage, increasingly higher drain-to-gate voltage differences across the select gates are avoided”; Paragraph [0052], “the step-up may begin based on a number of program-erase cycles which the memory device or portion thereof (e.g., block) has experienced”; wherein the scan is explicitly shown by a plurality of step ups in voltages which is equivalent to a gate scan and is particularly applied select gates; wherein the alteration is the manipulation of the voltage thresholds applied in the thresholds which is interpreted by the stepping/ramping of voltage; wherein this occurs based on a health status which would be obvious to be combined with Subramanian’s ranking values of health/quality).
Claims 2-3 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Subramanian in view of Li and further in view of U.S. Publication No. 2011/0055468 to Gonzalez et al. ("Gonzalez").
Regarding claim 2, the Subramanian/Li combination teaches all of the elements of claim 1. However, the combination does not appear to teach:
wherein the method includes performing the select gate scan operation according to a particular frequency.
However, in the same field of endeavor, Gonzalez teaches:
wherein the method includes performing the select gate scan operation according to a particular frequency (Gonzalez: Paragraph [0017], “the scrubbing operation may be made adaptive to the integrity of the data read. For example, if one or a threshold level of data errors is found in one region of the memory cell array, the rate of scrubbing in that region may be increased. Conversely, if no errors or only a few data errors less than a threshold are found in a given region, this allows lowering the rate of scrubbing of the given region. The frequency and location of scrub may also be adapted to usage levels and other system parameters. These and other features of scrub are calculated to provide a balance between the need to maintain data integrity and the need to maintain a high level of system performance”; wherein scan operations (scrubs) are executed at an adjustable frequency depending on device health (number of errors). it would be obvious to combine Gonzalez to the Subramanian/Li combination as they both address the retention and endurance failures in NAND and are both based on quantity of errors).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by the Subramanian/Li combination by adjusting the frequency of the scan, as taught by Gonzalez. One of ordinary skill in the art would have been motivated to use the methods of Gonzalez because it would overall improve system performance by limiting operations. (Gonzalez: Paragraph [0054]).
Regarding claim 3, the Subramanian/Li/Gonzalez combination teaches all of the elements of claim 2 and further teaches:
wherein the method includes altering the particular frequency based, at least in part, on the determined quality characteristics of the memory die (Gonzalez: Paragraph [0017], “the scrubbing operation may be made adaptive to the integrity of the data read. For example, if one or a threshold level of data errors is found in one region of the memory cell array, the rate of scrubbing in that region may be increased. Conversely, if no errors or only a few data errors less than a threshold are found in a given region, this allows lowering the rate of scrubbing of the given region. The frequency and location of scrub may also be adapted to usage levels and other system parameters. These and other features of scrub are calculated to provide a balance between the need to maintain data integrity and the need to maintain a high level of system performance”; wherein scan operations (scrubs) are executed at an adjustable frequency depending on device health (number of errors). it would be obvious to combine Gonzalez to the Subramanian/Li combination as they both address the retention and endurance failures in NAND and are both based on quantity of errors).
Regarding claim 17, the Subramanian/Li combination teaches all of the elements of claim 16. However, the combination does not appear to teach:
wherein the processor is configured to alter the select gate scan operation by altering how frequently the select gate scan operation is performed.
However, in the same field of endeavor, Gonzalez teaches:
wherein the processor is configured to alter the select gate scan operation by altering how frequently the select gate scan operation is performed (Gonzalez: Paragraph [0017], “the scrubbing operation may be made adaptive to the integrity of the data read. For example, if one or a threshold level of data errors is found in one region of the memory cell array, the rate of scrubbing in that region may be increased. Conversely, if no errors or only a few data errors less than a threshold are found in a given region, this allows lowering the rate of scrubbing of the given region. The frequency and location of scrub may also be adapted to usage levels and other system parameters. These and other features of scrub are calculated to provide a balance between the need to maintain data integrity and the need to maintain a high level of system performance”; wherein scan operations (scrubs) are executed at an adjustable frequency depending on device health (number of errors). it would be obvious to combine Gonzalez to the Subramanian/Li combination as they both address the retention and endurance failures in NAND and are both based on quantity of errors).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by the Subramanian/Li combination by adjusting the frequency of the scan, as taught by Gonzalez. One of ordinary skill in the art would have been motivated to use the methods of Gonzalez because it would overall improve system performance by limiting operations. (Gonzalez: Paragraph [0054]).
Claims 4 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Subramanian in view of Li and further in view of U.S. Publication No. 2010/0031096 to Di Iorio et al. ("Di Iorio").
Regarding claim 4, the Subramanian/Li combination teaches all of the elements of claim 1 and further teaches:
altering the signaling applied to the select gate in performance of the select gate scan operation or how frequently the select gate scan operation is performed, or both, based, at least in part, on the determined quality characteristics of the memory die (Li: Paragraph [0051], “the first step of the erase portion ramps nodes 1000 and 1008 from 0 V to Vsg. Node 1002 is set at a relatively high level which passes Vsg to nodes 1004 and 1006. The second step of the erase portion maintains Vsg at node 1000 and ramps the voltage at node 1008 from Vsg to Verase>Vsg. Vsg can be adjusted and synchronized relative to Vsl/Vbl and Vsgd/Vsgs. In this case, Vdg=Vbl-Vcg=Verase-Vsg. In case of multiple erase-verify iterations, Verase can be stepped up by a predefined step size, Verase-step. Moreover, Vsg can also be adjusted by a step size Vsg-step depending on the degradation of the select gates. In one approach, Vsg-step is higher when a number of program-erase cycles is higher”; Paragraph [0095], “select gate voltages for a selected sub-block in an erase operation in accordance with one embodiment of step 510 of FIG. 5A, where a level of the select gate voltages steps up for each erase-verify iteration. For example, the select gate voltages 561-568 are Vsg0-Vsg7, respectively. In one approach, the step size Vsg-step is the same as Verase-step, so that the drain-to-gate voltage of the select gate is constant in the different erase-verify iterations. By stepping up the select gate voltage with the erase voltage, increasingly higher drain-to-gate voltage differences across the select gates are avoided”; Paragraph [0052], “the step-up may begin based on a number of program-erase cycles which the memory device or portion thereof (e.g., block) has experienced”; wherein the scan is explicitly shown by a plurality of step ups in voltages which is equivalent to a gate scan and is particularly applied select gates; wherein the alteration is the manipulation of the voltage thresholds applied in the thresholds which is interpreted by the stepping/ramping of voltage; wherein this occurs based on a health status which would be obvious to be combined with Subramanian’s health/quality values which are based on the distances which by the transitive property makes the alteration based on the distances).
However, the combination does not appear to teach:
determining, based on application of a modulated check failure byte signal, a fail bit criteria corresponding to the memory die;
determining the quality characteristics of the memory die based, at least in part, on the determined fail bit criteria;
However, in the same field of endeavor, Di Iorio teaches:
determining, based on application of a modulated check failure byte signal, a fail bit criteria corresponding to the memory die (Di Iorio: Paragraph [0015], “According to a particular embodiment, during programming, verification circuitry may evaluate bits in a byte and generate a failed byte signal if at least one bit of a byte has not been correctly programmed. According to a particular embodiment, circuit 100 may count the number of failing bytes, notifying a memory controller whether the number of failing bytes exceeds a tolerated amount of fails (K)”);
determining the quality characteristics of the memory die based, at least in part, on the determined fail bit criteria (Di Iorio: Paragraph [0015], “According to a particular embodiment, during programming, verification circuitry may evaluate bits in a byte and generate a failed byte signal if at least one bit of a byte has not been correctly programmed. According to a particular embodiment, circuit 100 may count the number of failing bytes, notifying a memory controller whether the number of failing bytes exceeds a tolerated amount of fails (K)”; wherein quality characteristics would be the health of die and this could be combined with the Subramanian/Li combination because both are triggered based on a health/degradation threshold in which a need to run a select gate scan would be needed and would enjoy the benefits of Di Iorio); and
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by the Subramanian/Li combination by using fail bit criteria from a failure byte signal, as taught by Di Iorio. One of ordinary skill in the art would have been motivated to use the methods of Di Iorio because it would assist in alerting the system when a tolerable amount of errors have occurred and therefore would allow the system to resolve any issues when they arise. (Di Iorio: Paragraph [0015]).
Regarding claim 20, the Subramanian/Li combination teaches all of the elements of claim 16 and further teaches:
alter the select gate scan operation (Li: Paragraph [0051], “the first step of the erase portion ramps nodes 1000 and 1008 from 0 V to Vsg. Node 1002 is set at a relatively high level which passes Vsg to nodes 1004 and 1006. The second step of the erase portion maintains Vsg at node 1000 and ramps the voltage at node 1008 from Vsg to Verase>Vsg. Vsg can be adjusted and synchronized relative to Vsl/Vbl and Vsgd/Vsgs. In this case, Vdg=Vbl-Vcg=Verase-Vsg. In case of multiple erase-verify iterations, Verase can be stepped up by a predefined step size, Verase-step. Moreover, Vsg can also be adjusted by a step size Vsg-step depending on the degradation of the select gates. In one approach, Vsg-step is higher when a number of program-erase cycles is higher”; Paragraph [0095], “select gate voltages for a selected sub-block in an erase operation in accordance with one embodiment of step 510 of FIG. 5A, where a level of the select gate voltages steps up for each erase-verify iteration. For example, the select gate voltages 561-568 are Vsg0-Vsg7, respectively. In one approach, the step size Vsg-step is the same as Verase-step, so that the drain-to-gate voltage of the select gate is constant in the different erase-verify iterations. By stepping up the select gate voltage with the erase voltage, increasingly higher drain-to-gate voltage differences across the select gates are avoided”; Paragraph [0052], “the step-up may begin based on a number of program-erase cycles which the memory device or portion thereof (e.g., block) has experienced”; wherein the scan is explicitly shown by a plurality of step ups in voltages which is equivalent to a gate scan and is particularly applied select gates; wherein the alteration is the manipulation of the voltage thresholds applied in the thresholds which is interpreted by the stepping/ramping of voltage; wherein this occurs based on a health status which would be obvious to be combined with Subramanian’s health/quality values).
However, the combination does not appear to teach:
monitor a quantity of bit failures detected in a particular time period for the one of the select gates;
based on the monitored quantity of bit failures detected.
However, in the same field of endeavor, Di Iorio teaches:
monitor a quantity of bit failures detected in a particular time period for the one of the select gates (Di Iorio: Paragraph [0015], “According to a particular embodiment, during programming, verification circuitry may evaluate bits in a byte and generate a failed byte signal if at least one bit of a byte has not been correctly programmed. According to a particular embodiment, circuit 100 may count the number of failing bytes, notifying a memory controller whether the number of failing bytes exceeds a tolerated amount of fails (K)”; wherein the particular time period is during the programming);
based on the monitored quantity of bit failures detected (Di Iorio: Paragraph [0015], “According to a particular embodiment, during programming, verification circuitry may evaluate bits in a byte and generate a failed byte signal if at least one bit of a byte has not been correctly programmed. According to a particular embodiment, circuit 100 may count the number of failing bytes, notifying a memory controller whether the number of failing bytes exceeds a tolerated amount of fails (K)”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by the Subramanian/Li combination by using count of bit failures, as taught by Di Iorio. One of ordinary skill in the art would have been motivated to use the methods of Di Iorio because it would assist in alerting the system when a tolerable amount of errors have occurred and therefore would allow the system to resolve any issues when they arise. (Di Iorio: Paragraph [0015]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Subramanian in view of Li and further in view of U.S. Publication No. 2018/0075919 to Pang et al. ("Pang").
Regarding claim 5, the Subramanian/Li combination teaches all of the elements of claim 1 and further teaches:
altering the signaling applied to the select gate in performance of the select gate scan operation or how frequently the select gate scan operation is performed, or both, based, at least in part, on the determined quality characteristics of the memory die (Li: Paragraph [0051], “the first step of the erase portion ramps nodes 1000 and 1008 from 0 V to Vsg. Node 1002 is set at a relatively high level which passes Vsg to nodes 1004 and 1006. The second step of the erase portion maintains Vsg at node 1000 and ramps the voltage at node 1008 from Vsg to Verase>Vsg. Vsg can be adjusted and synchronized relative to Vsl/Vbl and Vsgd/Vsgs. In this case, Vdg=Vbl-Vcg=Verase-Vsg. In case of multiple erase-verify iterations, Verase can be stepped up by a predefined step size, Verase-step. Moreover, Vsg can also be adjusted by a step size Vsg-step depending on the degradation of the select gates. In one approach, Vsg-step is higher when a number of program-erase cycles is higher”; Paragraph [0095], “select gate voltages for a selected sub-block in an erase operation in accordance with one embodiment of step 510 of FIG. 5A, where a level of the select gate voltages steps up for each erase-verify iteration. For example, the select gate voltages 561-568 are Vsg0-Vsg7, respectively. In one approach, the step size Vsg-step is the same as Verase-step, so that the drain-to-gate voltage of the select gate is constant in the different erase-verify iterations. By stepping up the select gate voltage with the erase voltage, increasingly higher drain-to-gate voltage differences across the select gates are avoided”; Paragraph [0052], “the step-up may begin based on a number of program-erase cycles which the memory device or portion thereof (e.g., block) has experienced”; wherein the scan is explicitly shown by a plurality of step ups in voltages which is equivalent to a gate scan and is particularly applied to select gates; wherein the alteration is the manipulation of the voltage thresholds applied in the thresholds which is interpreted by the stepping/ramping of voltage; wherein this occurs based on a health status which would be obvious to be combined with Pang’s quality characteristics and corrective action) such that a frequency of performance of the select gate scan operation is altered (Gonzalez: Paragraph [0017], “he scrubbing operation may be made adaptive to the integrity of the data read. For example, if one or a threshold level of data errors is found in one region of the memory cell array, the rate of scrubbing in that region may be increased. Conversely, if no errors or only a few data errors less than a threshold are found in a given region, this allows lowering the rate of scrubbing of the given region. The frequency and location of scrub may also be adapted to usage levels and other system parameters. These and other features of scrub are calculated to provide a balance between the need to maintain data integrity and the need to maintain a high level of system performance”; wherein scan operations (scrubs) are executed at an adjustable frequency depending on device health (number of errors). it would be obvious to combine Gonzalez to Li as they both address the retention and endurance failures in NAND and are both based on quantity of errors).
However, the combination does not appear to teach:
wherein the method includes:
determining, based on application of a modulated read level signal, characteristics associated with a tail region of a voltage threshold corresponding to the select gate of the memory die;
determining the quality characteristics of the memory die based, at least in part, on the characteristics associated with the tail region of a threshold voltage distribution corresponding to the select gate;
However, in the same field of endeavor, Pang teaches:
wherein the method includes:
determining, based on application of a modulated read level signal, characteristics associated with a tail region of a voltage threshold corresponding to the select gate of the memory die (Pang: Paragraph [0050], “The evaluation of the dummy memory cells can involve sensing the dummy memory cells using a demarcation voltage and counting a number of the dummy memory cells which have a threshold voltage below the demarcation voltage”; wherein the modulated read level signal can be the demarcation voltage and the counting of cells with voltage below a threshold would be equivalent to the probing the tail of the distribution with a modulated read signal; wherein it is a read as well in order to “poke” at the edge/tail of the Vth distribution);
determining the quality characteristics of the memory die based, at least in part, on the characteristics associated with the tail region of a threshold voltage distribution corresponding to the select gate (Pang: Paragraph [0149], “A decision step 1302 determines whether the number of dummy memory cells which have a Vth<Vdem is more than a specified number N. If this is true, step 1303 performs a corrective action for the associated data memory cells”; wherein the count determined as the characteristic is compared to a threshold and provides a quality/health factor that determines if something needs to be done which could be combined with Li which uses a degradation/health factor to determine if altering of a select gate scan voltage is necessary);
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by the Subramanian/Li combination by looking at tail regions of voltage threshold and determining quality characteristics based on the tail region of voltage distribution, as taught by Pang. One of ordinary skill in the art would have been motivated to use the methods of Pang because it assists in detecting when a corrective action needs to occur and in combination with Subramanian/Li would allow it to detect when to make the adjustments to the scan. (Pang: Paragraphs [0050] and [0149]).
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Li and further in view of Gonzalez.
Regarding claim 8, Li teaches:
An apparatus, comprising:
a memory device including a memory die (Li: Paragraph [0056], “The memory device 100 may include one or more memory die 108. The memory die 108 includes a 3D (three-dimensional) memory array of storage elements 150”);
a select gate coupled to at least one string of memory cells of the memory die (Li: Paragraph [0048], “In one approach, the memory device includes NAND strings which have a drain-side select gate (SGD) on one end and a source-side select gate (SGS) on the other end”); and
a processor coupled to the memory device, wherein the processor is configured to (Li: Paragraph [0056], “Typically a controller 150 is included in the same memory device 100 (e.g., a removable storage card) as the one or more memory die 108. Commands and data are transferred between the host and controller 150 via lines 120 and between the controller and the one or more memory die 108 via lines 118”):
determine quality characteristics of the memory die (Li: Paragraph [0051], “the first step of the erase portion ramps nodes 1000 and 1008 from 0 V to Vsg. Node 1002 is set at a relatively high level which passes Vsg to nodes 1004 and 1006. The second step of the erase portion maintains Vsg at node 1000 and ramps the voltage at node 1008 from Vsg to Verase>Vsg. Vsg can be adjusted and synchronized relative to Vsl/Vbl and Vsgd/Vsgs. In this case, Vdg=Vbl-Vcg=Verase-Vsg. In case of multiple erase-verify iterations, Verase can be stepped up by a predefined step size, Verase-step. Moreover, Vsg can also be adjusted by a step size Vsg-step depending on the degradation of the select gates. In one approach, Vsg-step is higher when a number of program-erase cycles is higher”; Paragraph [0095], “select gate voltages for a selected sub-block in an erase operation in accordance with one embodiment of step 510 of FIG. 5A, where a level of the select gate voltages steps up for each erase-verify iteration. For example, the select gate voltages 561-568 are Vsg0-Vsg7, respectively. In one approach, the step size Vsg-step is the same as Verase-step, so that the drain-to-gate voltage of the select gate is constant in the different erase-verify iterations. By stepping up the select gate voltage with the erase voltage, increasingly higher drain-to-gate voltage differences across the select gates are avoided”; Paragraph [0052], “the step-up may begin based on a number of program-erase cycles which the memory device or portion thereof (e.g., block) has experienced”; wherein the scan is explicitly shown by a plurality of step ups in voltages which is equivalent to a gate scan and is particularly applied select gates; wherein the alteration is the manipulation of the voltage thresholds applied in the thresholds which is interpreted by the stepping/ramping of voltage; wherein this occurs based on a health status which would be obvious to be combined with Subramanian’s ranking values of health/quality);
based, at least in part, on the determined quality characteristics of the memory die, alter signaling applied to the select gate in performance of a select gate scan operation(Li: Paragraph [0051], “the first step of the erase portion ramps nodes 1000 and 1008 from 0 V to Vsg. Node 1002 is set at a relatively high level which passes Vsg to nodes 1004 and 1006. The second step of the erase portion maintains Vsg at node 1000 and ramps the voltage at node 1008 from Vsg to Verase>Vsg. Vsg can be adjusted and synchronized relative to Vsl/Vbl and Vsgd/Vsgs. In this case, Vdg=Vbl-Vcg=Verase-Vsg. In case of multiple erase-verify iterations, Verase can be stepped up by a predefined step size, Verase-step. Moreover, Vsg can also be adjusted by a step size Vsg-step depending on the degradation of the select gates. In one approach, Vsg-step is higher when a number of program-erase cycles is higher”; Paragraph [0095], “select gate voltages for a selected sub-block in an erase operation in accordance with one embodiment of step 510 of FIG. 5A, where a level of the select gate voltages steps up for each erase-verify iteration. For example, the select gate voltages 561-568 are Vsg0-Vsg7, respectively. In one approach, the step size Vsg-step is the same as Verase-step, so that the drain-to-gate voltage of the select gate is constant in the different erase-verify iterations. By stepping up the select gate voltage with the erase voltage, increasingly higher drain-to-gate voltage differences across the select gates are avoided”; Paragraph [0052], “the step-up may begin based on a number of program-erase cycles which the memory device or portion thereof (e.g., block) has experienced”; wherein the scan is explicitly shown by a plurality of step ups in voltages which is equivalent to a gate scan and is particularly applied select gates; wherein the alteration is the manipulation of the voltage thresholds applied in the thresholds which is interpreted by the stepping/ramping of voltage; wherein this occurs based on a health status which would be obvious to be combined with Subramanian’s ranking values of health/quality)
perform the select gate scan operation using the altered signaling (Li: Paragraph [0088], “An erase operation can be initiated by control circuitry of the memory device independently of an external host controller, or in response to an external host controller, for instance”; Paragraph [0095], “Paragraph [0095], “select gate voltages for a selected sub-block in an erase operation in accordance with one embodiment of step 510 of FIG. 5A, where a level of the select gate voltages steps up for each erase-verify iteration. For example, the select gate voltages 561-568 are Vsg0-Vsg7, respectively”; wherein the altered scan based on voltage thresholds isn’t just defined by the controller but it is actually executed using the stepped-vsg sequence).
However, Li does not appear to explicitly teach:
such that a frequency of performance of the select gate scan operation is altered;
However, in the same field of endeavor, Gonzalez teaches:
such that a frequency of performance of the select gate scan operation is altered (Gonzalez: Paragraph [0017], “he scrubbing operation may be made adaptive to the integrity of the data read. For example, if one or a threshold level of data errors is found in one region of the memory cell array, the rate of scrubbing in that region may be increased. Conversely, if no errors or only a few data errors less than a threshold are found in a given region, this allows lowering the rate of scrubbing of the given region. The frequency and location of scrub may also be adapted to usage levels and other system parameters. These and other features of scrub are calculated to provide a balance between the need to maintain data integrity and the need to maintain a high level of system performance”; wherein scan operations (scrubs) are executed at an adjustable frequency depending on device health (number of errors). it would be obvious to combine Gonzalez to Li as they both address the retention and endurance failures in NAND and are both based on quantity of errors); and
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by Li by adjusting the frequency of the scan, as taught by Gonzalez. One of ordinary skill in the art would have been motivated to use the methods of Gonzalez because it would overall improve system performance by limiting operations. (Gonzalez: Paragraph [0054]).
Regarding claim 9, the Li/Gonzalez combination teaches all of the elements of claim 8 and further teaches:
wherein the signaling is altered such that the select gate scan operation is performed at a greater frequency than prior to the signaling being altered (Gonzalez: Paragraph [0017], “he scrubbing operation may be made adaptive to the integrity of the data read. For example, if one or a threshold level of data errors is found in one region of the memory cell array, the rate of scrubbing in that region may be increased. Conversely, if no errors or only a few data errors less than a threshold are found in a given region, this allows lowering the rate of scrubbing of the given region. The frequency and location of scrub may also be adapted to usage levels and other system parameters. These and other features of scrub are calculated to provide a balance between the need to maintain data integrity and the need to maintain a high level of system performance”; wherein scan operations (scrubs) are executed at an adjustable frequency depending on device health (number of errors). it would be obvious to combine Gonzalez to Li as they both address the retention and endurance failures in NAND and are both based on quantity of errors).
Regarding claim 10, the Li/Gonzalez combination teaches all of the elements of claim 8 and further teaches:
wherein the signaling is altered such that the select gate scan operation is performed at a lesser frequency than prior to the signaling being altered (Gonzalez: Paragraph [0017], “he scrubbing operation may be made adaptive to the integrity of the data read. For example, if one or a threshold level of data errors is found in one region of the memory cell array, the rate of scrubbing in that region may be increased. Conversely, if no errors or only a few data errors less than a threshold are found in a given region, this allows lowering the rate of scrubbing of the given region. The frequency and location of scrub may also be adapted to usage levels and other system parameters. These and other features of scrub are calculated to provide a balance between the need to maintain data integrity and the need to maintain a high level of system performance”; wherein scan operations (scrubs) are executed at an adjustable frequency depending on device health (number of errors). it would be obvious to combine Gonzalez to Li as they both address the retention and endurance failures in NAND and are both based on quantity of errors).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Gonzalez and further in view of Subramanian.
Regarding claim 11, the Li/Gonalez combination teaches all of the elements of claim 8. However, the combination does not teach:
wherein the quality characteristics include a physical location at which the memory die was fabricated on a wafer.
However, in the same field of endeavor, Subramanian teaches:
wherein the quality characteristics include a physical location at which the memory die was fabricated on a wafer (Subramanian: Paragraph [0003], “A wafer map is a set of information that is used by process equipment when handling a wafer at its workstation. The map data includes the coordinates of each die on a wafer, bin assignments for good dies and reject dies, wafer orientation or rotation, and the wafer identification that is used to associate the wafer map with the physical wafer”; Paragraphs [0038]-[0053], “Move the wafer table manually to the reference die location and teach the position. Read and Store the wafer table Reference die X and Y coordinates. Perform neighborhood learning. For neighborhood learning the following information is used to form the neighborhood matrix. See FIG. 1 1—Good pattern die and align 2—Good pattern die and align failed 3—Partial pattern die 4—Partial mirror die 5—Mirror die 6—Plug die 7—No die 8—Ink die 9—Exceed wafer diameter 10—Exceed wafer table limit 11—Edge of wafer 12—Edge of wafer table”; Paragraph [0059], “Move the wafer table one die up to a die to the left of the reference die and gather information and update the neighborhood matrix. It is a good die and so a 1 is recorded”; wherein Subramanian teaches that each die’s x,y coordinates are stored relative to a reference die location. Under BRI this establishes a distance metric which is x,y coordinate compared to a reference die so that will be physical distance compared to a particular location).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by the Li/Gonzalez combination by using a physical location of dies on a wafer as quality characteristics, as taught by Subramanian. One of ordinary skill in the art would have been motivated to use the methods of Subramanian because it would improve efficiency of detecting issues with the wafer and dies and therefore will assist in bettering the system. (Subramanian: Paragraphs [0002]-[0008] and Abstract).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Gonzalez and further in view of U.S. Publication No. 2012/0068754 to Su et al. (“Su”).
Regarding claim 12, the Li/Gonzalez combination teaches all of the elements of claim 8. However, the combination does not appear to teach:
wherein the quality characteristics include doping profile variations associated with the memory die resulting from memory die fabrication processes.
However, in the same field of endeavor, Su teaches:
wherein the quality characteristics include doping profile variations associated with the memory die resulting from memory die fabrication processes (Su: Paragraph [0032], “For example, gate oxide thickness variation, channel doping concentration variation, and the like, can cause transistor threshold variation. The transistor threshold variation then causes transistor-switching delay variation”; wherein doping profile variations is equivalent to channel doping concentration variation; wherein Su teaches that doping variation affects electrical behavior; wherein this characteristic would be beneficial to quality/health; therefore it would be obvious to combine with the corrective actions as a corrective action could be determined with this quality characteristic).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by the Li/Gonzalez combination by doping profiles variations to detect when quality may be impacted and would need a solution, as taught by Su. One of ordinary skill in the art would have been motivated to use the methods of Su because it would improve design cycles as well as allowing certain power targets to be hit. (Su: Paragraphs [0002]-[0003]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Gonzalez and further in view of U.S. Publication No. 2023/0148366 to Guo (“Guo”).
Regarding claim 13, the Li/Gonzalez combination teaches all of the elements of claim 8. However, the combination does not appear to teach:
wherein the processor is configured to:
determine a slope of a portion of a voltage threshold exhibited by the select gate during operation of the memory device; and
alter the signaling applied to the select gate in performance of the select gate scan operation based, at least in part, on the determined slope.
However, in the same field of endeavor, Guo teaches:
wherein the processor is configured to:
determine a slope of a portion of a voltage threshold exhibited by the select gate during operation of the memory device (Guo: Paragraph [0131], “As an example, the memory device may be programmed in an Incremental Step Pulse Programming (ISPP) manner. It should be pointed out that when the step and/or the programming voltage slope changes, the change speed of the threshold voltage of a memory cell would also change, so the value ranges of the second preset value and the second preset ratio can be adjusted correspondingly”; Paragraph [0134], “the step and/or the programming voltage slope of the incremental step pulse programming is obtained, and the value range of the second preset value is determined according to the step and/or the programming voltage slope; or, the value range of the second preset ratio is determined according to the step and/or the programming voltage slope. In this way, the value range of the second preset value and the value range of the second preset ratio can be flexibly adjusted, and the slow programming speed caused by improper setting of the second preset value and the second preset ratio can be reduced, thus improving the programming speed, and reducing the programming quality”; wherein the slope of voltages is determined; also the incremental step pulse programming can actually be interpreted as a select gate scan as the voltage is increased incrementally similar to a gate scan); and
alter the signaling applied to the select gate in performance of the select gate scan operation based, at least in part, on the determined slope (Guo: Paragraph [0131], “As an example, the memory device may be programmed in an Incremental Step Pulse Programming (ISPP) manner. It should be pointed out that when the step and/or the programming voltage slope changes, the change speed of the threshold voltage of a memory cell would also change, so the value ranges of the second preset value and the second preset ratio can be adjusted correspondingly”; Paragraph [0134], “the step and/or the programming voltage slope of the incremental step pulse programming is obtained, and the value range of the second preset value is determined according to the step and/or the programming voltage slope; or, the value range of the second preset ratio is determined according to the step and/or the programming voltage slope. In this way, the value range of the second preset value and the value range of the second preset ratio can be flexibly adjusted, and the slow programming speed caused by improper setting of the second preset value and the second preset ratio can be reduced, thus improving the programming speed, and reducing the programming quality”; wherein the slope of voltages is determined; also the incremental step pulse programming can actually be interpreted as a select gate scan as the voltage is increased incrementally similar to a gate scan; wherein finally the signaling is altered based on the determination of slope).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by the Li/Gonzalez combination by using slope of a voltage threshold distribution to determine a need to adjust, as taught by Guo. One of ordinary skill in the art would have been motivated to use the methods of Guo because it would improve the time for verification and ensuring quality is a urgent problem to be solved. (Guo: Paragraph [0004]).
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Gonzalez and further in view of Di Iorio.
Regarding claim 14, the Li/Gonzalez combination teaches all of the elements of claim 8 and further teaches:
wherein the processor is configured to alter the signaling applied to the select gate in performance of the select gate scan operation (Li: Paragraph [0051], “the first step of the erase portion ramps nodes 1000 and 1008 from 0 V to Vsg. Node 1002 is set at a relatively high level which passes Vsg to nodes 1004 and 1006. The second step of the erase portion maintains Vsg at node 1000 and ramps the voltage at node 1008 from Vsg to Verase>Vsg. Vsg can be adjusted and synchronized relative to Vsl/Vbl and Vsgd/Vsgs. In this case, Vdg=Vbl-Vcg=Verase-Vsg. In case of multiple erase-verify iterations, Verase can be stepped up by a predefined step size, Verase-step. Moreover, Vsg can also be adjusted by a step size Vsg-step depending on the degradation of the select gates. In one approach, Vsg-step is higher when a number of program-erase cycles is higher”; Paragraph [0095], “select gate voltages for a selected sub-block in an erase operation in accordance with one embodiment of step 510 of FIG. 5A, where a level of the select gate voltages steps up for each erase-verify iteration. For example, the select gate voltages 561-568 are Vsg0-Vsg7, respectively. In one approach, the step size Vsg-step is the same as Verase-step, so that the drain-to-gate voltage of the select gate is constant in the different erase-verify iterations. By stepping up the select gate voltage with the erase voltage, increasingly higher drain-to-gate voltage differences across the select gates are avoided”; Paragraph [0052], “the step-up may begin based on a number of program-erase cycles which the memory device or portion thereof (e.g., block) has experienced”; wherein the scan is explicitly shown by a plurality of step ups in voltages which is equivalent to a gate scan and is particularly applied select gates; wherein the alteration is the manipulation of the voltage thresholds applied in the thresholds which is interpreted by the stepping/ramping of voltage; wherein this occurs based on a health status which would be obvious to be combined with Subramanian’s health/quality values)
However, the combination does not appear to teach:
based, at least in part, on a fail bit criteria exhibited by the select gate during operation of the memory device.
However, in the same field of endeavor, Di Iorio teaches:
based, at least in part, on a fail bit criteria exhibited by the select gate during operation of the memory device (Di Iorio: Paragraph [0015], “According to a particular embodiment, during programming, verification circuitry may evaluate bits in a byte and generate a failed byte signal if at least one bit of a byte has not been correctly programmed. According to a particular embodiment, circuit 100 may count the number of failing bytes, notifying a memory controller whether the number of failing bytes exceeds a tolerated amount of fails (K)”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by the Li/Gonzalez combination by using fail bit criteria from a failure byte signal, as taught by Di Iorio. One of ordinary skill in the art would have been motivated to use the methods of Di Iorio because it would assist in alerting the system when a tolerable amount of errors have occurred and therefore would allow the system to resolve any issues when they arise. (Di Iorio: Paragraph [0015]).
Regarding claim 15, the Li/Gonzalez combination teaches all of the elements of claim 8 and further teaches:
alter the signaling applied to the select gate in performance of the select gate scan operation (Li: Paragraph [0051], “the first step of the erase portion ramps nodes 1000 and 1008 from 0 V to Vsg. Node 1002 is set at a relatively high level which passes Vsg to nodes 1004 and 1006. The second step of the erase portion maintains Vsg at node 1000 and ramps the voltage at node 1008 from Vsg to Verase>Vsg. Vsg can be adjusted and synchronized relative to Vsl/Vbl and Vsgd/Vsgs. In this case, Vdg=Vbl-Vcg=Verase-Vsg. In case of multiple erase-verify iterations, Verase can be stepped up by a predefined step size, Verase-step. Moreover, Vsg can also be adjusted by a step size Vsg-step depending on the degradation of the select gates. In one approach, Vsg-step is higher when a number of program-erase cycles is higher”; Paragraph [0095], “select gate voltages for a selected sub-block in an erase operation in accordance with one embodiment of step 510 of FIG. 5A, where a level of the select gate voltages steps up for each erase-verify iteration. For example, the select gate voltages 561-568 are Vsg0-Vsg7, respectively. In one approach, the step size Vsg-step is the same as Verase-step, so that the drain-to-gate voltage of the select gate is constant in the different erase-verify iterations. By stepping up the select gate voltage with the erase voltage, increasingly higher drain-to-gate voltage differences across the select gates are avoided”; Paragraph [0052], “the step-up may begin based on a number of program-erase cycles which the memory device or portion thereof (e.g., block) has experienced”; wherein the scan is explicitly shown by a plurality of step ups in voltages which is equivalent to a gate scan and is particularly applied select gates; wherein the alteration is the manipulation of the voltage thresholds applied in the thresholds which is interpreted by the stepping/ramping of voltage; wherein this occurs based on a health status which would be obvious to be combined with Subramanian’s health/quality values)
However, the combination does not appear to teach:
determine a quantity of bit failures exhibited by the select gate during operation of the memory device;
based, at least in part, on the determined quantity of bit failures;
However, in the same field of endeavor, Di Iorio teaches:
determine a quantity of bit failures exhibited by the select gate during operation of the memory device (Di Iorio: Paragraph [0015], “According to a particular embodiment, during programming, verification circuitry may evaluate bits in a byte and generate a failed byte signal if at least one bit of a byte has not been correctly programmed. According to a particular embodiment, circuit 100 may count the number of failing bytes, notifying a memory controller whether the number of failing bytes exceeds a tolerated amount of fails (K)”)
based, at least in part, on the determined quantity of bit failures (Di Iorio: Paragraph [0015], “According to a particular embodiment, during programming, verification circuitry may evaluate bits in a byte and generate a failed byte signal if at least one bit of a byte has not been correctly programmed. According to a particular embodiment, circuit 100 may count the number of failing bytes, notifying a memory controller whether the number of failing bytes exceeds a tolerated amount of fails (K)”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by the Li/Gonzalez combination by using fail bit criteria from a failure byte signal, as taught by Di Iorio. One of ordinary skill in the art would have been motivated to use the methods of Di Iorio because it would assist in alerting the system when a tolerable amount of errors have occurred and therefore would allow the system to resolve any issues when they arise. (Di Iorio: Paragraph [0015]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Subramanian in view of Li and further in view of Guo.
Regarding claim 19, the Subramanian/Li combination teaches all of the elements of claim 16. However, the combination does not appear to teach:
wherein the processor is configured to:
monitor a slope associated with a portion of a voltage distribution associated with a voltage threshold of the one of the select gates; and
alter the select gate scan operation based on the monitored slope.
However, in the same field of endeavor, Guo teaches:
wherein the processor is configured to:
monitor a slope associated with a portion of a voltage distribution associated with a voltage threshold of the one of the select gates (Guo: Paragraph [0131], “As an example, the memory device may be programmed in an Incremental Step Pulse Programming (ISPP) manner. It should be pointed out that when the step and/or the programming voltage slope changes, the change speed of the threshold voltage of a memory cell would also change, so the value ranges of the second preset value and the second preset ratio can be adjusted correspondingly”; Paragraph [0134], “the step and/or the programming voltage slope of the incremental step pulse programming is obtained, and the value range of the second preset value is determined according to the step and/or the programming voltage slope; or, the value range of the second preset ratio is determined according to the step and/or the programming voltage slope. In this way, the value range of the second preset value and the value range of the second preset ratio can be flexibly adjusted, and the slow programming speed caused by improper setting of the second preset value and the second preset ratio can be reduced, thus improving the programming speed, and reducing the programming quality”; wherein the slope of voltages is determined; also the incremental step pulse programming can actually be interpreted as a select gate scan as the voltage is increased incrementally similar to a gate scan); and
alter the select gate scan operation based on the monitored slope (Guo: Paragraph [0131], “As an example, the memory device may be programmed in an Incremental Step Pulse Programming (ISPP) manner. It should be pointed out that when the step and/or the programming voltage slope changes, the change speed of the threshold voltage of a memory cell would also change, so the value ranges of the second preset value and the second preset ratio can be adjusted correspondingly”; Paragraph [0134], “the step and/or the programming voltage slope of the incremental step pulse programming is obtained, and the value range of the second preset value is determined according to the step and/or the programming voltage slope; or, the value range of the second preset ratio is determined according to the step and/or the programming voltage slope. In this way, the value range of the second preset value and the value range of the second preset ratio can be flexibly adjusted, and the slow programming speed caused by improper setting of the second preset value and the second preset ratio can be reduced, thus improving the programming speed, and reducing the programming quality”; wherein the slope of voltages is determined; also the incremental step pulse programming (similar to Li’s step based gate scan) can actually be interpreted as a select gate scan as the voltage is increased incrementally similar to a gate scan; wherein finally the signaling is altered based on the determination of slope).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by the Subramanian/Li combination by using slope of a voltage threshold distribution to determine a need to adjust, as taught by Guo. One of ordinary skill in the art would have been motivated to use the methods of Guo because it would improve the time for verification and ensuring quality is an urgent problem to be solved. (Guo: Paragraph [0004]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. (US 20250239315 A1, US 20240412788 A1, US 20240379167 A1, US 20170141245 A1, US 20140169095 A1, US 20070027567 A1, US 20030120445 A1).
US 20250239315 A1: In step 802 of FIG. 8, the control circuit reads a data set from a plurality of non-volatile memory cells in overlapping threshold voltages distributions. For example, the process of FIG. 7 will be performed one or more times to sense information from memory cells in the threshold voltage distributions of FIG. 5D for one or more code words and the system attempts to decode the one or more code words (e.g., using ECC Engine 158). In step 804, the control circuit determines that the data set was not read successfully (e.g., because the code words sensed from the memory cells have too many errors for the ECC process to correct). In step 806, the control circuit, in response to determining that the data set was not read successfully, identifies memory cells in upper tails and lower tails of overlapping threshold voltages distributions. In one embodiment, the control circuit identifies memory cells that are storing error bits from the code words having too many errors and that are in upper tails or lower tails of overlapping threshold voltages distributions. In step 808, the control circuit adjusts threshold voltages of the identified memory cells (identified in step 806) to be closer to centers of the overlapping threshold voltages distributions without changing threshold voltages distributions for the identified memory cells being adjusted. More details of steps 806 and 808 will be discussed below.
US 20240412788 A1: Here, the threshold voltage characteristics may include a threshold voltage value of each of the memory cells, a threshold voltage slope of each of the memory cells, and a cell current value of each of the memory cells.
US 20240379167 A1: Since the first sub-period 1SEC is a period in which the erase operation of the memory cells is performed relatively fast, the first erase voltage 1Vers higher than the reference voltage Vref may be constantly applied to the source line. Therefore, between the first time T1 at which the erase operation is started and the second time T2 at which the first sub-period 1SEC is ended, slopes 1Gs and 1Gf of the memory cells MCs and MCf, which are decreased by the first erase voltage 1Vers, may become larger than slopes pGs and pGf of the threshold voltage Vth of memory cells, which are decreased by the reference voltage Vref.
US 20170141245 A1: Several p-type Si wafers that differ in the doping in their front surface, n-type emitter regions were used in the other examples reported below. As set forth above, both the overall doping profile and the surface dopant concentration are understood to influence the overall quality of photovoltaic cells fabricated using these wafers. Since both a high recombination loss and a high resistance electrical connection are deleterious to the overall electrical performance of a PV cell, different approaches have been taken to balance these factors, as is implicit in the various p-type wafer substrates described below: The p-type wafers herein were all textured on both major surfaces by a hydroxide etching treatment.
US 20140169095 A1: In order to maintain the threshold voltage of a select transistor within a desired range, the threshold voltage may be monitored to see if it is within the predetermined range and restore it to the predetermined range if it is no longer within the predetermined range. The threshold voltage may be monitored periodically during the lifecycle of the memory (e.g. based on a time stamp or other time indicator), or may be monitored in response to some triggering event. Hot count (the number of write/erase cycles) may be used to trigger monitoring. For example, select transistors may be monitored every N cycles (e.g. every 1000 cycles). Alternatively, monitoring may be performed in response to increasing numbers of ECC errors so that when the number of ECC errors exceeds a threshold number then monitoring is performed. Other triggering events may also be used.
US 20070027567 A1: Consider the following example of Table 1, below. In this example, step 202 was performed twice, storing the values identified as Wafer Positions 1 and 2, and step 212 was performed twice, storing the valued identified as Wafer Positions 3 and 4. As can be seen from the table, Wafer Position 1 does not have the highest number of good die, so in the present embodiment, this position will not be further considered. The remaining three Wafer Positions all share the same number of good die--405 die. TABLE-US-00001 TABLE 1 Wafer Position Good Total Shared (Die arrangement) Die Dummies Dummies 1 395 3 1 2 405 4 0 3 405 4 2 4 405 3 0
US 20030120445 A1: The wafer test data 10 is a table that contains wafer ID, X/Y coordinates of the chip, and the wafer test sort result. These data are input into two routines. The `block_analysis` 14 routine extracts .alpha. and .lambda..sub.k using windowing, as described above. The `neighbor_analysis` 12 routine analyzes and computes the local region yield bin for each device. The final piece of information is the pass/fail disposition of the good wafer die following reliability screen (wafer-level voltage stress, module-level burn-in, etc.)18. The bin wafer data 16 and reliability data 18 are merged as shown in FIG. 8:
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/MATTHEW N PUTARAKSA/Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114
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