DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to applicant’s communication filed March 11, 2026. The applicant’s remarks and amendment to the specification and/or claims were considered with the results that follow.
Claims 1, 2, and 4-21 have been presented for examination in this application. In response to the Examiner’s action of December 23, 2025, claims 1, 5, 6, 11 and 21.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4-8, 10-18, and 20-23 is/are rejected under 35 U.S.C. 102(a)(1)as being anticipated by Koszewnik (US# 2018/0143786).
Regarding claim 1, Koszewnik teaches obtaining processing request data; obtaining processing request data [0070, line 3: value]; receiving a memory operation instruction [0070, lines 1-3]; forming a global memory pool between a second storage medium (130) of the computing node (140+120+130) and a first storage medium (170 or 160) of a storage node (150 + external storage) that is external to the computing node and that is communicatively coupled to the computing node via a network [Poolable Arrays (130) and Slabs (170) (Fig. 1) and external memory (0022, lines 1-8)]; and performing, independently of data conversion between the first storage medium and the second storage medium [although not explicitly recited, one of ordinary skill in the art would recognize that moving data from an external storage space such as disk or flash drive to an internal RAM storage space requires both address and data storage conversion due to the qualities of the different types of storage media], a memory operation of the processing request data on the global memory pool based on a memory the memory operation instruction [0070, application->request->RMW; see also 0042 & 0045].
Regarding claim 2, Koszewnik teaches wherein the memory operation instruction comprises at least one of memory allocation, memory setting, memory copying [read-modify-write, 0042], memory movement, memory release, or memory comparison.
Regarding claim 4, Koszewnik teaches reading to-be-processed data from the global memory pool; and pool; processing the to-be-processed data based on the processing request data by executing the memory operation instruction to obtain processed data, and writing the processed data into storage space indicated by a first address in the global memory pool [0042, read-modify-write operation; 0045, 0070].
Regarding claim 5, Koszewnik teaches determining, based on a user requirement (operation)and a storage medium characteristic (storage space), to write the processed data into the storage space and wherein the storage medium characteristic comprises a writing latency, a read latency, an available storage capacity [address & offset for storage also based on available addresses associated with storage device, 0079, lines 7-9; see also 0034, lines 4-8], an access speed, central processing unit (CPU) consumption, an energy consumption ratio, or a reliability.
Regarding claim 6, Koszewnik teaches wherein the storage space is in the first storage medium or the second storage medium [0034, lines 1-4; Fig. 1; 0022].
Regarding claim 7, Koszewnik teaches wherein after the writing the processed data into the storage space, the method further comprises reading the processed data from the global memory pool based on the first address [another RMW operation performed again on same address as previously for claim 1; 0070, 0042, 0045].
Regarding claim 8, Koszewnik teaches writing the processed data into the storage node [writing as part of RMW operation of claim 1].
Regarding claim 10, Koszewnik teaches performing a memory operation on data between the global memory pool and the storage node based on a characteristic of cold/hot data and the memory operation instruction [0096; changing referencing of slab and memory pool].
Claim 11 recites similar claim language to that of claim 1, and is rejected for the same reasons as claim 1.
Claim 12 recites similar claim language to that of claim 2, and is rejected for the same reasons as claim 2.
Regarding claim 13, Koszewnik teaches wherein the first storage medium of the second storage medium comprises a memory [0030], a memory server or a storge-class memory (SCM).
Claim 14 recites similar claim language to that of claim 4, and is rejected for the same reasons as claim 4.
Claim 15 recites similar claim language to that of claim 5, and is rejected for the same reasons as claim 5.
Regarding claim 16, Koszewnik teaches wherein the storage space is in the first storage medium or the second storage medium [0034, lines 1-4; Fig. ].
Claim 17 recites similar claim language to that of claim 7, and is rejected for the same reasons as claim 7.
Claim 18 recites similar claim language to that of claim 8, and is rejected for the same reasons as claim 8.
Claim 20 recites similar claim language to that of claim 10, and is rejected for the same reasons as claim 10.
Claim 21 recites similar claim language to that of claim 1, and is rejected for the same reasons as claim 1.
Regarding claim 22, Koszewnik teaches wherein the storage medium characteristic further comprises a total storage capacity [address & offset for storage based on total capacity, 0079, lines 7-9]
Regarding claim 23, Koszewnik teaches further comprising further forming the global memory pool through unified addressing [data stored in RAMs and external memories must be accessible to be used, and are thus part of a “unified” totality of addressable areas (0022), like that of Applicant’s example of unified addressing in paragraph 0057, lines 7-8].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koszewnik (US# 2018/0143786).
Regarding claims 9 and 19, Koszewnik teaches data operations and moving data in memory [0023] but fails to teach prefetching data from the storage node based on the memory operation instruction, and storing the data in the global memory pool. One of ordinary skill in the art would recognize that prefetching is incorporating when data potentially relativistic data is loaded into memory before being specifically called upon, which leads to quicker access to said data when a corresponding operation calling for said data occurs. The Examiner takes OFFICIAL NOTICE of this teaching. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Koszewnik to include data prefetching because of the benefit disclosed supra.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 2, and 4-23 have been considered but are moot in view of the new grounds of rejection.
Regarding Applicant’s argument on page of the response that Koszewnik fails to teach “forming a global memory pool between a second storage medium of a computing node and a first storage medium of a storage node that is external to the computing node and that is communicatively coupled to the computing node via a network; and 2) performing, independently of data conversion between the first storage node and the second storage node, a memory operation of the processing request data on the global memory pool based on the memory operation instruction”, the Examiner respectfully disagrees. As noted above, the prior art of Koszewnik teaches all claim elements as recited. Koszewnik teaches in at least paragraphs 0022 and 0104 that external memories may be added to supplement the RAM 116. Furthermore, the claim language does not recite what may or may not be comprised in the compute node or storage node other than the second storage medium and first storage medium in their respective nodes. The Examiner has indicated above the components that at least are comprised within a broad and reasonable interpretation of the compute node and storage node, where the storage node also includes the external memory of paragraph 0022.
Applicant’s Arguments directed towards the 35 USC 103 rejection carry over the arguments directed to their parent claims, and Examiner’s explanation directed towards Applicant’s arguments for the independent claims disclosed above would also apply for these arguments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Brian R. Peugh whose telephone number is (571) 272-4199. The examiner can normally be reached on Monday-Friday from 7:30am to 3:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Rocio Del Mar Perez-Velez, phone number 571-270-5935, can be reached. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is 571-272-2100.
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/BRIAN R PEUGH/ Primary Examiner, Art Unit 2133
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