DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/1/24 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park (US 2006/0132665).
As to claim 1, Park teaches an array substrate (see annotated fig. 4 below) comprising:
a semiconductor film (224) disposed on an upper-layer side of an insulating substrate (210, [0103] – [0104]);
a gate insulating film (215) disposed in a layer above the semiconductor film (224, [0053], 115 in fig. 2 corresponds to 215 in fig. 4);
a gate electrode (221N) disposed in a layer above the gate insulating film (215A, [0103]);
an interlayer insulating film (215B) disposed in a layer above the gate electrode (221P, [0096], 115B in fig. 2 corresponds to 215B in fig. 4);
a thin film transistor including a source electrode (222N) and a drain electrode (223P) disposed on the upper-layer side of the gate electrode (221N) via the interlayer insulating film (215A, [0103]); and
a gate wiring line continuously formed with the gate electrode of the thin film transistor ([0100] – [0101], the electrode and the wiring are together),
wherein the gate electrode and the gate wiring line include an aluminum film ([0059]), and a protective metal film (221’N) made of a metal material having a melting point higher than a melting point of aluminum, and covering an entire surface of the aluminum film ([0067], [0087], and [0103], film 160 is patterned to become 221’N and comprises the same material as the protective layer claimed).
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As to claim 2, Park further teaches (see annotated fig.4 above) the protective metal film (221’N) includes an overlapping portion overlapping with the aluminum film, and a protruding portion protruding from the overlapping portion and not overlapping with the aluminum film, the semiconductor film (224N) is an impurity semiconductor film, and of the semiconductor film, an impurity concentration in a first region (224NC) overlapping with the overlapping portion of the protective metal film is different from an impurity concentration in a second region (224NL) overlapping with the protruding portion of the protective metal film ([0104] – [0106], the overlapping portion is over the channel of the SC layer and the protruding portions are over the LDD regions of the SC layer).
As to claim 3, Park further teaches (see annotated fig. 4 above) the semiconductor film (224N) has a structure including a channel region (224NC) overlapping with the aluminum film of the gate electrode (221N) and the overlapping portion of the protective metal film (221’N), a source region (224NS) and a drain region (224ND) being high-concentration impurity regions disposed on both sides of the channel region (224NC), and being respectively connected to one of the source electrode (222N) and the drain electrode (223N) of the thin film transistor, and a low-concentration impurity region (224NL) disposed in at least one of between the channel region (224NC) and the source region (224NS) and between the channel region (224NC) and the drain region (224ND), and overlapping with the protruding portion of the protective metal film (221N’N, [0104] – [0106]).
As to claim 4, Park further teaches the semiconductor film (224) is a polysilicon film ([0047]).
As to claim 5, Park further teaches a counter substrate disposed to face the array substrate with an internal space provided between the array substrate and the counter substrate; and a liquid crystal layer sealed in the internal space ([0014] – [0015])
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park (US 2006/0132665).
As to claim 6, Park teaches a method for manufacturing an array substrate (figs. 2A-2F), the method comprising:
forming a semiconductor film (124) of a thin film transistor on an upper-layer side of an insulating substrate (110, fig. 2A, [0047]);
forming a gate insulating film (115A) of the thin film transistor on the semiconductor film (124, fig. 2B, [0053]);
forming an aluminum film (121) that forms a part of the gate electrode and a part of the gate wiring line ([0054] and [0100] – [0101], the electrode and the wiring are together);
patterning, by etching, a base layer including the formed first metal film (see 103 explanation below) and the formed aluminum film (fig. 2B, [0055]);
forming a second metal film (160) that is made of a metal having a melting point higher than the melting point of aluminum and that forms, on the patterned base layer, a part of the gate electrode and a part of the gate wiring line (fig. 2C);
patterning the formed second metal film (160) by etching the second metal film (160) to have a planar size larger than a planar size of the base layer (shown in the embodiment of fig. 4), and forming the gate electrode and the gate wiring line including the base layer and the second metal film (fig. 2C); and
performing, after forming the gate electrode and the gate wiring line, heat treatment at a temperature equal to or higher than 450°C ([0108] while not explicitly taught, thermal protection implies a thermal process. However, annealing and impurity driving thermal processes when forming a transistor are known in the art and would have been obvious so as to fabricate a transistor. Some of those processes would require high temperatures above 450°C, depending on the requirement.)
Park does not teach forming a first metal film that is made of a metal material having a melting point higher than a melting point of aluminum and that forms, on the gate insulating film, a part of a gate electrode of the thin film transistor and a part of a gate wiring line connected to the gate electrode.
However, Park does teach that it is beneficial to surround the first gate with the second gate material for the purposes of protecting the first gate from defects ([0108]). Thus, adding a second gate layer on all sides of the first gate (i.e. below the bottom surface of the first gate) would have been obvious for the reasons stated above.
As to claim 7, Park further teaches the semiconductor film is an impurity semiconductor film, introduction of impurities is performed, after forming the gate electrode and before performing the heat treatment, in which ionized impurities are accelerated and injected into the semiconductor film, and in the introduction of the impurities, a surface of the gate electrode is not covered with another portion and remains exposed ([0055] – [0057]).
As to claim 8, Park further teaches the semiconductor film is a polysilicon film, and when performing the heat treatment, crystallinity of the polysilicon film deteriorating due to the introduction of the impurities is recovered ([0047], inherent to heat treatments of that temperature).
Conclusion
Any response to this Office Action should be faxed to (571) 273-8300 or mailed to:
Commissioner for Patents
P.O. Box 1450
Alexandria, VA 22313-1450
Hand-Delivered responses should be brought to:
Customer Service Window
Randolph Building
401 Dulany Street
Alexandria, VA 22313
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREN M KUSUMAKAR whose telephone number is (571)270-3520. The examiner can normally be reached on Monday – Friday from 7:30a – 4:30p EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KAREN KUSUMAKAR/
Primary Examiner, Art Unit 2897
9/30/26
