The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is in response to communications filed on 10/1/2024.
Claims 1-12 are pending.
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 7, and 10 is/are rejected under 35 U.S.C. 102(A)(1) as being anticipated by Tsu (US 7705850 B1).
Regarding claim 1, Tsu discloses an apparatus, comprising: a memory; and control circuitry (col. 3, lines 32-50, "a core processing unit 410 that includes a plurality of direct memory access (DMA) processing engines 420" with the core processing unit performing preset actions - memory storing instructions for the core processing unit is therefore inherent), to:
receive packets (col. 2, lines 17-19, "multiple read completion packets that are received"),
which are en-route to undergo transport-layer processing in a network device in accordance with a transport protocol that requires arrival of the packets in a sequential order (col. 2, lines 17-19, "the multiple read completion packets that are received in response thereto are ordered in accordance with the timing of the multiple read requests" - transport layer processing is generally understood as processing of packets before the packets are further processed by a requesting application, to include correctly ordering. Here, the requesting applications are DMA engines 420 (see col. 3, lines 45-47); col. 3, lines 59-61, "receive the read completion PCIe packets through PCIe interface 222 and PCIe interface 224" however, col. 3, line 43, "packets are ordered by the core processing unit 410" (therefore, the packets are received by the PCIe interfaces and ordered by processing unit 410. From Fig. 4, the PCIe interfaces are separate from unit 410, and thus, at the moment the packets are received, they are en-route to processing unit 410)),
at least some of the received packets being read responses that are received in response to a read request from the network device (col. 3, lines 56-67, "endpoint device 220 sends the first read request PCIe packet over PCIe interface 222. Then, at step 504, endpoint device 220 sends the second read request PCIe packet over PCIe interface 224. Endpoint device 220 then waits to receive the read completion PCIe packets through PCIe interface 222 and PCIe interface 224 (step 506). At step 508, a check is made to see if the read completion PCIe packet is received through PCIe interface 222 before the read completion PCIe packet is received through PCIe interface 224. If so, the read completion PCIe packets are used in the order of their receipt (step 510). If not, the read completion PCIe packets are used in the reverse order of their receipt (step 512)");
detect, by monitoring the read request sent by the network device, that one or more of the read responses deviate from the sequential order (col. 3, lines 42-45, "the received read completion PCIe packets are ordered by the core processing unit 410 in the same order in which the first and second read request PCIe packets were issued" - monitoring which packet is sent first is inherent);
buffer the one or more deviating read responses in the memory (col. 3, lines 61-67, "a check is made to see if the read completion PCIe packet is received through PCIe interface 222 before the read completion PCIe packet is received through PCIe interface 224. If so, the read completion PCIe packets are used in the order of their receipt (step 510). If not, the read completion PCIe packets are used in the reverse order of their receipt (step 512)" - buffering at least one packet in a memory inherent as otherwise packets would be lost before all packets arrive); and
using the memory, reorder the read responses and provide the read responses in the sequential order to the network device (col. 3, lines 61-67, "a check is made to see if the read completion PCIe packet is received through PCIe interface 222 before the read completion PCIe packet is received through PCIe interface 224. If so, the read completion PCIe packets are used in the order of their receipt (step 510). If not, the read completion PCIe packets are used in the reverse order of their receipt (step 512)" ).
Regarding claim 4, Tsu discloses the apparatus according to claim 1, wherein the control circuitry is configured to reorder and provide the read responses, by (i) retaining the one or more deviating read responses in the memory until arrival of one or more read responses that precede the one or more deviating read responses in the sequential order, and only then (ii) providing the one or more read responses that precede the one or more deviating read responses, followed by the one or more deviating read responses (col. 3, lines 61-67, "a check is made to see if the read completion PCIe packet is received through PCIe interface 222 before the read completion PCIe packet is received through PCIe interface 224. If so, the read completion PCIe packets are used in the order of their receipt (step 510). If not, the read completion PCIe packets are used in the reverse order of their receipt (step 512)").
Regarding claim 7, Tsu discloses a method (col. 1, line 59, "a method").
The remaining limitations of claims 7 and 10 are similar in scope to those of claims 1 and 4. Therefore, claims 7 and 10 are rejected for the same reasons as set forth in the rejection of claims 1 and 4, above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 5, 9, and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsu (US 7705850 B1) in view of Galon et al. (US 9692560 B1, hereinafter Galon).
Regarding claim 3, Tsu discloses the apparatus according to claim 1, wherein the transport protocol is Direct Memory Access (DMA), and wherein the read request is an DMA read (col. 4, lines 4-13, "a read request is issued by a DMA processing engine […] Endpoint device 220 then receives the read completion PCIe packet through the PCIe interface determined in step 604 (step 608). When it does, the read data contained in the read completion PCIe packet are provided to the DMA processing engine that issued the read request").
Tsu does not disclose that Direct Memory Access (DMA) is Remote Direct Memory Access (RDMA).
Galon discloses that Direct Memory Access (DMA) may be Remote Direct Memory Access (RDMA) (col. 3, lines 22-28, "host systems 102A/102B with adapters' 116A/116B may operate as remote direct memory access (RDMA) nodes. Adapter 116A/116B may be referred to as requestor adapter (or simply as requestor) or a responder adapter (or responder). It is noteworthy that both adapters can be configured to operate as a requestor and the responder at the same time"; col. 13, lines 42-45, "the requestor determines if it has received an out of order RDMA read response or an out of order atomic response packet. If yes, then in block B206, the received packet is buffered in an out of order buffer" - where RDMA, by definition, is "an extension of the Direct Memory Access (DMA)" for enabling access to memories of remote devices, see Hagoort, "The Basics of Remote Direct Memory Access (RDMA) in vSphere", 2024, page 1).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Tsu in view of Galon so that Direct Memory Access (DMA) is Remote Direct Memory Access (RDMA).
One of ordinary skill in the art would have been motivated because it would allow quick access to memories that are not local to a host thus providing flexibilities not possible with DMA.
Regarding claim 5, Tsu discloses the apparatus according to claim 1.
Tsu does not disclose that the control circuitry is configured to detect that a time that elapsed since initiating buffering of the one or more deviating read responses exceeds a defined timeout, and in response cause the network device to request retransmission of the one or more read responses that precede the one or more deviating read responses.
Galon discloses control circuitry that is configured to detect that a time that elapsed since initiating buffering of the one or more deviating read responses exceeds a defined timeout, and in response cause the network device to request retransmission of the one or more read responses that precede the one or more deviating read responses (col. 11, lines 54-61, "The requestor, as a data sender, may also have its retransmission timer expired, indicating that the response packet (including possibly a NAK sequence error packet) have been lost in the network. This effectively causes the requester to stop current transmission, and retransmit all the packets, starting from a last acknowledged PSN (or possibly even start retransmitting from an “older” PSN, which is the beginning of a work queue which was partially lost)").
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Tsu in view of Galon so that the control circuitry is configured to detect that a time that elapsed since initiating buffering of the one or more deviating read responses exceeds a defined timeout, and in response cause the network device to request retransmission of the one or more read responses that precede the one or more deviating read responses.
One of ordinary skill in the art would have been motivated because a "responder, as a data sender, cannot detect packet losses" (col. 11, lines 61-63) and therefore requesting retransmission is necessary to prevent errors or lost packets.
Regarding claim 9, Tsu discloses the method according to claim 7.
The remaining limitations of claim 9 are similar in scope to those of claim 3. Therefore, claim 9 is rejected for the same reasons as set forth in the rejection of claim 3, above.
Regarding claim 11, Tsu discloses the method according to claim 7.
The remaining limitations of claim 11 are similar in scope to those of claim 5. Therefore, claim 11 is rejected for the same reasons as set forth in the rejection of claim 5, above.
Claim(s) 6 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsu (US 7705850 B1) in view of Georgiou et al. (US 20050025152 A1).
Regarding claim 6, Tsu discloses the apparatus according to claim 1, wherein the control circuitry is configured to detect and buffer the deviating read responses, and to reorder and provide the read responses (col. 3, lines 61-67, "a check is made to see if the read completion PCIe packet is received through PCIe interface 222 before the read completion PCIe packet is received through PCIe interface 224. If so, the read completion PCIe packets are used in the order of their receipt (step 510). If not, the read completion PCIe packets are used in the reverse order of their receipt (step 512)").
Tsu does not disclose that the received packets are associated with multiple flows, wherein the reordering is performed separately for each of the flows.
Georgiou discloses that the received packets are associated with multiple flows, wherein the reordering is performed separately for each of the flows (¶[0026], "reordering a plurality of packet flows, generally shown as reference numeral 200. Packets from two flows, A and B, are received intermixed and portions being out-of-order. Packets associated with flow A are labeled "A", packets associated with flow B are labeled "B". For each of the flows, packet sequence breaks are detected and recorded into the corresponding reorder table, e.g., 215 or 225, and packets are stored in the memory as linked lists, e.g., 210 or 220. For the example of FIG. 3, six linked lists are used as there are six distinct out-of-order packet segments, three each from two flows, A and B. Any number of out-of-sequence segments may occur for a flow. Included in this diagram is a resulting transmitted packet stream, generally shown as reference numeral 235, with packets in order for both flows A and B produced as a result of using this invention").
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Tsu in view of Georgiou so that the received packets are associated with multiple flows, wherein the reordering is performed separately for each of the flows.
One of ordinary skill in the art would have been motivated because a "responder, as a data sender, cannot detect packet losses" (col. 11, lines 61-63) and therefore requesting retransmission is necessary to prevent errors or lost packets.
Regarding claim 12, Tsu discloses the method according to claim 7.
The remaining limitations of claim 12 are similar in scope to those of claim 6. Therefore, claim 12 is rejected for the same reasons as set forth in the rejection of claim 6, above.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 and 7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6 of U.S. Patent No. 12,132,665 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Regarding claim 1, US Patent No. 12,132,665 B2 discloses an apparatus, comprising: a memory; and control circuitry (Claim 1, "An apparatus, comprising: a memory; and control circuitry, to"), to:
receive packets (Claim 1, "receive packets"),
which are en-route to undergo transport-layer processing in a network device in accordance with a transport protocol that requires arrival of the packets in a sequential order (Claim 1, "which are en-route to undergo transport-layer processing in a network device in accordance with a transport protocol that requires arrival of the packets in a sequential order"),
at least some of the received packets being read responses that are received in response to a read request from the network device (Claim 6, "at least some of the received packets are read responses that are received in response to a read request from the network device");
detect, by monitoring the read request sent by the network device, that one or more of the read responses deviate from the sequential order (Claim 1, "detect that one or more of the packets deviate from the sequential order");
buffer the one or more deviating read responses in the memory (Claim 1, "buffer the one or more deviating packets in the memory"); and
using the memory, reorder the read responses and provide the read responses in the sequential order to the network device (Claim 1, "using the memory, reorder the packets and provide the packets in the sequential order to the network device").
Regarding claim 7, Claim 1 of US Patent No. 12,132,665 B2 implicitly recites a method.
The remaining limitations of claim 7 are similar in scope to those of claim 1. Therefore, claim 7 is rejected for the same reasons as set forth in the rejection of claim 1, above.
Claims 1, 3-7, 9-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4, and 10 of U.S. Patent No. 12,132,665 B2 in view of Galon (US 9692560 B1).
Regarding claim 1, US Patent No. 12,132,665 B2 discloses an apparatus, comprising: a memory; and control circuitry (An apparatus, comprising: a memory; and control circuitry, to: ), to:
receive packets (receive packets, ),
which are en-route to undergo transport-layer processing in a network device in accordance with a transport protocol that requires arrival of the packets in a sequential order (which are en-route to undergo transport-layer processing in a network device in accordance with a transport protocol that requires arrival of the packets in a sequential order; ),
detect, by monitoring the read request sent by the network device, that one or more of the read responses deviate from the sequential order (detect that one or more of the packets deviate from the sequential order; );
buffer the one or more deviating read responses in the memory (buffer the one or more deviating packets in the memory; ); and
using the memory, reorder the read responses and provide the read responses in the sequential order to the network device (using the memory, reorder the packets and provide the packets in the sequential order to the network device; and in response to detecting that a time that elapsed since initiating buffering of the one or more deviating packets exceeds a defined timeout, cause the network device to request retransmission of one or more packets that precede the one or more deviating packets.).
Claim 1 of US Patent No. 12,132,665 B2 does not disclose that at least some of the received packets are read responses that are received in response to a read request from the network device.
Galon discloses that at least some of the received packets are read responses that are received in response to a read request from the network device (col. 3, lines 22-28, "host systems 102A/102B with adapters' 116A/116B may operate as remote direct memory access (RDMA) nodes. Adapter 116A/116B may be referred to as requestor adapter (or simply as requestor) or a responder adapter (or responder). It is noteworthy that both adapters can be configured to operate as a requestor and the responder at the same time"; col. 13, lines 42-45, "the requestor determines if it has received an out of order RDMA read response or an out of order atomic response packet. If yes, then in block B206, the received packet is buffered in an out of order buffer").
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify US Patent No. 12,132,665 B2 in view of Galon so that at least some of the received packets are read responses that are received in response to a read request from the network device.
One of ordinary skill in the art would have been motivated because it would allow quick access to memories that are not local to a host.
Regarding claim 3, the combined system of US Patent No. 12,132,665 B2 and Galon discloses the invention substantially as applied to claim 1, above.
US Patent No. 12,132,665 B2 does not disclose that the transport protocol is Remote Direct Memory Access (RDMA), and wherein the read request is an RDMA read.
Galon discloses that the transport protocol is Remote Direct Memory Access (RDMA), and wherein the read request is an RDMA read (col. 3, lines 22-28, "host systems 102A/102B with adapters' 116A/116B may operate as remote direct memory access (RDMA) nodes. Adapter 116A/116B may be referred to as requestor adapter (or simply as requestor) or a responder adapter (or responder). It is noteworthy that both adapters can be configured to operate as a requestor and the responder at the same time"; col. 13, lines 42-45, "the requestor determines if it has received an out of order RDMA read response or an out of order atomic response packet. If yes, then in block B206, the received packet is buffered in an out of order buffer" - where RDMA, by definition, is "an extension of the Direct Memory Access (DMA)" for enabling access to memories of remote devices, see Hagoort, "The Basics of Remote Direct Memory Access (RDMA) in vSphere", 2024, page 1).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify US Patent No. 12,132,665 B2 in view of Galon so that the transport protocol is Remote Direct Memory Access (RDMA), and wherein the read request is an RDMA read.
One of ordinary skill in the art would have been motivated because it would allow quick access to remote memories.
Regarding claim 4, the combined system of US Patent No. 12,132,665 B2 and Galon discloses the invention substantially as applied to claim 1, above, wherein the control circuitry is configured to reorder and provide the read responses, by (i) retaining the one or more deviating read responses in the memory until arrival of one or more read responses that precede the one or more deviating read responses in the sequential order, and only then (ii) providing the one or more read responses that precede the one or more deviating read responses, followed by the one or more deviating read responses (US Patent No. 12,132,665 B2, Claim 4).
Regarding claim 5, the combined system of US Patent No. 12,132,665 B2 and Galon discloses the invention substantially as applied to claim 1, above.
US Patent No. 12,132,665 B2 does not disclose that the control circuitry is configured to detect that a time that elapsed since initiating buffering of the one or more deviating read responses exceeds a defined timeout, and in response cause the network device to request retransmission of the one or more read responses that precede the one or more deviating read responses.
Galon discloses control circuitry that is configured to detect that a time that elapsed since initiating buffering of the one or more deviating read responses exceeds a defined timeout, and in response cause the network device to request retransmission of the one or more read responses that precede the one or more deviating read responses (col. 11, lines 54-61, "The requestor, as a data sender, may also have its retransmission timer expired, indicating that the response packet (including possibly a NAK sequence error packet) have been lost in the network. This effectively causes the requester to stop current transmission, and retransmit all the packets, starting from a last acknowledged PSN (or possibly even start retransmitting from an “older” PSN, which is the beginning of a work queue which was partially lost)").
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify US Patent No. 12,132,665 B2 in view of Galon so that the control circuitry is configured to detect that a time that elapsed since initiating buffering of the one or more deviating read responses exceeds a defined timeout, and in response cause the network device to request retransmission of the one or more read responses that precede the one or more deviating read responses.
One of ordinary skill in the art would have been motivated because a "responder, as a data sender, cannot detect packet losses" (col. 11, lines 61-63) and therefore requesting retransmission is necessary to prevent errors or lost packets.
Regarding claim 6, the combined system of US Patent No. 12,132,665 B2 and Galon discloses the invention substantially as applied to claim 1, above, wherein the received packets are associated with multiple flows, and wherein the control circuitry is configured to detect and buffer the deviating read responses, and to reorder and provide the read responses, separately for each of the flows (US Patent No. 12,132,665 B2, Claim 10).
Regarding claims 7 and 9-12, Claim 1 of US Patent No. 12,132,665 B2 implicitly discloses a method.
The remaining limitations of claims 7 and 9-12 are similar in scope to those of claims 1 and 3-6. Therefore, claims 7 and 9-12 are rejected for the same reasons as set forth in the rejection of claims 1 and 3-6, above.
Allowable Subject Matter
Claims 2 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/BORIS D GRIJALVA LOBOS/ Primary Patent Examiner, Art Unit 2446
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