DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lobsiger et al (US PGPUB 2012/0098577).
Regarding claim 1, Figure 3 of Lobsiger discloses a power switching system comprising:
a plurality of power switching units coupled in parallel, each of the power switching units including a respective power switch and sense circuitry configured to sense current of the respective power switch [Figure 3, paragraph 33]
a communication system configured to convey a system-wide switching command to the power switching units along a communication channel [Cref]
circuitry for determining magnitudes of delays that are to be applied to the execution of the system-wide switching command the plurality of power switching units [Figure 4]
wherein each of the delays is tailored to a respective power switching unit and the circuitry for determining the magnitudes of the delays comprises circuitry for comparing times needed for the sensed currents at the different power switching units to reach or cross a threshold during a switching transition that is responsive to a previous system-wide switching command, or circuitry for comparing values of the sensed currents at the different power switching units at a time defined with respect to a previous system-wide switching command [paragraphs 33-46; Figure 4]
circuitry, included in each of the power switching units, that is configured to delay execution of the system-wide switching command by the delay that is tailored to that power switching unit [Figure 3; paragraphs 33-46; Figure 4]
Figure 3 of Lobsiger does not explicitly disclose configured to sense voltages between main terminals of the respective power switch.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Lobsiger by sensing voltages as a matter of simple design-choice, since it would have been a matter of simple substitution of one known element for another to obtain predictable results, as implied by Lobsiger [paragraph 25].
Regarding claim 2, Figure 3 of Lobsiger, as applied to claim 1, discloses wherein the circuitry for determining the magnitudes of the delays is configured to determine the magnitudes of the delays on a switching cycle-by-switching cycle basis [paragraphs 33-46].
Regarding claim 3, Figure 3 of Lobsiger, as applied to claim 1, discloses wherein each of the plurality of power switching units comprises a synchronizable clock configured to produce a clock signal, and wherein each of the power switching units is configured to reference either the times needed for the sensed voltages at the different power switching units to reach or cross a threshold, or the time defined with respect to a previous system-wide switching command to the synchronized clock signal [paragraphs 33-46].
Regarding claim 4, Figure 3 of Lobsiger, as applied to claim 3, discloses wherein the circuitry for determining the magnitudes of the delays is configured to determine delays that either reduce differences between the times needed for the sensed voltages at the different power switching units to reach or cross the threshold or reduce differences between the values of the sensed voltages at the time [paragraphs 33-46].
Regarding claim 5, Figure 3 of Lobsiger, as applied to claim 1, discloses wherein the system-wide switching command is a clock signal having different frequencies; and the delay is expressed in communications between the power switching units in terms of cycles of one of the frequencies of the clock signal [paragraphs 33-46].
Regarding claim 6, Figure 3 of Lobsiger, as applied to claim 1, discloses wherein magnitudes of the delays by which execution of the system-wide switching command is delayed differ in each of the plurality of power switching units [paragraphs 33-46].
Regarding claim 7, Figure 3 of Lobsiger, as applied to claim 1, discloses wherein: the communication system comprises a communications bus; the plurality of power switching units includes a master power switching unit and a plurality of slave power switching units coupled to the communications bus, wherein each of the master and slave power switching units includes a power switch, sense circuitry configured to sense voltages between main terminals of the power switch, and a communications interface coupled to the communications bus, and wherein each of the slave power switching units includes control circuitry configured to transmit, using the communications interface, a signal that includes information characterizing the sensed voltages to the master power switching unit, and wherein the power switching system includes circuitry configured to receive the information characterizing the sensed voltages at the slave power switching units and compare the sensed voltages at the slave power switching units with the sensed voltages between main terminals at the power switch of the master power switching unit to determine an adjustment to be applied to a switching transition during a subsequent switching cycle by a first of the slave power switching units, wherein the adjustment is tailored to the first of the slave power switching units, and further wherein the master power switching unit includes circuitry for transmitting, using the communications interface and to the first of the slave power switching units, a signal characterizing the adjustment [Figure 6; Figure 7].
Regarding claim 8, Figure 3 of Lobsiger, as applied to claim 7, discloses a system controller configured to provide a system-wide switching command that indicates a desired ON or OFF state of the master power switching unit and the plurality of slave power switching units and the adjustment is to be applied to the system-wide switching command [Figure 7; paragraphs 48 and 49].
Regarding claim 9, Figure 3 of Lobsiger, as applied to claim 8, discloses wherein the system controller includes the circuitry that is configured to receive the information characterizing the sensed voltages at the slave power switching units and compare the sensed voltages to determine the adjustment [Figure 7; paragraphs 48 and 49].
Regarding claim 10, Figure 3 of Lobsiger, as applied to claim 8, discloses wherein the adjustment is configured to reduce a delay between the system-wide switching command and the execution of the system-wide switching command by the at least one power switch [Figure 7; paragraphs 48 and 49].
Regarding claim 11, Figure 3 of Lobsiger, as applied to claim 1, discloses wherein either: a) the adjustment is between 0 and 1000 nanoseconds; or b) the delay is a fraction less than one of an inherent rise time or fall time of a control terminal of the respective power switch in the power switching system; or c) both a) and b) [paragraphs 33-46].
Regarding claim 12, Figure 3 of Lobsiger discloses a method comprising:
sensing currents of a plurality of power switches coupled in parallel in a power switching system [paragraphs 33-46; Figure 3]
determining either times needed for the sensed currents to reach or cross a threshold during a switching transition that is responsive to a system-wide switching command, or values of the sensed currents at a time defined with respect to the system-wide switching command [paragraphs 33-46]
determining, for a first of the power switches in the power switching system, an adjustment to be applied to execution of the system-wide switching command in a subsequent switching cycle, wherein the adjustment is tailored to the first of the power switches [paragraphs 33-46]
at a driver of the first power switch, applying the adjustment to the execution of the system-wide switching in the subsequent switching cycle [Figure 4; paragraphs 33-46]
Figure 3 of Lobsiger does not explicitly disclose sensing voltages between the main terminals of a plurality of power switches.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Lobsiger by sensing voltages as a matter of simple design-choice, since it would have been a matter of simple substitution of one known element for another to obtain predictable results, as implied by Lobsiger [paragraph 25].
Regarding claim 13, Figure 3 of Lobsiger, as applied to claim 12, discloses wherein either: a) the subsequent switching cycle is a next, immediately subsequent switching cycle; or b) the adjustment is determined to unbalance current carried by the power switches in the power switching system; or c) both a) and b) [paragraphs 33-46].
Regarding claim 14, Figure 3 of Lobsiger, as applied to claim 12, discloses wherein the adjustment is a configured to reduce a delay between the system-wide switching command and the execution of the system-wide switching command by the at least one power switch [paragraphs 33-46].
Regarding claim 15, Figure 3 of Lobsiger, as applied to claim 12, discloses wherein either: a) the adjustment is between 0 and 1000 nanoseconds; or b) the delay is a fraction less than one of an inherent rise time or fall time of a control terminal of the respective power switch in the power switching system; or c) both a) and b) [paragraphs 33-46].
Regarding claim 16, Figure 3 of Lobsiger, as applied to claim 12, discloses wherein the method further comprises: determining, for a second of the power switches in the power switching system, a second adjustment to be applied to execution of the system-wide switching command in the subsequent switching cycle, wherein the first adjustment differs from the second adjustment; and at a driver the second power switch, applying the adjustment to the execution of the system-wide switching in the subsequent switching cycle [paragraphs 33-46].
Regarding claim 17, Figure 3 of Lobsiger, as applied to claim 12, discloses wherein the system-wide switching command is a clock signal having different frequencies; and the adjustment is expressed in terms of cycles of one of the frequencies of the clock signal [paragraphs 33-46].
Regarding claim 18, Figure 3 of Lobsiger, as applied to claim 12, discloses wherein either the times needed for the sensed voltages to reach or cross the threshold or the time defined with respect to the system-wide switching command are referenced to a clock signals that are synchronized with clock signals of other of the power switches in the power switching system [paragraphs 33-46].
Conclusion
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/TOMI SKIBINSKI/Primary Examiner, Art Unit 2842 /LINCOLN D DONOVAN/Supervisory Patent Examiner, Art Unit 2842