DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I, figures 1-8, reads on claims 1-11 in the reply filed on 04/20/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 10 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Kurosawa (US 5262686)
Regarding claim 1, Kurosawa discloses a comparator [figs. 1-3] comprising: a switching circuit [switch 11-14, fig. 1] configured to receive a first input voltage [SIN, fig. 1] and a second input voltage [REF, fig. 1] respectively from a first input terminal [input terminal SIN] and a second input terminal [input terminal SIN], and to output a first switching voltage [voltage at N1] and a second switching voltage [voltage at N6] respectively to a first switching node [N1] and a second switching node [N6]; a first sampling/comparing circuit [41 consists of 51/52] configured to receive the first switching voltage from the first switching node and to output a first comparison voltage [S20] to a first comparison node [N5]; a second sampling/comparing circuit [42 consists of 55/56] configured to receive the second switching voltage from the second switching node and to output a second comparison voltage [S30] to a second comparison node [N10]; and an output circuit [31, figs. 1 and 3] configured to receive the first comparison voltage and the second comparison voltage respectively from the first comparison node and the second comparison node, and to output an output voltage [SOUT] to a single output terminal [output terminal SOUT], wherein the comparator is configured to operate in a first phase [reset at t1, fig. 3] and a second phase [conversion at t2, fig. 3] in response to a clock signal [cl. 7, ln. 15-22], wherein each of the first input voltage and the second input voltage have a variable voltage level [cl. 6-cl. 7], wherein the switching circuit is configured to output the second input voltage as the first switching voltage [using switch 12] and output the first input voltage as the second switching voltage [using switch 13] during the first phase, and output the first input voltage as the first switching voltage [using switch 11] and output the second input voltage as the second switching [using switch 14] voltage during the second phase, wherein the first sampling/comparing circuit [41] is configured to sample a first sampling voltage [voltage stored at node N2] based on the second input voltage during the first phase, and output the first comparison voltage [S20] corresponding to a result of comparing the first input voltage with the first sampling voltage during the second phase, wherein the second sampling/comparing circuit [42] is configured to sample a second sampling voltage [voltage stored at node N7] based on the second input voltage during the second phase, and output the second comparison voltage [S30] corresponding to a result of comparing the first input voltage with the second sampling voltage during the first phase, and wherein the output circuit [31] is configured to output the output voltage [SOUT] corresponding to the second comparison voltage during the first phase [during t1], and output the output voltage corresponding to the first comparison voltage during the second phase [during t2].
Regarding claim 2, Kurosawa discloses [figs. 1-3] wherein the switching circuit includes: a first switch [11] connected between the first input terminal and the first switching node; a second switch [14] connected between the second input terminal the second switching node; a third switch [13] connected between the first input terminal and the second switching node; and a fourth switch [12] connected between the second input terminal and the first switching node, wherein during the first phase [reset at t1, see fig. 3], the switching circuit is configured to turn off the first switch and the second switch, and turn on the third switch and the fourth switch, and wherein during the second phase [conversion at t2, see fig. 3], the switching circuit is configured to turn on the first switch and the second switch, and turn off the third switch and the fourth switch.
Regarding claim 3, Kurosawa discloses [figs. 1-3] wherein the first sampling/comparing circuit includes: a sampling capacitor [15] connected between the first switching node and a first node [N2]; a first inverter [17] connected between the first node and a second node [N3]; a second inverter [20] connected between the second node and the first comparison node; and a switch [16], wherein the switch and the first inverter are connected in parallel between the first node and the second node, and wherein the first sampling/comparing circuit is configured to turn on the switch during the first phase and turn off the switch during the second phase [see fig. 3].
Regarding claim 4, Kurosawa discloses [figs. 1-3] wherein during the first phase, the first sampling/comparing circuit is configured to sample a voltage [sampled voltage at node N2] obtained by subtracting an offset voltage of the first inverter [offset of 17] from the second input voltage to provide the first sampling voltage by using the sampling capacitor, and during the second phase the first sampling/comparing circuit is configured to output through the first inverter and the second inverter a voltage [voltage at node N2] corresponding to a voltage obtained by subtracting the first sampling voltage from the first input voltage as the first comparison voltage.
Regarding claim 5, Kurosawa discloses [figs. 1-3] wherein the first comparison voltage has a logical high level [logic "1" voltage, such as 5 V; cl. 6, ln. 59-67 and cl. 7, ln. 1-3] when the first input voltage is greater than the second input voltage and has a logical low level [a logic "0" voltage, such as 0 V] when the first input voltage is smaller than the second input voltage.
Regarding claim 6, Kurosawa discloses [figs. 1-3] wherein the first inverter [17] includes a CMOS inverter [inherent] including an input terminal [input terminal 17] connected to the first node and an output terminal [output terminal 17] connected to the second node, and wherein the switch [16, cl. 2, ln. 24-35] is configured to short-circuit the input terminal and the output terminal of the CMOS inverter when turned on during the first phase.
Regarding claim 10, Kurosawa discloses wherein the output circuit [31, figs. 1-2] includes: a first switch [Q3, fig. 2] connected between the first comparison node and the single output terminal; and an second switch [Q10, fig. 2] connected between the second comparison node and the single output terminal, wherein the output circuit is configured to turn off the first switch [Q3] and turn on the second switch [Q10] during the first phase, and wherein the output circuit is configured to turn on the first switch [Q3] and turn off the second switch [Q10] during the second phase.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kurosawa (US 5262686).
Regarding claim 11, Kurosawa discloses a comparator [see figs. 1-3] comprising: a first switch [11, fig. 1] connected between a first input terminal [input terminal SIN] and a first switching node [N1], the first switch configured to receive a first input voltage [SIN] at the first input terminal; a second switch [14] connected between a second input terminal [input terminal REF] and a second switching node [N6], the second switch configured to receive a second input voltage [REF] at the second input terminal; a third switch [13] connected between the first input terminal and the second switching node; a fourth switch [12] connected between the second input terminal and the first switching node; a first sampling capacitor [15] connected between the first switching node and a first node [N2]; a first inverter [17] connected between the first node and a second node [N3]; a second inverter [20] connected between the second node and a first comparison node [N5]; a fifth switch [16] connected in parallel with the first inverter and between the first node and the second node; a second sampling capacitor [25] connected between the second switching node and a third node [N7]; a third inverter [27] connected between the third node and a fourth node [N8]; a fourth inverter [30] connected between the fourth node and a second comparison node [N10]; a sixth switch [26] connected in parallel with the third inverter and between the third node and the fourth node; a seventh switch [Q3, fig. 2] connected between the first comparison node and a single output terminal [terminal SOUT], the single output terminal configured to output an output voltage [SOUT]; and an eighth switch [Q10, fig. 2] connected between the second comparison node and the single output terminal, wherein the comparator is configured to operate in a first phase [reset at t1, fig. 3] and a second phase [conversion, at t2, fig. 3] in response to a clock signal [cl. 7, ln. 15-22], wherein each of the first input voltage and the second input voltage have a variable voltage level [cl. 6-cl. 7], wherein during the first phase, the comparator is configured to turn off the first switch [11], the second switch [14], the sixth switch [26], and the seventh switch [Q3], and turn on the third switch [13], the fourth switch [12], the fifth switch [16], and the eighth switch [Q10], and wherein during the second phase [during t2], the comparator is configured to turn on the first switch [11], the second switch [14], and the seventh switch [Q3], and turn off the third switch [13], the fourth switch [12], the fifth switch [16], and the eighth switch [Q10]. Kurosawa does not explicitly disclose the sixth switch [26] turn off during the second phase. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the switching sequence of fig. 3 so that the sixth switch [SW26] is ON during t2, is a predictable and routine modification in chopper-stabilized comparator design, consistent with standard offset cancellation techniques.
Regarding claim 7, Kurosawa discloses all the features with respect to claim 1 as indicated above. Kurosawa further disclose [figs. 1-3] wherein the second sampling/comparing circuit [55/56] includes: a sampling capacitor [25] connected between the second switching node and a first node [N7]; a first inverter [27] connected between the first node and a second node [N8]; a second inverter [30] connected between the second node and the second comparison node; and a switch [26], wherein the switch and the first inverter are connected in parallel between the first node and the second node, and wherein the second sampling/comparing circuit is configured to turn off the switch [26] during the first phase. Kurosawa does not disclose turn on the switch during the second phase. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the switching sequence of fig. 3 so that the sixth switch [SW26] is ON during t2, is a predictable and routine modification in chopper-stabilized comparator design, consistent with standard offset cancellation techniques.
Regarding claim 8, Kurosawa discloses [figs. 1-3] wherein during the second phase the second sampling/comparing circuit [42] is configured to sample a voltage [sampled voltage at node N7] obtained by subtracting an offset voltage of the first inverter [offset 27] from the second input voltage to provide the second sampling voltage by using the sampling capacitor, and during the first phase the second sampling/comparing circuit is configured to output through the first inverter and the second inverter a voltage [voltage at node N7] corresponding to a voltage obtained by subtracting the second sampling voltage from the first input voltage as the second comparison voltage.
Regarding claim 9, Kurosawa discloses [figs. 1-3] wherein the second comparison voltage has a logical high level [logic "1" voltage, such as 5 V; cl. 6, ln. 59-67 and cl. 7, ln. 1-3] when the first input voltage is greater than the second input voltage and has a logical low level [a logic "0" voltage, such as 0 V] when the first input voltage is smaller than the second input voltage.
Conclusion
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/METASEBIA T RETEBO/Primary Examiner, Art Unit 2836
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