Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
1. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claim(s) 7-15, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang (Pub. No.: US 2012/0250426).
3. Regarding independent claim 7, Huang teaches an apparatus comprising: a memory controller (Fig. 6, #71) configured to provide a data clock signal (Fig. 6, clock output from #701) to a memory device (Fig. 6) and provide a duty cycle adjuster (DCA) code (Fig. 6, VCP, Fig. 7, S84 comparing operand VCAL and Vref get the result increase/decrease the duty cycle) to the memory device (Fig. 6), wherein the DCA code is one of a plurality of DCA codes (Fig. 7, S84-S86), wherein a first set of the plurality of DCA codes (Fig. 7, S84-S86) cause the memory device (Fig. 6) to increase a duty cycle of a signal (Fig. 7, S85) and a second set of the plurality of DCA codes (Fig. 7, S84-S86) cause the memory device (Fig. 6) to decrease the duty cycle of the signal (Fig. 7, S86).
4. Regarding claim 8, Huang teaches the DCA code (Fig. 7, S84-S86) causes the memory device (Fig. 6) to adjust the duty cycle of the signal within a DCA range (Fig. 7, S87-S88).
5. Regarding claim 9, Huang teaches the DCA range (Fig. 7, S87-S88) is divided into a plurality of steps (Fig. 7, S84-S87).
6. Regarding claim 10, Huang teaches a difference between a first step (Fig. 7, S87, Yes) and a second step (Fig. 7, S87, No) is different than a difference between the second step (Fig. 7, S87, No) and a third step (Fig. 7, S88).
7. Regarding claim 11, Huang teaches the plurality of steps are nonlinear (Fig. 7).
8. Regarding claim 12, Huang teaches the plurality of steps (Fig. 7, S84-S87) comprises a step range between step 0 to step 7(-7) (see Fig. 7, S87-S88).
9. Regarding claim 13, Huang teaches at least one DCA code (Fig. 7, S84-S86) of the plurality of DCA codes (Fig. 7, S84-S86) causes the memory device (Fig. 6) to maintain the duty cycle of the signal.
10. Regarding claim 14, Huang teaches the memory controller (Fig. 6, #71) is configured to cause the DCA code (Fig. 7, S84-S86) to be written to a mode register of the memory device (Fig. 6).
11. Regarding claim 15, Huang teaches the memory controller (Fig. 6, #71) is further configured to receive duty cycle monitoring results (see Fig. 7) from the memory device (Fig. 6), and the DCA code provided to the memory device (Fig. 6) is based, at least in part, on the duty cycle monitoring results (see Fig. 7, S84-S86).
Allowable Subject Matter
12. Claims 1-6, 16-22 are allowed.
13. With respect to claim 1, there is no teaching, suggestion, or motivation for combination in the prior art to a mode register configured to store a first DCA code and a second DCA code in a plurality of opcodes, wherein the duty cycle is adjusted through the first DCA code and the second DCA code, wherein the first DCA code is for an upper byte and the second DCA code for a lower byte.
14. With respect to dependent claims 2-6, since these claims are depending on claim 1, therefore claims 2-6 are allowable subject matter.
15. With respect to claim 16, there is no teaching, suggestion, or motivation for combination in the prior art to a mode register write command and a duty cycle adjuster (DCA) code to cause the DCA code to be written to the mode register, and cause the memory to adjust a duty cycle of the internal data clock signal based on the DCA code.
16. With respect to dependent claims 17-22, since these claims are depending on claim 16, therefore claims 17-22 are allowable subject matter.
Response to Argument
21. Applicant’s arguments with respect to claim 7 has been considered but are not persuasive.
The office understands that why the applicant argues Huang fails to teaches or suggest, “provide a duty cycle adjuster (DCA) code to the memory device” as recited in claim 7. If one considers that the memory controller and the memory device are two completely separated entities, the applicant’s argument may make sense. However, the term “memory device” is very broad and the applicant did not further define the term of the memory device and the structure relationship between memory device and the memory controller. Based on the broadest and reasonable interpretation, the “memory device” could be interpreted as a memory cell, a memory block, a memory array with its surrounding, a memory module, a memory stack, a memory chip etc. If the office considered the memory device as a combination of a memory and a memory controller together, then Huang fully teaches provide a duty cycle adjuster (DCA) code to the memory device; because memory device is recognized as whole in Fig. 6, the DCA code sent into the controller (as part of the memory device (Fig. 6)), and make the memory device increase/decrease the duty cycle.
Based on above reason, the office believe Huang fully teaches the claim 7-12.
Conclusion
22. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
23. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Han Yang whose telephone is (571) 270-3048. The examiner can normally be reached on Monday-Friday 8am-5pm with alternate Friday off. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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HY
06/18/2026
/HAN YANG/
Primary Examiner, Art Unit 2824
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