DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12 May 2026 has been entered.
Priority
Claims 1-20 include certain subject matter that is not supported by U.S. Provisional Application No. 63/573,367. The Examiner notes that individual claims have their own priority dates and a claim only receives the benefit of an effective filing date of the provisional application if the provisional application fully supports the claim (see MPEP 2152.01). Therefore, each of the claims in the current application, which are not fully supported by the provisional application, has a priority date of 01 October 2024, which is the filing date of the current application.
CLAIM INTERPRETATION
Claims in this application are not interpreted under 35 U.S.C. §112(f).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 9, 12-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. US 2020/0004675 A1 (Park) in view of US Patent Application Publication No. US 2021/0034130 A1 (Guim) in further view of further view of the article by Simon Southwell, titled “PCI Express Primer #4: Configuration Space”, published 17 August 2022 on LinkedIn and preserved by the Internet Archive on 26 July 2024 (Southwell) in further view of US Patent Application Publication No. US 2023/0379682 A1 (Chen).
Regarding claim 1 and analogous claims 12 and 20:
Park teaches, a method for memory management, the method comprising: receiving, by a memory device, a host command comprising first data, the first data being associated with a first location of a non-volatile memory (by disclosing an electronic device (100) [Fig. 1]. The electronic device (100) receives a CMD from the host (10) [Fig. 1] [0020-0022]. Receiving a command includes receiving a write command and data for writing the data into the electronic device (100) [0021]. The received command may also include metadata and a logical block address (a first location of a non-volatile memory), and may first be buffered in a volatile memory [0041-0043] [0062]. The metadata may be associated with a name space [0064] (a first location of a non-volatile memory). The memory system may be controlled by a memory controller (110) including a processor (112) executing firmware (FW) [Fig. 2]. The electronic device (100) may be a PCI E card type memory device [0033]), based on a flush request and based on the first priority information, writing, by the memory device, the first data from a volatile memory to the non-volatile memory (by teaching that in response to a sudden power off (SPO) and receiving a control signal from the processor (112) (flush request), and based on a namespace and a corresponding priority associated with that namespace, data may be preferentially flushed from the buffer (volatile memory) to the non-volatile memory based on the priority of the namespace of the data [0081-086]. The namespaces may be flushed according to a priority order because there may not be enough power in a backup power source to flush all of the namespaces [0067-0068] [0081-0086]).
Park does not explicitly disclose, but Guim teaches that a received command to store data may include an indicated priority (i.e., a host command comprising first priority information associated with first data as taught through the combination with Park) (by teaching that a level of criticality may be provided by the software stack and conveyed as part of the data payloads [0045]) storing, by the memory device, the first priority information in a priority table of the memory device, the priority table comprising status information generated by the memory device (by teaching the resource (510) that may keep track in a table of memory ranges or list of ranges, an amount of power needed to flush the memory range (status information generated by the memory device), and a priority/criticality of the data for the memory range in a table for data that it needs to flush, such data stored in a volatile memory or cache [Fig. 5A] [0046-0047]) accessing, by the memory device, the first priority information from the first priority table, and based on the first priority information, flushing the data (by teaching that a priority based manager can query all resources in response to a power outage to access the fields in the table indicating the priority of data and the amount of power to flush. The power manager can then allocate backup power to the resources based on the priority of the data, and the resources can perform data flushing to persistent media using allocated backup power according to a priority order of the data [0046-0050]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the flushing of namespaces according to a priority when there is not enough power to backup all namespaces in the event of a power loss as taught by Park to include receiving an associated priority with the data or application storing the data as part of the storage request, and storing the memory ranges and priorities in a table with an estimated power to flush the data (status) so that they can be reported to a power manager to negotiate for an amount of backup power and then later used to flush the data according to a priority order as taught by Guim.
One of ordinary skill in the art would have been motivated to make this modification because it may allow an application to resume as though only interrupted and may allow for backup power to be effectively allocated according to priority as taught by Guim in [0029] [0032].
Park does not explicitly disclose, but Southwell teaches, one or more command and status registers (CSR) (by teaching that PCI Express endpoints (i.e., the PCI-E Card type memory device taught by Park) are outfitted with a PCIe type 0 configuration space set of registers, which includes a set of common registers, the configuration space, and a PCIe capability structure, which includes PCIe capabilities register [pg. 2, ¶1] [pg. 3, ¶3] [pg. 6, last ¶ - continued through pg. 9, ¶2]. In sum, these registers may be considered “command and status registers” (CSRs) as they define registers for host/cpu control of the endpoint (command register) and they define registers for the endpoint (i.e., PCI-E card type memory device taught by Park (i.e., memory device)) to indicate status to the host/cpu (status register) [pg. 1, ¶1]. For example, these registers include command registers that allow global control of the device, and status registers that the device can use to indicate status, such as detected errors [pg. 2, ¶¶3-4] [pg. 3, ¶3 – pg. 4, ¶4] [pgs. 7-8 – bullets discussing “device capabilities register” fields, “device control register” fields, and “] [pg. 9, §Extended Capabilities – continued through pg. 10]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the PCI-E card memory device as taught by Park to include the PCIe configuration space, common, and capability registers, which are accessible to a host/cpu to inspect the capabilities and status and set parameters in the PCIe endpoint device (i.e., the PCI-E card memory device as taught by Park) as taught by Southwell.
One of ordinary skill in the art would have been motivated to make this modification because it would allow it to be compatible with the PCIe specification, be backward compatible with the original PCI specification, and by implementing the extended capabilities of the PCIe specification, enhance functionality for the operating system (i.e., of the host) as taught by Southwell in [pg. 1].
Guim does not explicitly disclose, but Chen teaches, the priority table being accessible to a host via one or more control and status registers (CSR) of the memory device (by teaching a set of registers (730, 735) implemented as configuration registers compliant with a PCIe based protocol [0053]. The registers may implement a bound memory table (735), with entries that indicate a priority level associated with the described block of memory in a memory range. A higher priority indicates cache lines that should be flushed firstly over other cache lines with a lower priority. The priority levels in the bound memory table may be set by a host by writing to a control register (730) (i.e., the priority table being accessible to a host via one or more CSR of the memory device) [0054-0055]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the priorities in the table used to flush data from the resources according to a priority order and amount of power needed to flush each range as taught by Park in view of Guim to include being stored in registers of the PCIe configuration space (i.e., control and status registers as taught by Southwell) and modifiable (accessible) by a host write to a control register of the PCIe configuration space (i.e., control and status registers as taught by Southwell) as taught by Chen.
One of ordinary skill in the art would have been motivated to make this modification because it would allow the priority levels indicating which data should be flushed firstly to be dynamically modifiable by the host as taught by Chen in [0055] and placing them in the configuration space registers allows the driver software to inspect the capabilities and status advertised by the device and set parameters as taught by Southwell in [pg. 1, ¶1].
Regarding claim 2 and analogous claim 13:
The method of claim 1 is made obvious by Park in view of Guim in further view of Southwell in further view of Chen (Park-Guim-Southwell-Chen).
Park further discloses, wherein: the memory device comprises a host interface ((111) [Fig. 2]) configured to receive the host command from the host via a first protocol (the host interface (111) can implement one of the various protocols listed in [0037]) and the host command comprises first location information for identifying the first location of the non-volatile memory (by teaching that a host request address may include an LBA that may be translated into a physical address for writing data to the non-volatile memory device. Furthermore, the denoted namespace may indicate a partition of the non-volatile memory [0063-0065]).
Regarding claim 3 and analogous claim 14:
The method of claim 1 is made obvious by Park-Guim-Southwell-Chen.
Park further discloses, further comprising receiving, by the memory device, the flush request based on a power event (by teaching that in response to a sudden power off (SPO) and receiving a control signal from the processor (112) (flush request), and based on a namespace and a corresponding priority associated with that namespace, data may be preferentially flushed from the buffer (volatile memory) to the non-volatile memory based on the priority of the namespace of the data [0081-086]).
Regarding claim 4 and analogous claim 15:
The method of claim 1 is made obvious by Park-Guim-Southwell-Chen.
Park discloses wherein the memory device comprises a cache controller for initiating, based on the flush request, flushing operations according to priority levels (by teaching the memory controller (113), which flushes the cached data cached in the buffer memory (115) into the non-volatile memory (120) according to the priority of the namespaces [Figs. 1-2] [0062] [0066-0068]).
Park does not explicitly disclose, but Guim teaches according to priority levels in the priority table (by teaching that a priority based manager can query all resources in response to a power outage to access the fields in the table indicating the priority of data and the amount of power to flush. The power manager can then allocate backup power to the resources based on the priority of the data, and the resources can perform data flushing to persistent media using allocated backup power according to a priority order of the data as indicated by the table [0046-0050]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the flushing of namespaces according to a priority when there is not enough power to backup all namespaces in the event of a power loss as taught by Park to include receiving an associated priority with the data or application storing the data as part of the storage request, and storing the memory ranges and priorities in a table with an estimated power to flush the data so that they can be reported to a power manager to negotiate for an amount of backup power and then later used to flush the data according to a priority order as taught by Guim.
One of ordinary skill in the art would have been motivated to make this modification because it may allow an application to resume as though only interrupted and may allow for backup power to be effectively allocated according to priority as taught by Guim in [0029] [0032].
Regarding claim 5 and analogous claim 16:
The method of claim 1 is made obvious by Park-Guim-Southwell-Chen.
Park further discloses, further comprising: based on the flush request, accessing, by the memory device, address information associated with the first priority information (by teaching that to flush data, a host request may include an LBA, which is translated into a physical address used for storing the data to the non-volatile memory, the request is associated with a namespace, which is associated with a priority (associated with the first priority information) [0063-0067]).
Regarding claim 6 and analogous claim 17:
The method of claim 1 is made obvious by Park-Guim-Southwell-Chen.
Park does not explicitly disclose, but Guim teaches, wherein: the priority table comprises second priority information associated with second data, the second data being associated with a second location of the non-volatile memory, the second priority information being different from the first priority information; and the method further comprises, based on at least one of the first priority information or the second priority information, determining a relative order for writing the first data and the second data from the volatile memory to the non-volatile memory (by teaching that the table may include a plurality of memory ranges, corresponding power needed to flush each range, and corresponding priorities of each range. The priorities may be different (i.e., critical data level 1, critical data level 2) such that a plurality of address ranges may be flushed according to a priority order [Fig. 5A] [0044-0056]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the flushing of namespaces according to a priority when there is not enough power to backup all namespaces in the event of a power loss as taught by Park to include receiving an associated priority with the data or application storing the data as part of the storage request, and storing the memory ranges and priorities in a table with an estimated power to flush the data so that they can be reported to a power manager to negotiate for an amount of backup power and then later used to flush the data according to a priority order as taught by Guim.
One of ordinary skill in the art would have been motivated to make this modification because it may allow an application to resume as though only interrupted and may allow for backup power to be effectively allocated according to priority as taught by Guim in [0029] [0032].
Regarding claim 9:
The method of claim 1 is made obvious by Park-Guim-Southwell-Chen.
Park further discloses, wherein the memory device prioritizes the writing of the first data over writing second data from the volatile memory to the non-volatile memory based on the first data being associated with a higher priority level than the second data (by teaching that some namespace data are prioritized for flushing over other namespace data when there is not enough power to flush all the namespaces [0067-0068] [0081-0086]).
Claims 7-8 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Park-Guim-Southwell-Chen in further view of US Patent Application Publication No. US 2020/0104056 A1 (Benisty).
Regarding claim 7 and analogous claim 18:
The method of claim 1 is made obvious by Park-Guim-Southwell-Chen.
Park further discloses receiving a first device command associated with writing first data from the volatile memory to the non-volatile memory with a receiving a second device command associated with writing second data from the volatile memory to the non-volatile memory (by teaching that write data received from the host (110) as part of a write command is cached in the buffer memory (115). The memory device may receive a plurality of write commands, including commands associated with different namespaces, such that it would have to flush data associated with multiple namespaces [0021] [0063-0067] [0081-0085]).
Park does not explicitly disclose, but Benisty teaches that the commands may be received in first queue associated with a first priority level and by a second queue associated with a second priority level (by teaching that queues may be stored in the controller memory buffer (CMB), which may be in the RAM (116) [0046]. Additionally, there may be a plurality of namespaces, which are associated with different priorities (first and second priority level). Each namespace may have its own queue (first and second queue) [0072] [0078] [0091]. The commands are for writing data to the memory (104) [Fig 2A] [Fig. 10]. The namespaces and therefore queues are given different priority levels such that a different number of resources are allocated to the different namespaces, in this way one namespace may receive more resources than another [0072] [0078] [0091]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the write commands for the different namespaces which include write data cached in a buffer memory as taught by Park to include being received in namespace queues, where the namespaces are allocated different amounts of resources based on a namespace priority as taught by Benisty.
One of ordinary skill in the art would have been motivated to make this modification because it would allow the implementation of a QoS methodology where each queue is known to have certain performance parameters, and it allows namespaces to have guaranteed performance levels without being starved by other higher priority commands as taught by Benisty in [0072] [0078].
Regarding claim 8 and analogous claim 19:
The method of claim 7 is made obvious by Park-Guim-Southwell-Chen in further view of Benisty.
Park does not explicitly disclose, but Benisty teaches, wherein the first queue and the second queue are associated with at least one of a priority scheme or an arbitration scheme configured by software (by teaching that which queue is executed from next is based on a priority arbitration scheme based on available resources as seen in [Fig. 9] and as configured by a host command (904) as implemented by software running on the controller (802) [0038] [0077-0079] [0083-0094]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the write commands for the different namespaces which include write data cached in a buffer memory as taught by Park to include being received in namespace queues, where the namespaces are allocated different amounts of resources based on a namespace priority as configured by the controller from instructions from a host as taught by Benisty.
One of ordinary skill in the art would have been motivated to make this modification because it would allow the implementation of a QoS methodology where each queue is known to have certain performance parameters, and it allows namespaces to have guaranteed performance levels without being starved by other higher priority commands as taught by Benisty in [0072] [0078].
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Park-Guim-Southwell-Chen in further view of US Patent Application Publication No. US 2005/0117418 A1 (Jewell).
Regarding claim 10:
The method of claim 1 is made obvious by Park-Guim-Southwell-Chen.
Park does not explicitly disclose, but Jewell teaches, wherein the status information comprises confidence level information that is determined based on an energy level associated with the memory device (by teaching that whether or not the number of hardened pages exceeds a guarantee (whether the backup power is sufficient to backup all the pages the host/hosts believe will be backed up), the system enters an exposed state. The exposed state means that not all pages will be able to be backed up because the charge level of the secondary power supply is not sufficient. In this case, the system will need to harden the softened data to reduce the amount of hardened data to the guaranteed level. The system can allocate power to the exposed system according to a priority order [0102-0108]. The system may enter the exposed state due to re-estimating the power capacity of the battery due to aging [0101]. The system needs to inform the clients of the exposed state so that they may soften their pages as quickly as possible [0032] [0043] [0046] [0055] [0084] [0096] [0104]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the status information in the priority table as taught by Park in view of Guim to include an indication of whether the pages are hardened or softened, whether the system is exposed (confidence level), and how many pages need to be written to reduce the number of pages to the guaranteed amount for hardening (confidence level) as taught by Jewell.
One of ordinary skill in the art would have been motivated to make this modification because the power manager could use this information to place the system into a read-only state so that more hardened data is not written that worsens the number of exposed pages and returns the system to a read/write state as quickly as possible, and reporting this information to the clients could allow them to soften pages to also return the system to a guaranteed state more quickly, so that the system is not exposed and they won’t need to have pages hardened in a priority order where some will lose the pages permanently in a power loss as taught by Jewell in [0096] [0105-0108].
Regarding claim 11:
The method of claim 10 is made obvious by Park-Guim-Southwell-Chen in further view of Jewell.
Park does not explicitly disclose, but Jewell teaches, wherein: the confidence level information is determined based on an amount of energy that is consumed for storing the first data to the non-volatile memory; and the first priority information is determined based on the confidence level information (by teaching that whether or not the number of hardened pages exceeds a guarantee (whether the backup power is sufficient to backup all the pages the host/hosts believe will be backed up (i.e., determined based on an amount of energy that is consumed for storing the first data to the non-volatile memory)), the system enters an exposed state. The exposed state means that not all pages will be able to be backed up because the charge level of the secondary power supply is not sufficient. In this case, the system will need to harden the softened data to reduce the amount of hardened data to the guaranteed level. The system can allocate power to the exposed system according to a priority order [0102-0108]. The system may enter the exposed state due to re-estimating the power capacity of the battery due to aging [0101]. The system may also inform the clients of the exposed state so that they may soften their pages. Softening pages means that pages that were marked as being hardened (needing to be stored in non-volatile memory) are no longer required to be hardened (and accordingly do not need to be stored to volatile memory) [0032] [0043] [0046] [0055] [0084] [0096] [0104]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the information in the priority table as taught by Park in view of Guim to include an indication of whether the pages are hardened or softened, whether the system is exposed (confidence level), and how many pages need to be written to non-volatile memory or softened (marked as no longer needing to be saved to non-volatile memory (have their priority reduced) (priority determined based on confidence level information) to reduce the number of pages to the guaranteed amount for hardening (confidence level) as taught by Jewell.
One of ordinary skill in the art would have been motivated to make this modification because the power manager could use this information to place the system into a read-only state so that more hardened data is not written that worsens the number of exposed pages and returns the system to a read/write state as quickly as possible, and reporting this information to the clients could allow them to soften pages to also return the system to a guaranteed state more quickly, so that the system is not exposed and they won’t need to have pages hardened in a priority order where some will lose the pages permanently in a power loss as taught by Jewell in [0096] [0105-0108].
Response to Amendments/Arguments
Applicant' s arguments with respect to claims 1-20 have been considered but not persuasive. For example, Guim teaches a priority table storing status information generated by the memory device by teaching to store an amount of power to flush metric in the table with the priorities of the data. Southwell teaches a control and status register by teaching the PCIe configuration space registers, and Chen teaches to store the priority table (as taught by Southwell) in the PCIe configuration space registers so that a host may use command registers of the PCIe configuration space registers to dynamically alter the priorities in the table. Accordingly, the new combination of references including Southwell makes obvious the claimed invention, and Applicant’s arguments are not persuasive.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Patent Application Publication No. US 2021/0056016 A1 (Bulusu) – teaches a flush aperture that stores data marked as critical for flushing from a volatile to a non-volatile memory during a power loss event [Fig. 8]. Critical data will be flushed before non-critical data [0287]. The flushing process may include an order based on criticality [00234-247].
US Patent Application Publication No. US 2019/0227712 A1 (Katarina) – teaches that high priority data packets may be flushed first from volatile cache to non-volatile memory according to a priority/criticality of the data [0027].
US Patent No. US 10,783,048 B2 (Kumar) – teaches that memory modules are assigned a priority and during a power loss, data from each of the memory modules is preserved to a non-volatile memory according to the priority order [Fig. 8].
US Patent Application Publication No. US 2019/0042113 A1 (Li) – teaches to persist metadata from a volatile to a non-volatile memory according to a priority of the metadata [Fig. 3C] [0018].
US Patent Application Publication No. US 2018/0285260 A1 (Lu) – teaches a cache priority table includes entries of the memory side cache address space and indicates a priority of the data for restoration after a power loss [0035]. The cache data may also be persisted in response to the power loss according to a priority order or level of criticality [0038].
US Patent Application Publication No. US 2015/0293714 A1 (Matsubara) – teaches persisting data from the devices with the smallest caches first so that power may be removed from those caches, which may then be used to continue to persist data from the larger caches, which allows more data to be persisted than other orders which requires all caches to be powered for longer [Figs. 13-14] [0194-0207].
US Patent Application Publication No. US 2023/0400988 A1 (Muthiah) – recognizes the importance of saving the most important data first because not all data may be able to be persisted from a volatile to a non-volatile memory based on an available power after a power loss event [0031].
US Patent Application Publication No. US 2019/0107950 A1 (Sankaranarayanan) – teaches a criticality/save registers that indicates whether each memory range in the volatile memory is supposed to be backed up to non-volatile memory in the event of a power loss [Fig. 1] [0026].
US Patent Application Publication No. US 2021/0141433 A1 (Watt) – teaches to save more important data first as not all data may be able to be persisted from a volatile to non-volatile memory in light of a power failure [0036-0042]).
US Patent Application Publication No. US 2016/0267007 A1 (Zheng) – teaches backup priority information (730) that is used to selectively back up important data, such as dirty data, from volatile to non-volatile memory in response to a power failure [0121-0126] [0138].
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CURTIS JAMES KORTMAN whose telephone number is (303) 297-4404. The examiner can normally be reached Monday through Friday 7:30 AM through 4:00 PM MT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CURTIS JAMES KORTMAN/ Primary Examiner, Art Unit 2139
Prosecution Insights