DETAILED ACTION
This action is responsive to 10/01/2024.
Claims 1-11 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Uehara et al. (US Pub. 2023/0378292), hereinafter Uehara.
Regarding claim 1, Uehara discloses a vertical silicon carbide semiconductor device formed in a semiconductor chip having two main surfaces opposite to each other (a silicon carbide (SiC) semiconductor device having two surfaces (10a, 10b) opposite to each other-see fig. 2), comprising: a silicon carbide substrate (n+-type substrate made of SiC-see fig. 2 and [0037]); a buffer layer that is an epitaxial layer on the silicon carbide substrate (an n-type buffer layer 12 made of SiC-see fig. 2 and [0038]) [[:]]; another epitaxial layer having a doping concentration in a range of 1×1015/cm3 to 1×1016/cm3 on the buffer layer (low-concentration layer 13 has a concentration of 5.0 to 10.0x1015/cm3-see fig. 2 and [0039]); and electrodes on each of the two main surfaces of the semiconductor chip (source electrode 28 on the surface 10a and drain electrode 31 on the other surface 10b-see fig. 2), wherein the buffer layer has a doping concentration that is higher than the doping concentration of the another epitaxial layer but not more than 3×1017/cm3 (the buffer layer is designed to have an n-type impurity concentration between substrate 11 and the low-concentration layer 13 (see [0038]), the low-concentration layer has a concentration of 5.0 to 10.0x1015/cm3 (see [0039]) and the substrate 11 has a concentration of 1.0x1019/cm3. A concentration for the buffer layer that is higher than that of the low-concentration layer 13, but not more than 3×1017/cm3 can be selected between these two ranges), and the silicon carbide semiconductor device is free of a defect that extends from the silicon carbide substrate to the another epitaxial layer (see, for example, fig. 5, [0026], [0077], and [0081], which further disclose that basal plane dislocation (BPD) can expand to stacking fault (SF), which can lead to on-voltage increase, but defect portions D are formed in a JFET portion 14 in the present embodiment, as a result, when SiC semiconductor device S1 is in reverse conduction, the defect portions D function as hole traps, making it possible to suppress holes from reaching the low-concentration layer 13. As a result, it is possible to suppress the BPD from expanding to the SF, and it is possible to suppress an increase in an on-voltage).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uehara in view of Tanaka et al. (US Pub. 2019/0145021), hereinafter Tanaka.
Regarding claim 2, Uehara does not appear to expressly disclose further comprising a transition layer disposed between the silicon carbide substrate and the another epitaxial layer, the transition layer having a doping concentration between the doping concentration of the buffer layer and a doping concentration of the silicon carbide substrate.
Tanaka is relied upon to teach further comprising a transition layer disposed between the silicon carbide substrate and the another epitaxial layer, the transition layer having a doping concentration between the doping concentration of the buffer layer and a doping concentration of the silicon carbide substrate (see, see for example fig. 6 with description in [0075]-[0076], which illustrates a modification of an epitaxial substrate 3 (see fig. 3) to include an epitaxial layer 4 with a four-ply structure comprising a third epitaxial layer 43 having a higher n-type impurity concentration than a fourth epitaxial layer 44 and is provided between a single crystal substrate 10 comprising n-type SiC, and the fourth epitaxial layer 44).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Tanaka with the invention of Uehara to include a transition layer having a doping concentration that is between that of the buffer layer and the silicon substrate and disposed between the silicon carbide substrate and the another epitaxial layer, as taught by Tanaka, which enables a region having rejoined carriers to be physically separated from a region having an unfavorable dislocation, thereby preventing staking fault expansion (see [0076]).
Regarding claim 3, Tanaka is further relied upon to teach wherein the transition layer is thinner than the buffer layer (see, for example, fig. 6, thickness of the third epitaxial layer 43 is less than combined thickness of the first and the second epitaxial layers 41 and 42 (buffer layer-see [0030])).
Claims 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uehara in view of Noguchi (US Pub. 2021/0296433).
Regarding claim 6, Uehara discloses a vertical silicon carbide semiconductor device formed in a semiconductor chip having two main surfaces opposite to each other (a silicon carbide (SiC) semiconductor device having two surfaces (10a, 10b) opposite to each other-see fig. 2), comprising: a silicon carbide substrate (n+-type substrate made of SiC-see fig. 2 and [0037]); a buffer layer that is an epitaxial layer on the silicon carbide substrate (an n-type buffer layer 12 made of SiC-see fig. 2 and [0038])[[:]]; another epitaxial layer having a doping concentration in a range of 1×1015/cm3 to 1×1016/cm3 on the buffer layer (low-concentration layer 13 has a concentration of 5.0 to 10.0x1015/cm3-see fig. 2 and [0039]); and electrodes on each of two main surfaces of a semiconductor chip (source electrode 28 on the surface 10a and drain electrode 31 on the other surface 10b-see fig. 2), wherein the buffer layer has a doping concentration that is higher than the doping concentration of the another epitaxial layer but not more than 3×1017/cm3 (the buffer layer is designed to have an n-type impurity concentration between substrate 11 and the low-concentration layer 13 (see [0038]), the low-concentration layer has a concentration of 5.0 to 10.0x1015/cm3 (see [0039]) and the substrate 11 has a concentration of 1.0x1019/cm3. A concentration for the buffer layer that is higher than that of the low-concentration layer 13, but not more than 3×1017/cm3 can be selected between these two ranges), the silicon carbide semiconductor device is free of a first defect that extends from the silicon carbide substrate to the another epitaxial layer (see, for example, fig. 5, [0026], [0077], and [0081], which further disclose that basal plane dislocation (BPD) can expand to stacking fault (SF), which can lead to on-voltage increase, but defect portions D are formed in a JFET portion 14 in the present embodiment, as a result, when SiC semiconductor device S1 is in reverse conduction, the defect portions D function as hole traps, making it possible to suppress holes from reaching the low-concentration layer 13. As a result, it is possible to suppress the BPD from expanding to the SF, and it is possible to suppress an increase in an on-voltage).
Uehara does not appear to expressly disclose and the silicon carbide semiconductor device includes a second defect that is related to epitaxy growth, the second defect being provided in the another epitaxial layer generated during the epitaxy.
Noguchi, for example in fig. 3, [0003], and [0029], teaches crystal defects that occur upon epitaxial growth of a silicon carbide layer 2, and includes a plurality of defects such as, mainly, a triangle defect 12, downfall defect 13, and carrot defect 14.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Noguchi with the invention of Uehara to include other defects, such as defects crystal defects occurring upon epitaxial growth, which constitutes combining prior art elements according to known methods to yield predictable results (i.e., identify and solve the problem of defects in order to obtain a silicon carbide semiconductor device which can improve yield-see [0004]).
Regarding claim 7, Uehara discloses wherein the doping concentration of the buffer layer is not more than 3×1017/cm3 (the buffer layer is designed to have an n-type impurity concentration between substrate 11 and the low-concentration layer 13 (see [0038]), the low-concentration layer has a concentration of 5.0 to 10.0x1015/cm3 (see [0039]) and the substrate 11 has a concentration of 1.0x1019/cm3. A concentration for the buffer layer higher than that of the low-concentration layer 13, but not more than 3×1017/cm3 can be selected between these two ranges).
Regarding claim 8, Uehara in view of Noguchi does not appear to expressly disclose further comprising a transition layer disposed between the buffer layer and the another epitaxial layer, the transition layer having a doping concentration that is higher than the doping concentration of the buffer layer.
Tanaka is further relied upon to teach further comprising a transition layer disposed between the buffer layer and the another epitaxial layer, the transition layer having a doping concentration that is higher than the doping concentration of the buffer layer (see, see for example fig. 6 with description in [0075]-[0076], which illustrates a modification of an epitaxial substrate 3 (see fig. 3) to include an epitaxial layer 4 with a four-ply structure comprising a third epitaxial layer 43 having a higher n-type impurity concentration than a fourth epitaxial layer 44 and is provided between a single crystal substrate 10 comprising n-type SiC, and the fourth epitaxial layer 44).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Tanaka with the inventions of Uehara and Noguchi to include a transition layer having a doping concentration that is between that of the buffer layer and the silicon substrate and disposed between the silicon carbide substrate and the another epitaxial layer, as taught by Tanaka, which enables a region having rejoined carriers to be physically separated from a region having an unfavorable dislocation, thereby preventing staking fault expansion (see [0076]).
Allowable Subject Matter
Claims 4-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The applied references or any other reference of record fails to teach or suggest “wherein the buffer layer is a first buffer layer, further comprising a second buffer layer disposed between the silicon carbide substrate and the another epitaxial layer, the second buffer layer having a doping concentration between the doping concentration of the transition layer and the doping concentration of the silicon carbide substrate”, as recited in claim 4. Claim 5 depends from claim 4, and is therefore equally indicated as allowable.
Claims 9-11 are allowed.
The following is an examiner’s statement of reasons for allowance: the references of record fail to teach or suggest “. A method of manufacturing a vertical silicon carbide semiconductor device having electrodes on each of two main surfaces of a semiconductor chip that includes a low concentration buffer layer and an epitaxial layer that are grown on a silicon carbide substrate by epitaxy, the method comprising: as a pre-process, preparing a semiconductor wafer in which the low concentration buffer layer and the epitaxial layer are grown on the silicon carbide substrate by epitaxy; as a first detecting process, using a photoluminescence (PL) image of the low concentration buffer layer to detect a first defect that extends from the silicon carbide substrate to the epitaxial layer and a second defect that is generated in the epitaxial layer during the epitaxy; as a second detecting process, using a PL image of the epitaxial layer to detect the second defect; as a third detecting process, detecting the first defect based on a difference between detection results of the first detecting process and the second detecting process; as a forming process, forming a predetermined device structure in the semiconductor wafer; as a cutting process, dicing the semiconductor wafer into a plurality of individual semiconductor chips after the forming process; and as a selecting process, selecting from the plurality of semiconductor chips, one free of the first defect, based on a result of the third detecting process”, as recited in claim 9. Claims 10-11 depend from and recite limitations that further narrow claim 9, and are therefore equally allowed.
Representative prior art includes Nishihara et al. (US Pub. 2020/0116649), which teaches a method for manufacturing a SiC substrate that includes an evaluation step (see [0019]-[0020]) that includes observing a bar-shaped stacking fault by irradiating a first surface of the SiC substrate before stacking an epitaxial layer with excitation light and extracting light having a wavelength range of equal to or greater than 405 nm and equal to or less than 445 nm in photoluminescence light beams emitted from a first surface. However, Nishihara fails to teach or suggest the first to third detection steps outlined in claim 9 above.
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARDIS F AZONGHA whose telephone number is (571)270-7706. The examiner can normally be reached 10AM-7:00PM.
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/SARDIS F AZONGHA/Primary Examiner, Art Unit 2627
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