DETAILED ACTION
This action is responsive to the following communications: Application filed on Oct. 01, 2024.
Claims 1-18 are presented for Examination. Claim 1 is independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-18 are rejected under 35 U.S.C. § 101 because the claimed invention is directed to a judicial exception (i.e., an abstract idea) without significantly more.
Step 1 – Statutory Categories
Claims 1–5 recite a process. Claims 6–8 and 16–18 recite a machine. Claims 9–15 recite a manufacture. All claims therefore fall within a statutory category.
Step 2A – Prong One: Judicial Exception (Abstract Idea)
The claims recite abstract ideas in the form of mathematical concepts and mental processes.
Independent Claim 1 recites:
“determining a first turn-off negative voltage model and a second turn-off negative voltage model”;
“inputting the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the minimum turn-on voltage into the first turn-off negative voltage model to obtain a turn-off negative voltage upper limit absolute value”;
“inputting the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the maximum bearable negative voltage absolute value into the second turn-off negative voltage model to obtain a turn-off negative voltage lower limit absolute value”; and
“determining a turn-off negative voltage interval … based on the turn-off negative voltage upper limit absolute value and the turn-off negative voltage lower limit absolute value.”These limitations describe the creation and use of mathematical models (functions/equations) to calculate numerical limits. The specification confirms that the models are mathematical expressions (see, e.g., paragraphs [0064]–[0068] disclosing polynomial equations of the form
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where VSS_min represents the turn-off negative voltage upper limit absolute value, λ1 represents a first derating parameter, f 1(RG_on, RG_off, VDC) represents a function expression corresponding to the first turn-off negative voltage model, RG_on represents the turn-on gate resistance, RG_off represents the turn-off gate resistance, VDC represents the bus voltage, and Vth represents the minimum turn-on voltage.
Dependent claims 2–5 merely narrow the mathematical form of the models or specify input parameters. Claims 6–8 and 16–18 merely recite generic computer components or a storage medium performing the same mathematical operations. Claims 9–15 add conventional circuit elements that serve only as inputs or outputs to the mathematical models.
The claims therefore recite an abstract idea.
Step 2A – Prong Two: Integration into a Practical Application
The judicial exception is not integrated into a practical application.
The claims do not: Improve the functioning of a computer or other technology;
Apply the abstract idea with a particular machine beyond generic components;
Effect a transformation of a particular article; or
Apply the idea in any meaningful way beyond generally linking it to the technological environment of power electronics or inverters.
While the preamble and dependent claims mention a “switching transistor,” “inverter,” or “vehicle,” these elements are used only as sources of input parameters or as the ultimate field of use. The focus of the claims remains on the mathematical determination of voltage limits.
Step 2B – Inventive Concept
The claims do not include additional elements that amount to significantly more than the abstract idea. The recited parameters (gate resistances, bus voltage, threshold voltages) and circuit elements (driver, controller, resistors) are well-understood, routine, and conventional in power electronics. The mathematical models themselves do not constitute an inventive concept.
Accordingly, claims 1-18 are rejected under 35 U.S.C. § 101.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-18 are rejected under 35 U.S.C. § 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor regards as the invention.
Claim 1 – recited limitations of “determining a first turn-off negative voltage model and a second turn-off negative voltage model” is indefinite. The claim does not specify how the models are determined, what form they take (e.g., polynomial equation, lookup table, neural network, data mapping), or how the specific coefficients or functional relationships are derived. The phrase “function expression corresponding to the first turn-off negative voltage model” appearing in dependent claims 2 and 3 is likewise indefinite because the claim does not identify the particular function expression or its structural relationship to the physical parameters.
The limitations “inputting … into the first turn-off negative voltage model to obtain a turn-off negative voltage upper limit absolute value” and
“inputting … into the second turn-off negative voltage model to obtain a turn-off negative voltage lower limit absolute value” are indefinite because it is unclear what specific operations are performed by the “model” and how the output values are mathematically derived from the recited inputs.
Claim 6 recites “a first determining module,” “an acquiring module,” and “a second determining module.” These limitations invoke 35 U.S.C. § 112(f). However, the specification does not provide sufficient algorithmic structure corresponding to the claimed functions. While paragraphs [0094]–[0098] describe high-level steps, they fail to disclose the specific algorithms or rules by which the “modules” determine the models or calculate the voltage limits. Therefore, the claim is indefinite.
Claim 9 recited limitations of “the controller is configured to acquire a turn-off negative voltage interval … by implementing the method according to claim 1, and control the drive power supply to provide a negative turn-off voltage to the driver based on the turn-off negative voltage interval” is indefinite. It is unclear how the controller acquires the interval, what specific signals or data paths are used, and how the negative turn-off voltage is selected or applied in relation to the claimed interval.
Claims 10–15 Claims 10–15 recite specific pin connections, resistors, diodes, and coupling capacitors but fail to define the electrical characteristics, values, or operational relationships necessary to achieve the claimed functionality. For example, claim 10 does not specify the voltage levels at the positive and negative power pins or how they relate to the turn-off negative voltage interval determined by the method of claim 1. These limitations render the claims indefinite.
Claims 16–18 depend from claim 9 and are indefinite for the same reasons set forth above with respect to claim 9.
Appropriate correction is requested.
. Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-18 are rejected under 35 U.S.C. § 103 as being unpatentable over U.S. Patent Application Publication No. US 2023/0327577 A1 to Saito et al. (“Saito”) in view of U.S. Patent Application Publication No. US 2021/0021258 A1 to Wang et al. (“Wang”).
Regarding Independent Claim 1, Saito teaches that a method for determining a turn-off negative voltage of a switching transistor, the method comprising:
determining a first turn-off negative voltage model and a second turn-off negative voltage model (Saito, claim 1; para. [0035]; FIG. 19);
acquiring a turn-off gate resistance and a turn-on gate resistance of the switching transistor, a bus voltage, and a minimum turn-on voltage and a maximum bearable negative voltage absolute value of the switching transistor (Saito, para. [0035], [0039]–[0040]; FIG. 3, 7, 18; Wang, para. [0008], [0129], [0179]);
inputting the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the minimum turn-on voltage into the first turn-off negative voltage model to obtain a turn-off negative voltage upper limit absolute value of the switching transistor (Saito, claim 3; para. [0040]; FIG. 15, 16; Wang, para. [0043], eq. (4); para. [0118], eq. (45));
inputting the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the maximum bearable negative voltage absolute value into the second turn-off negative voltage model to obtain a turn-off negative voltage lower limit absolute value of the switching transistor (Saito, para. [0035]; FIG. 15, 16; Wang, para. [0043], eq. (5); para. [0129]); and
determining a turn-off negative voltage interval of the switching transistor based on the turn-off negative voltage upper limit absolute value and the turn-off negative voltage lower limit absolute value (Saito, para. [0035]; FIG. 15, 19; Wang, para. [0179]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Saito and Wang because both references are directed to the same problem of protecting power semiconductor switching elements during turn-off by determining safe upper and lower gate voltage limits. Saito teaches a system-level approach using junction temperature estimation and variable gate resistance to establish voltage boundaries, while Wang teaches the specific parameters (minimum turn-on threshold voltage and maximum bearable negative gate voltage) and mathematical expressions used to calculate those boundaries for SiC MOSFETs. The combination yields a more precise and predictable method for determining the turn-off negative voltage interval.
Regarding Claim 2, Saito teaches that wherein the first turn-off negative voltage model is expressed as:
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where:
VSS_min represents the turn-off negative voltage upper limit absolute value;
λ1 represents a first derating parameter;
f1(RG_on, RG_off, VDC) represents a function expression corresponding to the first turn-off negative voltage model;
RG_on represents the turn-on gate resistance;
RG_off represents the turn-off gate resistance;
VDC represents the bus voltage; and
Vth represents the minimum turn-on voltage.
(Saito, claim 5; para. [0039]; FIG. 3, 4; Wang, para. [0085]).
Regarding Claim 3, Claim 3 recites the second turn-off negative voltage model comprises a function expression involving a second derating parameter, the turn-on gate resistance, the turn-off gate resistance, and the bus voltage (Saito, para. [0048]–[0049]; FIG. 16; Wang, para. [0176], eq. (29)).
Regarding Claim 4, Claim 4 recites setting a negative value of the upper limit absolute value as an upper limit voltage and a negative value of the lower limit absolute value as a lower limit voltage to determine the interval (Saito, para. [0035]; FIG. 19; Wang, para. [0043], [0179]).
Regarding Claim 5, Claim 5 recites that the switching transistor is a silicon-carbide MOS transistor (Wang, Abstract; para. [0002], [0129]).
Regarding Claim 6, Claim 6 recites an apparatus comprising a first determining module, an acquiring module, and a second determining module configured to perform the steps of claim 1 (Saito, claim 1; FIG. 2 (inverter control unit 28, loss calculating unit 31, junction temperature estimate calculating unit 32, gate resistance changing unit 41)).Regarding Claim 7, Claim 7 recites an inverter comprising a memory, a processor, and a program stored in the memory to execute the method of claim 1 (Saito, FIG. 2; claim 1 (inverter control unit 28 on control board 11)).
Regarding Claim 8, Claim 8 recites a non-transitory computer-readable storage medium storing a program that executes the method of claim 1 (Saito, FIG. 2; control board 11 implementing the junction temperature and gate resistance changing functions).Regarding Claim 9, Claim 7 recites a switching transistor drive control circuit comprising a drive power supply, a driver, and a controller, wherein the controller acquires a turn-off negative voltage interval by implementing the method of claim 1 and controls the drive power supply to provide a negative turn-off voltage to the driver, and the driver drives the switching transistor to turn off based on the negative turn-off voltage (Saito, FIG. 2, 18; para. [0035], [0147]–[0152] (gate driver 29, inverter control unit 28, gate voltage power supply Vcc, variable resistance device 42)).
Regarding Claim 10, Claim 10 recites that the driver comprises a drive chip having a positive power pin connected to a positive turn-on voltage supply terminal, a negative power pin connected to a negative turn-off voltage supply terminal, an input pin connected to the controller, and an output pin (Saito, FIG. 18 (gate driver 29 with Vcc, HV–, OUT, and signal inputs from PWM control unit 27)).
Regarding Claim 11, Claim 11 recites a first gate resistor connected between the output pin of the drive chip and the gate of the switching transistor (Saito, FIG. 18; para. [0147] (resistance elements R10 and R20)).
Regarding Claim 12, Claim 12 recites a first diode and a second gate resistor in the gate drive path (Saito, FIG. 18 (diode elements in series with resistance elements R10/R20 in the gate drive path)).
Regarding Claim 13, Claim 13 recites a second diode connected in parallel with the second gate resistor (Saito, FIG. 18 (diode and resistor configuration in the turn-off gate path)).Regarding Claim 14, Claim 14 recites a coupling capacitor connected between the positive turn-on voltage supply terminal and the negative turn-off voltage supply terminal (Saito, FIG. 2, 18 (gate drive circuit topology for bridge arms)).
Regarding Claim 15, Claim 15 recites that a node between first and second coupling capacitors is connected to a midpoint of a bridge arm or grounded (Saito, FIG. 2 (upper and lower bridge arm configuration with gate drive connections)).
Regarding Claim 16, Claim 11 recites a motor control system comprising the switching transistor drive control circuit of claim 9 (Saito, claim 10; FIG. 2 (motor control unit 26 and inverter control unit 28)).
Regarding Claim 17, Claim 11 recites a compressor comprising the motor control system of claim 16 (Saito, claim 10; FIG. 1 (vehicular electric compressor 1 with motor 3 and inverter circuit)).
Regarding Claim 18, Claim 11 recites a vehicle comprising the compressor of claim 17 (Saito, para. [0180]; claim 10 (inverter device mounted on a vehicle)).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUHAMMAD S ISLAM whose telephone number is (571)272-8439. The examiner can normally be reached 9:30am to 6:00pm.
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/MUHAMMAD S ISLAM/Primary Examiner, Art Unit 2837
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