DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over “Enhancing Lifetime and Security of PCM-based Main Memory with Start-Gap Wear Leveling”, henceforth referred to as Qureshi et al. and further in view of Chinnakkonda Vidyapoornachary et al. (US 9,471,428).
Consider claim 1, Qureshi et al. in view of Chinnakkonda Vidyapoornachary et al. disclose a system comprising :a memory device; and a processing device coupled to the memory device, the processing device to perform operations comprising: identifying at least one unusable management unit (UMU) in a plurality of management units that are designated for wear leveling; storing, in a data structure, a physical address and a logical address of the identified at least one UMU; identifying a modified physical address space by excluding, from a physical address space for wear leveling, the physical address of the identified at least one UMU; identifying a first function that reflects a relationship between the physical address space and the modified physical address space; translating, using the first function, a first value of a register that tracks data movement in the physical address space to a second value of the register; and performing a wear leveling operation using the modified physical address space and the second value of the register, wherein the wear leveling operation moves data of a management unit to a neighboring management unit in a circular manner (Qureshi et al.: 1. Introduction, Fig. 4, 4. Start-Gap wear leveling, 4.1 design, 4.2 mapping of addresses, 5. Address-space randomization, discloses a system with memory, processors and the use of stop-gap wear leveling. Logical addressing is also disclosed. Stop-gap wear leaving moves data in a circular manner. Gap and start registers change (modified) continuously which changes the mapping of logical to physical address space (section 4.2 first sentence.). These registers are used in the wear leveling process. Qureshi et al. discloses that memory can fail, but does not go into detail about how failures are handled. Chinnakkonda Vidyapoornachary et al.: Col. 4 lines 4-20, Col. 5 lines 16-37, discloses the ability to detect a failed block of memory, record (updated L2P table) the failure and retire the block so that it is no longer used for storing data. As for the new limitations, the combination of references teaches having a modified L2P table that excludes bad memory (modified physical address space) and using the ability to detect bad memory and exclude in from the L2P table (first function) to identify the relationship of the new address space excluding bad memory from the memory’s previous configuration. The register values change based on the new mappings excluding bad memory.).
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify the Qureshi et al. reference to include retiring bad blocks as is done in Chinnakkonda Vidyapoornachary et al. because bad blocks are no longer reliable for storing or retrieving data.
Consider claim 2, Qureshi et al. in view of Chinnakkonda Vidyapoornachary et al. disclose the system of claim 1, wherein identifying the at least one UMU further comprises determining that a value of an endurance metric measured at least one of the plurality of management units satisfies a threshold criterion (Chinnakkonda Vidyapoornachary et al.: Col. 4 lines 4-20, Col. 5 lines 16-37, discloses comparing bit rate failures to a threshold.).
Consider claim 3, Qureshi et al. in view of Chinnakkonda Vidyapoornachary et al. disclose the system of claim 1, wherein the data structure comprises a plurality of records, and wherein each record of the plurality of records maps a physical address to a logical address of a UMU (Chinnakkonda Vidyapoornachary et al.: Col. 4 lines 4-20, Col. 5 lines 16-37, discloses the ability to detect a failed block of memory, record (updated L2P table) the failure and retire the block so that it is no longer used for storing data.).
Consider claim 4, Qureshi et al. in view of Chinnakkonda Vidyapoornachary et al. disclose the system of claim 1, wherein performing the wear leveling operation further comprises: translating a target logical address to a modified logical address using a first function; mapping the modified logical address to a modified physical address; and translating the modified physical address to a target physical address using a second function (Qureshi et al.: 1. Introduction, Fig. 4, 4. Start-Gap wear leveling, 4.1 design, 4.2 mapping of addresses, 5. Address-space randomization, discloses a system with memory, processors and the use of stop-gap wear leveling. This type of wear leveling utilizes start and gap registers, gap line. The use of these registers causes a continuous change in the mapping of L2P addresses. Further the use of randomization introduces intermediate addresses to the process.).
Consider claim 5, Qureshi et al. in view of Chinnakkonda Vidyapoornachary et al. disclose the system of claim 4, wherein performing the wear leveling operation further comprises: determining that the target logical address does not correspond to a logical address of a UMU in the data structure (Chinnakkonda Vidyapoornachary et al.: Col. 4 lines 4-20, Col. 5 lines 16-37, discloses the ability to detect a failed block of memory, record (updated L2P table) the failure and retire the block so that it is no longer used for storing data.).
Consider claim 6, Qureshi et al. in view of Chinnakkonda Vidyapoornachary et al. disclose the system of claim 4, wherein mapping the modified logical address to the modified physical address further comprises: copying content stored in a management unit corresponding to the modified logical address to a management unit corresponding to the modified physical address (Qureshi et al.: 1. Introduction, Fig. 4, 4. Start-Gap wear leveling, 4.1 design, 4.2 mapping of addresses, 5. Address-space randomization, discloses a system with memory, processors and the use of stop-gap wear leveling.).
Consider claim 7, Qureshi et al. in view of Chinnakkonda Vidyapoornachary et al. disclose the system of claim 4, wherein performing the wear leveling operation further comprises: using a value stored in a modified first register referencing an adjacent management unit corresponding to the modified logical address; and responsive to mapping the modified logical address to the modified physical address, decrementing the modified first register in a circular manner (Qureshi et al.: 1. Introduction, Fig. 4, 4. Start-Gap wear leveling, 4.1 design, 4.2 mapping of addresses, 5. Address-space randomization, discloses a system with memory, processors and the use of stop-gap wear leveling. This type of wear leveling utilizes start and gap registers, gap line. The use of these registers causes a continuous change in the mapping of L2P addresses. Further the use of randomization introduces intermediate addresses to the process.).
Consider claim 8, Qureshi et al. in view of Chinnakkonda Vidyapoornachary et al. disclose the system of claim 4, wherein performing the wear leveling operation further comprises: using a value stored in a modified second register; and responsive to mapping a plurality of modified logical addresses to a plurality of modified physical address in the modified physical address space, incrementing the modified second register in a circular manner (Qureshi et al.: 1. Introduction, Fig. 4, 4. Start-Gap wear leveling, 4.1 design, 4.2 mapping of addresses, 5. Address-space randomization, discloses a system with memory, processors and the use of stop-gap wear leveling. This type of wear leveling utilizes start and gap registers, gap line. The use of these registers causes a continuous change in the mapping of L2P addresses. Further the use of randomization introduces intermediate addresses to the process.).
Consider claim 9, Qureshi et al. in view of Chinnakkonda Vidyapoornachary et al. disclose the system of claim 4, wherein performing the wear leveling operation is responsive to a number of write operations performed in the memory device satisfying a threshold value (Qureshi et al.: 1. Introduction, Fig. 4, 4. Start-Gap wear leveling, 4.1 design, 4.2 mapping of addresses, 5. Address-space randomization, discloses that start-gap wear leveling occurs every so many writes.).
Consider claim 10, Qureshi et al. in view of Chinnakkonda Vidyapoornachary et al. disclose the system of claim 4, wherein the second function is an inverse function of the first function (Qureshi et al.: 1. Introduction, Fig. 4, 4. Start-Gap wear leveling, 4.1 design, 4.2 mapping of addresses, 5. Address-space randomization, the randomizer is an invertible function.).
Claims 11-16 are the method claims to system claims 1-6 and are rejected in the same manner.
Claims 17-20 are the medium claims to system claims 1-4 and are rejected in the same manner.
Response to Arguments
Applicant's arguments filed 5/18/2026 have been fully considered but they are not persuasive. The applicant’s arguments pertain to the new claim limitations, which have been addressed in the appropriate claim rejections above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ALSIP whose telephone number is (571)270-1182. The examiner can normally be reached M-F 9-5.
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/MICHAEL ALSIP/ Primary Examiner, Art Unit 2136
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