DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 9, 11-15 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (USPN 2016/0086542 A1, hereinafter Lee ‘542) in view of Lee et al. (USPN 2021/0043150 A1, hereinafter Lee ‘150).
As to claim 1, Lee ‘542 teaches a compensation circuit comprising:
a voltage calculator configured to generate a pixel driving voltage drop amount using a pixel driving voltage applied from a power supply and a pixel driving voltage fed back from a central portion of a display panel (see at least fig. 1: shows FEEDBACK UNIT returning VFEED from the panel back to the power supply device; fig. 9: designates “CENTER” and shows the output power supply line coupled back toward the center region, flow of ELVDD_IN/ELVDD_OUT around CENTER; [0008] “the power supply may adjust the voltage level of the power supply voltage applied to the input power supply line to compensate temporal variation of the power supply voltage.”; [0040] “The output power supply line 130 may be coupled … at a predetermined location (e.g., center portion) CENTER of the display panel”; [0043] “each of the input power supply line 120 and output power supply line 130 may have a mesh structure” – note the power supply line includes central and distributed portions across the panel and is not limited to edge nodes);
a gain compensator configured to amplify the generated pixel driving voltage drop amount using a predetermined gain value (see at least [0070] "Compared with a feedback unit 170a in FIG. 7, the feedback unit 170b in FIG. 8 may further include a unit gain buffer UGB coupled between the output power supply line and a third resistor R3. The unit gain buffer UGB may allow the display panel not to be electrically affected by the feedback unit 170b. For example, the unit gain buffer UGB may include an operational amplifier OP having an inverted input terminal coupled to an output terminal of the operational amplifier OP." - note Lee 542 illustrates unity gain, therefore the use of an amplifier with a fixed design-defined gain inherently corresponds to a predetermined gain);
a voltage compensator configured to generate a compensation voltage value for compensating display non-uniformity using the amplified pixel driving voltage drop amount (see at least [0055] "For example, in a case where a display panel 110a displays a box pattern 140a having a predetermined grayscale value as illustrated in FIG. 6A, the amount of voltage drop of a power supply voltage ELVDD may vary over time within one frame 200a or within one sub-frame SF2 as illustrated in FIG. 6B. Thus, the dropped power supply voltage ELVDD_OUT may vary over time."; [0061] "For example, as illustrated in FIG. 6C, the power supply device 150 may increase the power supply voltage ELVDD_IN applied to the display panel 110 during the first time period T1, during which the power supply voltage ELVDD_OUT received from the output power supply line 130 decreases. Further, the power supply device 150 may decrease the power supply voltage ELVDD_IN applied to the display panel 110 during the third time period T3, during which the power supply voltage ELVDD_OUT received from the output power supply line 130 increases. Accordingly, an effective voltage drop at each time period T1, T2, and T3 may be reduced. As a result, the pixels PX at different rows may have substantially the same or similar luminances, even if the respective pixels PX emit light at different time periods T1, T2, and T3. e.g., where the respective pixels PX emit light with the same emission duty cycle to produce the same grayscale value." - note the power supply device increases/decreases ELVDD_IN to reduce voltage drop variations over time and achieve uniform luminance).
Lee ‘542 does not directly teach compensating a gamma reference voltage, nor does it directly teach amplification at other predetermined gain values beyond unity, and wherein a voltage wire is formed in a non-active area on the side of the display panel.
Lee ‘150 teaches a voltage calculator configured to generate a pixel driving voltage drop amount using a pixel driving voltage applied from a power supply and a pixel driving voltage fed back directly from a central portion of a voltage wire formed in a side of a display panel; (see at least [0116] “The gamma reference voltage adjusting unit 161 compares the pixel driving voltage measurement value Vdd_s fed back … with a pixel driving voltage reference value Vdd_r generated by the power supply unit 16 …”; [0117] “a first differential amplifier … to amplify and output a difference value therebetween (a drop amount of the pixel driving voltage)”; [0119] “Vo = R2/R1*(Vdd_r − Vdd_s)” – note the first differential amplifier is the claimed voltage calculator, generation of a pixel driving voltage drop amount is Vdd_r − Vdd_s, pixel driving voltage applied is Vdd_r, a fed-back pixel driving voltage is Vdd_s and [0106] “the first power line 101 supplying the pixel driving voltage Vdd to the pixel is connected in a mesh form, and a widthwise wiring … is arranged for each horizontal line”; [0107] “the sensing line 104 may be connected to the widthwise wiring of the first power line 101 through a sensing switch transistor T101 controlled by using the scan signal”; [0108] “the widthwise wiring of the first power line 101 disposed on the corresponding horizontal line is connected to the sensing line 104, and the actual value Vdd_s … is supplied to the power supply unit 16 via the sensing line 104.” – note first power line 101 is the claimed voltage wire and the widthwise wiring is not merely an edge node - it is interior distributed power wiring feeding the horizontal pixel line which wiring represents a distributed (i.e., central/intermediate) portion of the voltage wire network supplying the display panel. Therefore, sensing from such widthwise wiring constitutes sensing from a “central portion” of the voltage wire; and [0107] “the sensing line 104 is provided in the outer area (or non-display area) of the screen (or display area) AA”; [0152] “the sensing line may be provided in an outer area of a display area on the display panel” – note the sensing structure and connection are formed in a non-active area on the side of the display panel. Because the sensing line connects directly to the widthwise wiring of the first power line 101, the voltage wire extends into and is accessible within the non-active outer area);
a gain compensator configured to amplify the generated pixel driving voltage drop amount using a predetermined gain value (see at least [0119] “the first differential amplifier amplifies a difference … at an R2/R1 ratio”; [0121] “by adjusting a ratio of the resistors R1 and R2 … by allowing R2/R1 to be greater than one”; [0158] “the amplification ratio … may be equal to or greater than one” – note the first differential amplifier corresponds to the claimed gain compensator and R2/R1 ratio is a gain ratio); and
a voltage compensator configured to generate a compensation voltage value for compensating a gamma reference voltage for a corresponding pixel using the amplified pixel driving voltage drop amount (see at least “second and third differential amplifiers … generate the high potential gamma input voltage Vgma_h and the low potential gamma input voltage Vgma_l on the basis of the drop amount of the pixel driving voltage”; [0123] “Vgma_h = Vgma_h0 + R2/R1*(Vdd_s − Vdd_r)”; [0125] “Vgma_l = Vgma_l0 + R2/R1*(Vdd_s − Vdd_r)”; [0128] “The gamma compensation voltage … has a range determined by the high potential/low potential gamma input voltage Vgma_h/Vgma_l”);
wherein the voltage wire is formed in a non-active area on the side of the display panel (see [0107] “the sensing line 104 is provided in the outer area (or non-display area) of the screen (or display area) AA”; [0152] “the sensing line may be provided in an outer area of a display area on the display panel” – note the sensing structure and connection are formed in a non-active area on the side of the display panel. Because the sensing line connects directly to the widthwise wiring of the first power line 101, the voltage wire extends into and is accessible within the non-active outer area).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Lee ’150’s differential amplification and gamma reference voltage compensation techniques into the compensation circuit of Lee ’542 because both references address the same problem of luminance and grayscale non-uniformity caused by pixel driving voltage drop across a display panel. Lee ’150 applies a known voltage-drop amplification and compensation technique at the gamma generation stage. Integrating this known technique into Lee ’542’s voltage-drop feedback architecture would have constituted a predictable use of prior art elements according to their established functions to further improve display uniformity and grayscale accuracy. The modification would have been well within ordinary design skill and would have yielded no unexpected result.
As to claim 2, the combination of Lee’542 and Lee ‘150 teach the compensation circuit of claim 1 (see above rejection), wherein the voltage calculator is arranged side by side with a longer side of the display panel, and is configured to receive the pixel driving voltage fed back from the central portion of the display panel corresponding to a central portion of a voltage wire which applies the pixel driving voltage to each pixel line in the display panel (see Lee ’542: Fig. 9 shows FEEDBACK UNIT returning V_FEED from the center region of the panel – note physical placement along the longer side of the display panel is not explicitly taught but would have been an obvious design choice to efficiently route the feedback signal).
As to claim 3, the combination of Lee’542 and Lee ‘150 teach the compensation circuit of claim 1 (see above rejection), wherein the voltage compensator is configured to generate the compensation voltage value for compensating for the gamma reference voltage using the amplified pixel driving voltage drop amount and a gamma reference voltage (see Lee ‘150 at least [0116]–[0117], [0123]–[0125], [0128]–[0130], [0141]–[0142]: adjusts Vgma_h/Vgma_l based on pixel voltage drop).
As to claim 4, the combination of Lee’542 and Lee ‘150 teach the compensation circuit of claim 1 (see above rejection), wherein the predetermined gain value is applied from a timing controller or a host system (see Lee ‘542 at least figs. 1, 9, [0070] "Compared with a feedback unit 170a in FIG. 7, the feedback unit 170b in FIG. 8 may further include a unit gain buffer UGB coupled between the output power supply line and a third resistor R3. The unit gain buffer UGB may allow the display panel not to be electrically affected by the feedback unit 170b. For example, the unit gain buffer UGB may include an operational amplifier OP having an inverted input terminal coupled to an output terminal of the operational amplifier OP."; and see Lee ‘150 at least fig. 1, [0119] “the first differential amplifier amplifies a difference (a voltage drop amount of pixel driving voltage) between the pixel driving voltage reference value Vdd_r and the pixel driving voltage measurement value Vdd_s at an R2/R1 ratio”; [0121] “by adjusting a ratio of the resistors R1 and R2 in the first differential amplifier, for example, by allowing R2/R1 to be greater than one”).
As to claim 5, the combination of Lee’542 and Lee ‘150 teach the compensation circuit of claim 1 (see above rejection), wherein the predetermined gain value is varied depending on a gray level value or a display brightness value (DBV) of the corresponding pixel (see Lee ‘150 at least [0116] “The gamma reference voltage adjusting unit 161 compares the pixel driving voltage measurement value Vdd_s fed back from each position of the display panel 10 with a pixel driving voltage reference value Vdd_r generated by the power supply unit 16 and supplied to the display panel 10, thereby adjusting the low potential gamma input voltage Vgma_l and the high potential gamma input voltage Vgma_h.”; [0117] “Referring to FIG. 10, the gamma reference voltage adjusting unit 161 may include a first differential amplifier that compares the pixel driving voltage reference value Vdd_r with the pixel driving voltage measurement value Vdd_s to amplify and output a difference value therebetween (a drop amount of the pixel driving voltage), and second and third differential amplifiers that generate the high potential gamma input voltage Vgma_h and the low potential gamma input voltage Vgma_l on the basis of the drop amount of the pixel driving voltage, respectively.” [0121] “adjusting a ratio of the resistors R1 and R2” – note the concept of varying gain according to gray level is a predictable design choice to optimize display performance).
As to claim 9, Lee ‘542 teaches a display device comprising:
a display panel including data lines, gate lines, and pixels applied with pixel driving voltages (see at least figs. 1-2: display panel 110, pixels PX, SSCAN, SDATA);
a data driver configured to supply pixel data to the data lines (see at least figs. 1-2: SDATA);
a power supply configured to apply the pixel driving voltage to the pixels (see at least fig. 1: power supply device 150); and
a compensation circuit configured to:
generate a pixel driving voltage drop amount using a pixel driving voltage applied from the power supply and a pixel driving voltage fed back from a central portion of the display panel (see at least fig. 1: shows FEEDBACK UNIT returning VFEED from the panel back to the power supply device; fig. 9: designates “CENTER” and shows the output power supply line coupled back toward the center region, flow of ELVDD_IN/ELVDD_OUT around CENTER; [0008] “the power supply may adjust the voltage level of the power supply voltage applied to the input power supply line to compensate temporal variation of the power supply voltage.”);
amplify the generated pixel driving voltage drop amount using a predetermined gain value (see at least [0070] "Compared with a feedback unit 170a in FIG. 7, the feedback unit 170b in FIG. 8 may further include a unit gain buffer UGB coupled between the output power supply line and a third resistor R3. The unit gain buffer UGB may allow the display panel not to be electrically affected by the feedback unit 170b. For example, the unit gain buffer UGB may include an operational amplifier OP having an inverted input terminal coupled to an output terminal of the operational amplifier OP." - note Lee 542 illustrates unity gain, therefore the use of an amplifier with a fixed design-defined gain inherently corresponds to a predetermined gain);
generate a compensation voltage value for a corresponding pixel using the amplified pixel driving voltage drop amount (see at least [0055] "For example, in a case where a display panel 110a displays a box pattern 140a having a predetermined grayscale value as illustrated in FIG. 6A, the amount of voltage drop of a power supply voltage ELVDD may vary over time within one frame 200a or within one sub-frame SF2 as illustrated in FIG. 6B. Thus, the dropped power supply voltage ELVDD_OUT may vary over time."; [0061] "For example, as illustrated in FIG. 6C, the power supply device 150 may increase the power supply voltage ELVDD_IN applied to the display panel 110 during the first time period T1, during which the power supply voltage ELVDD_OUT received from the output power supply line 130 decreases. Further, the power supply device 150 may decrease the power supply voltage ELVDD_IN applied to the display panel 110 during the third time period T3, during which the power supply voltage ELVDD_OUT received from the output power supply line 130 increases. Accordingly, an effective voltage drop at each time period T1, T2, and T3 may be reduced. As a result, the pixels PX at different rows may have substantially the same or similar luminances, even if the respective pixels PX emit light at different time periods T1, T2, and T3. e.g., where the respective pixels PX emit light with the same emission duty cycle to produce the same grayscale value." - note the power supply device increases/decreases ELVDD_IN to reduce voltage drop variations over time and achieve uniform luminance).
Lee ‘542 does not directly teach compensating a gamma reference voltage, nor does it directly teach amplification at other predetermined gain values beyond unity, and wherein a voltage wire is formed in a non-active area on the side of the display panel.
Lee ‘150 teaches a compensation circuit configured to: generate a pixel driving voltage drop amount using a pixel driving voltage applied from the power supply and a pixel driving voltage fed back directly from a central portion of a voltage wire formed in a side of the display panel (see at least [0116] “The gamma reference voltage adjusting unit 161 compares the pixel driving voltage measurement value Vdd_s fed back … with a pixel driving voltage reference value Vdd_r generated by the power supply unit 16 …”; [0117] “a first differential amplifier … to amplify and output a difference value therebetween (a drop amount of the pixel driving voltage)”; [0119] “Vo = R2/R1*(Vdd_r − Vdd_s)” – note generation of a pixel driving voltage drop amount is Vdd_r − Vdd_s, pixel driving voltage applied is Vdd_r, a fed-back pixel driving voltage is Vdd_s and [0106] “the first power line 101 supplying the pixel driving voltage Vdd to the pixel is connected in a mesh form, and a widthwise wiring … is arranged for each horizontal line”; [0107] “the sensing line 104 may be connected to the widthwise wiring of the first power line 101 through a sensing switch transistor T101 controlled by using the scan signal”; [0108] “the widthwise wiring of the first power line 101 disposed on the corresponding horizontal line is connected to the sensing line 104, and the actual value Vdd_s … is supplied to the power supply unit 16 via the sensing line 104.” – note first power line 101 is the claimed voltage wire and the widthwise wiring is not merely an edge node - it is interior distributed power wiring feeding the horizontal pixel line which wiring represents a distributed (i.e., central/intermediate) portion of the voltage wire network supplying the display panel. Therefore, sensing from such widthwise wiring constitutes sensing from a “central portion” of the voltage wire; and [0107] “the sensing line 104 is provided in the outer area (or non-display area) of the screen (or display area) AA”; [0152] “the sensing line may be provided in an outer area of a display area on the display panel” – note the sensing structure and connection are formed in a non-active area on the side of the display panel. Because the sensing line connects directly to the widthwise wiring of the first power line 101, the voltage wire extends into and is accessible within the non-active outer area),
amplify the generated pixel driving voltage drop amount using a predetermined gain value (see at least [0119] “the first differential amplifier amplifies a difference … at an R2/R1 ratio”; [0121] “by adjusting a ratio of the resistors R1 and R2 … by allowing R2/R1 to be greater than one”; [0158] “the amplification ratio … may be equal to or greater than one”), and
generate a compensation voltage value for compensating a gamma reference voltage for a corresponding pixel using the amplified pixel driving voltage drop amount (see at least “second and third differential amplifiers … generate the high potential gamma input voltage Vgma_h and the low potential gamma input voltage Vgma_l on the basis of the drop amount of the pixel driving voltage”; [0123] “Vgma_h = Vgma_h0 + R2/R1*(Vdd_s − Vdd_r)”; [0125] “Vgma_l = Vgma_l0 + R2/R1*(Vdd_s − Vdd_r)”; [0128] “The gamma compensation voltage … has a range determined by the high potential/low potential gamma input voltage Vgma_h/Vgma_l”);
wherein the voltage wire is formed in a non-active area on the side of the display panel (see [0107] “the sensing line 104 is provided in the outer area (or non-display area) of the screen (or display area) AA”; [0152] “the sensing line may be provided in an outer area of a display area on the display panel” – note the sensing structure and connection are formed in a non-active area on the side of the display panel. Because the sensing line connects directly to the widthwise wiring of the first power line 101, the voltage wire extends into and is accessible within the non-active outer area).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Lee ’150’s differential amplification and gamma reference voltage compensation techniques into the compensation circuit of Lee ’542 because both references address the same problem of luminance and grayscale non-uniformity caused by pixel driving voltage drop across a display panel. Lee ’150 applies a known voltage-drop amplification and compensation technique at the gamma generation stage. Integrating this known technique into Lee ’542’s voltage-drop feedback architecture would have constituted a predictable use of prior art elements according to their established functions to further improve display uniformity and grayscale accuracy. The modification would have been well within ordinary design skill and would have yielded no unexpected result.
As to claim 11, the combination of Lee’542 and Lee ‘150 teach the display device of claim 9 (see above rejection), further comprising: a first voltage wire arranged side by side with a longer side of the display panel , and a second voltage wire branched for each pixel line from the first voltage wire, wherein the compensation circuit receives the pixel driving voltage fed back from the central portion of the display panel corresponding a central portion of the first voltage wire (see Lee ’542: Fig. 9 shows FEEDBACK UNIT returning V_FEED from the center region of the panel – note physical placement along the longer side of the display panel is not explicitly taught but would have been an obvious design choice to efficiently route the feedback signal).
As to claim 12, the combination of Lee’542 and Lee ‘150 teach the display device of claim 9 (see above rejection), wherein the compensation circuit includes: a voltage calculator configured to generate the pixel driving voltage drop amount using the pixel driving voltage applied from the power supply and the pixel driving voltage fed back from the central portion of the display panel (see Lee ‘542 at least fig. 1: shows FEEDBACK UNIT returning VFEED from the panel back to the power supply device; fig. 9: designates “CENTER” and shows the output power supply line coupled back toward the center region, flow of ELVDD_IN/ELVDD_OUT around CENTER; [0008] “the power supply may adjust the voltage level of the power supply voltage applied to the input power supply line to compensate temporal variation of the power supply voltage.”); and a voltage compensator configured to generate the compensation voltage value for compensating the gamma reference voltage for the corresponding pixel using the amplified pixel driving voltage drop amount (see Lee ‘542 at least [0055] "For example, in a case where a display panel 110a displays a box pattern 140a having a predetermined grayscale value as illustrated in FIG. 6A, the amount of voltage drop of a power supply voltage ELVDD may vary over time within one frame 200a or within one sub-frame SF2 as illustrated in FIG. 6B. Thus, the dropped power supply voltage ELVDD_OUT may vary over time."; [0061] "For example, as illustrated in FIG. 6C, the power supply device 150 may increase the power supply voltage ELVDD_IN applied to the display panel 110 during the first time period T1, during which the power supply voltage ELVDD_OUT received from the output power supply line 130 decreases. Further, the power supply device 150 may decrease the power supply voltage ELVDD_IN applied to the display panel 110 during the third time period T3, during which the power supply voltage ELVDD_OUT received from the output power supply line 130 increases. Accordingly, an effective voltage drop at each time period T1, T2, and T3 may be reduced. As a result, the pixels PX at different rows may have substantially the same or similar luminances, even if the respective pixels PX emit light at different time periods T1, T2, and T3. e.g., where the respective pixels PX emit light with the same emission duty cycle to produce the same grayscale value." - note the power supply device increases/decreases ELVDD_IN to reduce voltage drop variations over time and achieve uniform luminance; and Lee ‘150 at least [0116] “The gamma reference voltage adjusting unit 161 compares the pixel driving voltage measurement value Vdd_s fed back from each position of the display panel 10 with a pixel driving voltage reference value Vdd_r generated by the power supply unit 16 and supplied to the display panel 10, thereby adjusting the low potential gamma input voltage Vgma_l and the high potential gamma input voltage Vgma_h.”; [0117] “Referring to FIG. 10, the gamma reference voltage adjusting unit 161 may include a first differential amplifier that compares the pixel driving voltage reference value Vdd_r with the pixel driving voltage measurement value Vdd_s to amplify and output a difference value therebetween (a drop amount of the pixel driving voltage), and second and third differential amplifiers that generate the high potential gamma input voltage Vgma_h and the low potential gamma input voltage Vgma_l on the basis of the drop amount of the pixel driving voltage, respectively.”; [0119] “the first differential amplifier amplifies a difference (a voltage drop amount of pixel driving voltage) between the pixel driving voltage reference value Vdd_r and the pixel driving voltage measurement value Vdd_s at an R2/R1 ratio”; [0121] “by adjusting a ratio of the resistors R1 and R2 in the first differential amplifier, for example, by allowing R2/R1 to be greater than one, it is also possible to compensate for the time difference between the sensing of the pixel driving voltage and the adjustment of the data voltage.” [0123]–[0125], [0128]–[0130], [0141]–[0142]).
As to claim 13, the combination of Lee’542 and Lee ‘150 teach the display device of claim 12 (see above rejection), wherein the compensation circuit further includes: a gain compensator configured to amplify the generated pixel driving voltage drop amount using the predetermined gain value (see Lee ‘150 at least [0116]–[0117], [0123]–[0125], [0128]–[0130], [0141]–[0142]: adjusts Vgma_h/Vgma_l based on pixel voltage drop).
As to claim 14, the combination of Lee’542 and Lee ‘150 teach the display device of claim 9 (see above rejection), wherein the predetermined gain value is applied from a timing controller or a host system (see Lee ‘542 at least figs. 1, 9, [0070] "Compared with a feedback unit 170a in FIG. 7, the feedback unit 170b in FIG. 8 may further include a unit gain buffer UGB coupled between the output power supply line and a third resistor R3. The unit gain buffer UGB may allow the display panel not to be electrically affected by the feedback unit 170b. For example, the unit gain buffer UGB may include an operational amplifier OP having an inverted input terminal coupled to an output terminal of the operational amplifier OP."; and see Lee ‘150 at least fig. 1, [0119] “the first differential amplifier amplifies a difference (a voltage drop amount of pixel driving voltage) between the pixel driving voltage reference value Vdd_r and the pixel driving voltage measurement value Vdd_s at an R2/R1 ratio”; [0121] “by adjusting a ratio of the resistors R1 and R2 in the first differential amplifier, for example, by allowing R2/R1 to be greater than one”).
As to claim 15, the combination of Lee’542 and Lee ‘150 teach the display device of claim 9 (see above rejection), wherein the predetermined gain value varies depending on a grayscale value or a display brightness value (DBV) of the corresponding pixel (see Lee ‘150 at least [0116] “The gamma reference voltage adjusting unit 161 compares the pixel driving voltage measurement value Vdd_s fed back from each position of the display panel 10 with a pixel driving voltage reference value Vdd_r generated by the power supply unit 16 and supplied to the display panel 10, thereby adjusting the low potential gamma input voltage Vgma_l and the high potential gamma input voltage Vgma_h.”; [0117] “Referring to FIG. 10, the gamma reference voltage adjusting unit 161 may include a first differential amplifier that compares the pixel driving voltage reference value Vdd_r with the pixel driving voltage measurement value Vdd_s to amplify and output a difference value therebetween (a drop amount of the pixel driving voltage), and second and third differential amplifiers that generate the high potential gamma input voltage Vgma_h and the low potential gamma input voltage Vgma_l on the basis of the drop amount of the pixel driving voltage, respectively.” [0121] “adjusting a ratio of the resistors R1 and R2” – note the concept of varying gain according to gray level is a predictable design choice to optimize display performance).
As to claim 19, the combination of Lee’542 and Lee ‘150 teach the display device of claim 9 (see above rejection), further comprising: a gamma voltage generator configured to adjust the gamma reference voltage using the amplified pixel driving voltage drop amount and generate a gamma voltage for each gray level using the adjusted gamma reference voltage (see Lee ‘150 at least [0116]-[0130], [0141]-[0142] discloses: adjustment of Vgma_h/Vgma_l based on pixel voltage drop and generation of gamma compensation voltage per gray level).
As to claim 20, the combination of Lee’542 and Lee ‘150 teach the display device of claim 19 (see above rejection), wherein the gamma voltage generator includes a gamma reference voltage regulator and a gamma compensation voltage generator, wherein the gamma reference voltage regulator uses the amplified pixel driving voltage drop amount to adjust the gamma reference voltage including a high potential gamma reference voltage and a low potential gamma reference voltage, and wherein the gamma compensation voltage generator generates a gamma compensation voltage for each gray level using the adjusted high potential gamma reference voltage and low potential gamma reference voltage (see Lee ‘150 at least [0116]-[0130], [0141]-[0142] discloses: adjustment of Vgma_h/Vgma_l based on pixel voltage drop and generation of gamma compensation voltage per gray level).
Claims 6-8 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (USPN 2016/0086542 A1, hereinafter Lee ‘542) in view of Lee et al. (USPN 2021/0043150 A1, hereinafter Lee ‘150), further in view of Park et al. (USPN 2022/0208043 A1).
As to claim 6, the combination of Lee’542 and Lee ‘150 teach the compensation circuit of claim 1 (see above rejection).
Lee ‘542 and Lee ‘150 do not directly teach wherein the gain compensator includes a digital analog converter (DAC) module, and wherein the DAC module includes: a first input terminal configured to receive the pixel driving voltage drop amount; a second input terminal configured to receive the predetermined gain value; and a first output terminal configured to amplify the pixel driving voltage drop amount received from the first input terminal using the predetermined gain value received from the second input terminal and to output the amplified pixel driving voltage drop amount.
Park teaches wherein the gain compensator includes a digital analog converter (DAC) module, and wherein the DAC module includes: a first input terminal configured to receive the pixel driving voltage drop amount; a second input terminal configured to receive the predetermined gain value; and a first output terminal configured to amplify the pixel driving voltage drop amount received from the first input terminal using the predetermined gain value received from the second input terminal and to output the amplified pixel driving voltage drop amount (see at least figs. 12, 14, 16, 18: DAC, [0088]: “The power source PS includes an error amplifier EAMP which amplifies a difference between the virtual feedback voltage … and a reference voltage VREF.”; [0183]; [0198]; [0201]: “The power multiplier PMU multiplies a current value … and the resistance … By doing this, the power multiplier PMU can calculate the voltage drop amount …”; [0202]: “The reference voltage source RS can adjust a magnitude of the reference voltage VREF based on the output of the power multiplier PMU.”; [0206]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Park’s DAC, offset generation and error-amplifier compensation techniques into the combined circuit of Lee ’542 and Lee ’150 in order to improve the accuracy of voltage drop compensation. Both Lee ’542 and Lee ’150 already teach feedback-based compensation for voltage drop and gamma reference errors, and Park addresses the same problem—compensating for voltage drop to maintain uniform luminance—by refining the compensation signal with offset correction and error removal. A skilled artisan would have recognized that integrating Park’s teachings would have predictably enhanced the precision of the combined compensation circuit by correcting zero-gain errors and baseline offsets, thereby yielding improved grayscale accuracy and uniformity. The combination would have yielded predictable results to one of ordinary skill in the art.
As to claim 7, the combination of Lee’542, Lee ‘150 and Park teach the compensation circuit of claim 6 (see above rejection), wherein the DAC module further comprises: a second output terminal configured to output an offset value for a value output from the first output terminal when a value input to the first input terminal is 0 (see Park at least [0200] “In the power look-up table PLUT, a resistance between the output terminal of the power source PS and the display panel DP can be stored.” – note even if the sensed current = 0 (analogous to first input = 0), there remains a stored resistance/output adjustment that effectively represents an offset value; [0202] “The reference voltage source RS can adjust … based on the output of the power multiplier PMU. … when the output … is decreased, the magnitude of the reference voltage VREF is decreased so that the output of the error amplifier EAMP can be decreased.” – note this implies that a baseline or offset adjustment exists, even at low/zero input.; [0206]; note while not literally naming “offset value,” the disclosure supports outputting a correction (offset) when input is at baseline, due to the stored resistance and calibration values in PLUT).
As to claim 8, the combination of Lee’542, Lee ‘150 and Park teach the compensation circuit of claim 7 (see above rejection), further comprising: an error compensator configured to receive the amplified pixel driving voltage drop amount and the offset value and to generate a voltage drop amount in which a zero gain error is removed, wherein the voltage compensator generates the compensation voltage value for compensating the gamma reference voltage using the voltage drop amount in which a zero gain error is removed and generated from the error compensator (see at least figs. 12, 14, 16, 18: EAMP + RS functioning as the error compensator and CTR generating the corrected compensation voltage; [0183], [0196]-[0202]; [0206]: “The magnitude of the reference voltage VREF of the error amplifier EAMP is adjusted based on the voltage drop amount. By doing this, the high potential power voltage VDDEL is increased by the voltage drop amount … to compensate for additional voltage drop.”; [0257]-[0259]: “The power source can include an error amplifier which amplifies a difference between the virtual feedback voltage and a reference voltage.”).
As to claim 16, the combination of Lee’542 and Lee ‘150 teach the display device of claim 13 (see above rejection).
Lee ‘542 and Lee ‘150 do not directly teach wherein the gain compensator includes a digital analog converter (DAC) module, and wherein the DAC module includes: a first input terminal configured to receive the pixel driving voltage drop amount; a second input terminal configured to receive the predetermined gain value; and a first output terminal configured to amplify the pixel driving voltage drop amount received from the first input terminal using the predetermined gain value received from the second input terminal and to output the amplified pixel driving voltage drop amount.
Park teaches wherein the gain compensator includes a digital analog converter (DAC) module, and wherein the DAC module includes: a first input terminal configured to receive the pixel driving voltage drop amount; a second input terminal configured to receive the predetermined gain value; and a first output terminal configured to amplify the pixel driving voltage drop amount received from the first input terminal using the predetermined gain value received from the second input terminal and to output the amplified pixel driving voltage drop amount (see at least figs. 12, 14, 16, 18: DAC, [0088]: “The power source PS includes an error amplifier EAMP which amplifies a difference between the virtual feedback voltage … and a reference voltage VREF.”; [0183]; [0198]; [0201]: “The power multiplier PMU multiplies a current value … and the resistance … By doing this, the power multiplier PMU can calculate the voltage drop amount …”; [0202]: “The reference voltage source RS can adjust a magnitude of the reference voltage VREF based on the output of the power multiplier PMU.”; [0206]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Park’s DAC, offset generation and error-amplifier compensation techniques into the combined circuit of Lee ’542 and Lee ’150 in order to improve the accuracy of voltage drop compensation. Both Lee ’542 and Lee ’150 already teach feedback-based compensation for voltage drop and gamma reference errors, and Park addresses the same problem—compensating for voltage drop to maintain uniform luminance—by refining the compensation signal with offset correction and error removal. A skilled artisan would have recognized that integrating Park’s teachings would have predictably enhanced the precision of the combined compensation circuit by correcting zero-gain errors and baseline offsets, thereby yielding improved grayscale accuracy and uniformity. The combination would have yielded predictable results to one of ordinary skill in the art.
As to claim 17, the combination of Lee’542, Lee ‘150 and Park teach the display device of claim 16 (see above rejection), wherein the DAC module further comprises: a second output terminal configured to output an offset value for a value output from the first output terminal when a value input to the first input terminal is 0 (see Park at least [0200] “In the power look-up table PLUT, a resistance between the output terminal of the power source PS and the display panel DP can be stored.” – note even if the sensed current = 0 (analogous to first input = 0), there remains a stored resistance/output adjustment that effectively represents an offset value; [0202] “The reference voltage source RS can adjust … based on the output of the power multiplier PMU. … when the output … is decreased, the magnitude of the reference voltage VREF is decreased so that the output of the error amplifier EAMP can be decreased.” – note this implies that a baseline or offset adjustment exists, even at low/zero input.; [0206]; note while not literally naming “offset value,” the disclosure supports outputting a correction (offset) when input is at baseline, due to the stored resistance and calibration values in PLUT).
As to claim 18, the combination of Lee’542, Lee ‘150 and Park teach the display device of claim 17 (see above rejection), wherein the compensation circuit further includes: an error compensator configured to receive the amplified pixel driving voltage drop amount and the offset value to generate a voltage drop amount in which a zero gain error is removed, and wherein the voltage compensator generates the compensation voltage value for compensating the gamma reference voltage using the amplified pixel driving voltage drop amount in which a zero gain error is removed and generated from the error compensator (see at least figs. 12, 14, 16, 18: EAMP + RS functioning as the error compensator and CTR generating the corrected compensation voltage; [0183], [0196]-[0202]; [0206]: “The magnitude of the reference voltage VREF of the error amplifier EAMP is adjusted based on the voltage drop amount. By doing this, the high potential power voltage VDDEL is increased by the voltage drop amount … to compensate for additional voltage drop.”; [0257]-[0259]: “The power source can include an error amplifier which amplifies a difference between the virtual feedback voltage and a reference voltage.”).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (USPN 2016/0086542 A1, hereinafter Lee ‘542) in view of Lee et al. (USPN 2021/0043150 A1, hereinafter Lee ‘150), further in view of Kim et al. (USPN 2022/0084479 A1).
As to claim 10, the combination of Lee’542 and Lee ‘150 teach the display device of claim 9 (see above rejection).
Lee’542 and Lee ‘150 do not directly teach wherein the data driver includes a first data driver disposed at an upper end of the display panel and a second data driver disposed at a lower end of the display panel, wherein a pair of data lines is connected to the first data driver and the second data driver for each column line, wherein an odd-numbered data line is connected to pixels arranged on an odd-numbered pixel line, and wherein an even-numbered data line is connected to pixels arranged on an even-numbered pixel line.
Kim teaches wherein the data driver includes a first data driver disposed at an upper end of the display panel and a second data driver disposed at a lower end of the display panel, wherein a pair of data lines is connected to the first data driver and the second data driver for each column line, wherein an odd-numbered data line is connected to pixels arranged on an odd-numbered pixel line, and wherein an even-numbered data line is connected to pixels arranged on an even-numbered pixel line (see at least fig. 4 and [0098] “A first data driver DIC1 and a second data driver DIC2 may be disposed on the first circuit board FLM1. That is, the first and second data drivers DIC1 and DIC2 may be disposed outside the display panel DP.” – note first data driver DIC1 and second data driver DIC2 are disposed at opposite ends and can be upper/lower depending on viewing direction, also note even data line DL20 connected to first data driver DIC1 and odd data line DL21 connected to second data driver DIC2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further incorporate the dual-end data driver architecture of Kim into the display device of Lee ’542 as modified by Lee ’150. Lee ’542 and Lee ’150 already teach a display device including a display panel, data drivers, and compensation circuitry for ensuring uniform luminance across the panel. Kim teaches that providing first and second data drivers disposed at opposite ends of the display panel, with data lines coupled to both drivers, reduces signal delay, improves uniformity of data voltage distribution, and alleviates loading effects in high-resolution, large-area displays (see Kim fig. 4 and description). A person of ordinary skill in the art would have recognized that combining Kim’s dual-driver arrangement with the compensation circuitry of Lee ’542/Lee ’150 would have yielded predictable benefits by ensuring that the improved voltage compensation techniques are applied in a panel structure that also minimizes data line resistance and signal degradation. Thus, the combination would have been obvious because it represents the use of a known driver placement technique (as taught by Kim) in the context of known compensation circuitry (as taught by Lee ’542/Lee ’150) to achieve the well-understood goal of improved display uniformity and stable grayscale performance.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (USPN 2016/0086542 A1, hereinafter Lee ‘542) in view of Lee et al. (USPN 2021/0043150 A1, hereinafter Lee ‘150), further in view of Hong (USPN 2014/0339508 A1).
As to claim 21, the combination of Lee ‘542 and Lee ‘150 teach the display device of claim 9 (see above rejection).
Lee ‘542 and Lee ‘150 do not directly teach wherein the voltage wire formed in the non- active area is formed with a wider width than voltage wires formed in an active area of the display panel.
Hong teaches wherein the voltage wire formed in the non-active area is formed with a wider width than voltage wires formed in an active area of the display panel (see at least [0039] “The switching elements (SW1, SW2) may be disposed in a non-display area NDA which surrounds the display area DA”; [0043] “The power bus lines (CB1, CB2) may receive the first power supply voltage ELVSS from a driving unit 10 which will be described later. The power bus lines (CB1, CB2) may be relatively wider than other wiring lines in order to effectively prevent a voltage drop. The power bus lines (CB1, CB2) may include a first power bus line CB1 and a second power bus line CB2. The first power bus line CB1 may be disposed outside and adjacent to the first side of the display area DA, and the second power bus line CB2 may be disposed outside and adjacent to the second side of the display area DA.”).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date, to form the non-active-area voltage wire of Lee ’542/Lee ’150 with a wider width than voltage wiring in the display area, as taught by Hong, in order to reduce resistive voltage drop. Increasing conductor width to reduce resistance and IR drop is a well-understood and predictable electrical design principle. Applying Hong’s known structural technique to the non-active-area voltage wire of Lee ’542/Lee ’150 would have predictably improved voltage uniformity, consistent with the shared objective of reducing voltage drop across the display panel.
Response to Arguments
Applicant's arguments filed 12/11/2025 have been fully considered but they are not persuasive.
Applicant's argues –
“Regarding claims 1 and 9 as previously presented, the Office Action alleges that Lee' 542 and Lee '150 teach all of the claimed features.
In contrast to amended claims 1 and 9, Lee'542 and Lee'150 do not teach or suggest all of the claimed features including, inter alia, "...a pixel driving voltage fed back directly from a central portion of a voltage wire formed in a side of a display panel, ... wherein the voltage wire is formed in a non-active area on the side of the display panel" (emphasis added).
For example, with reference to Applicant's FIG. 7, when the display panel has a longer length in the second axis direction than the length in the first axis direction, the voltage drop of the pixel driving voltage is much larger, and thus a voltage wire VL for applying the pixel driving voltage can be formed side by side in the second axis direction of the display panel.
For instance, in an embodied invention of the present application, the voltage wire (e.g., VL) is directly formed in a side bezel area of the display panel.
Further in this example of the present application, the voltage wire (e.g., VL) can include a first voltage wire (e.g., VL1 and a second voltage wire (e.g., VL2). In particular, the first voltage wire (e.g., VL1) can be formed side by side with the display panel along the second axis direction of the display panel, and the second voltage wire (e.g., VL2) can be branched from the first voltage wire (e.g., VL1) and formed side by side with the display panel along the first axis direction.
However, in contrast to the embodied invention, Lee' 542 does not teach or suggest the specific features recited in amended claims 1 and 9. That is, as shown in Figure 9 of Lee'542 (reproduced below), Lee' 542 only discloses that the power supply voltage ELVDD_IN is supplied at both edge portions TOP and BOTTOM of the display panel 110, and dropped power supply voltages ELVDD_OUT1 and ELVDD_OUT2 are output at the both edge portions TOP and BOTTOM of the display panel 110.
Also, the term 'CENTER' shown in Fig. 9 merely indicates the center of the panel and does not describe any explanation related to the location where the power supply voltage is fed back.
Lee' 150 does not cure the deficiencies of Lee' 542.
Thus, Lee'542 and Lee' 150 do not teach or suggest all of the specific features and specific spatial relationships as recited in amended claims 1 and 9.
Park and Kim fail to cure the deficiencies of Lee' 542 and Lee'150.
The various dependent claims are allowable at least based on their dependency from claim 1 or 9, and/or further in view of their own respective features.
Accordingly, reconsideration and withdrawal of the rejections are respectfully requested, and Applicant respectfully submits that the application should be in condition for allowance.
Claim 21 has been added for the Examiner's consideration. Claim 21 is allowable at least based on its dependency from claim 1, and/or further in view of its own respective features. Thus, consideration and allowance of claim 21 are respectfully requested.”
Examiner disagrees –
Regarding claims 1 and 9:
Lee ‘542 teaches a voltage calculator configured to generate a pixel driving voltage drop amount using a pixel driving voltage applied from a power supply and a pixel driving voltage fed back from a central portion of a display panel (see at least fig. 1: shows FEEDBACK UNIT returning VFEED from the panel back to the power supply device; fig. 9: designates “CENTER” and shows the output power supply line coupled back toward the center region, flow of ELVDD_IN/ELVDD_OUT around CENTER; [0008] “the power supply may adjust the voltage level of the power supply voltage applied to the input power supply line to compensate temporal variation of the power supply voltage.”; [0040] “The output power supply line 130 may be coupled … at a predetermined location (e.g., center portion) CENTER of the display panel”; [0043] “each of the input power supply line 120 and output power supply line 130 may have a mesh structure” – note the power supply line includes central and distributed portions across the panel and is not limited to edge nodes);
Lee ‘150 teaches a voltage calculator configured to generate a pixel driving voltage drop amount using a pixel driving voltage applied from a power supply and a pixel driving voltage fed back directly from a central portion of a voltage wire formed in a side of a display panel; (see at least [0116] “The gamma reference voltage adjusting unit 161 compares the pixel driving voltage measurement value Vdd_s fed back … with a pixel driving voltage reference value Vdd_r generated by the power supply unit 16 …”; [0117] “a first differential amplifier … to amplify and output a difference value therebetween (a drop amount of the pixel driving voltage)”; [0119] “Vo = R2/R1*(Vdd_r − Vdd_s)” – note the first differential amplifier is the claimed voltage calculator, generation of a pixel driving voltage drop amount is Vdd_r − Vdd_s, pixel driving voltage applied is Vdd_r, a fed-back pixel driving voltage is Vdd_s and [0106] “the first power line 101 supplying the pixel driving voltage Vdd to the pixel is connected in a mesh form, and a widthwise wiring … is arranged for each horizontal line”; [0107] “the sensing line 104 may be connected to the widthwise wiring of the first power line 101 through a sensing switch transistor T101 controlled by using the scan signal”; [0108] “the widthwise wiring of the first power line 101 disposed on the corresponding horizontal line is connected to the sensing line 104, and the actual value Vdd_s … is supplied to the power supply unit 16 via the sensing line 104.” – note first power line 101 is the claimed voltage wire and the widthwise wiring is not merely an edge node - it is interior distributed power wiring feeding the horizontal pixel line which wiring represents a distributed (i.e., central/intermediate) portion of the voltage wire network supplying the display panel. Therefore, sensing from such widthwise wiring constitutes sensing from a “central portion” of the voltage wire; and [0107] “the sensing line 104 is provided in the outer area (or non-display area) of the screen (or display area) AA”; [0152] “the sensing line may be provided in an outer area of a display area on the display panel” – note the sensing structure and connection are formed in a non-active area on the side of the display panel. Because the sensing line connects directly to the widthwise wiring of the first power line 101, the voltage wire extends into and is accessible within the non-active outer area);
wherein the voltage wire is formed in a non-active area on the side of the display panel (see [0107] “the sensing line 104 is provided in the outer area (or non-display area) of the screen (or display area) AA”; [0152] “the sensing line may be provided in an outer area of a display area on the display panel” – note the sensing structure and connection are formed in a non-active area on the side of the display panel. Because the sensing line connects directly to the widthwise wiring of the first power line 101, the voltage wire extends into and is accessible within the non-active outer area).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Lee ’150’s differential amplification and gamma reference voltage compensation techniques into the compensation circuit of Lee ’542 because both references address the same problem of luminance and grayscale non-uniformity caused by pixel driving voltage drop across a display panel. Lee ’150 applies a known voltage-drop amplification and compensation technique at the gamma generation stage. Integrating this known technique into Lee ’542’s voltage-drop feedback architecture would have constituted a predictable use of prior art elements according to their established functions to further improve display uniformity and grayscale accuracy. The modification would have been well within ordinary design skill and would have yielded no unexpected result.
Regarding newly added claim 21:
Hong teaches wherein the voltage wire formed in the non-active area is formed with a wider width than voltage wires formed in an active area of the display panel (see at least [0039] “The switching elements (SW1, SW2) may be disposed in a non-display area NDA which surrounds the display area DA”; [0043] “The power bus lines (CB1, CB2) may receive the first power supply voltage ELVSS from a driving unit 10 which will be described later. The power bus lines (CB1, CB2) may be relatively wider than other wiring lines in order to effectively prevent a voltage drop. The power bus lines (CB1, CB2) may include a first power bus line CB1 and a second power bus line CB2. The first power bus line CB1 may be disposed outside and adjacent to the first side of the display area DA, and the second power bus line CB2 may be disposed outside and adjacent to the second side of the display area DA.”).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date, to form the non-active-area voltage wire of Lee ’542/Lee ’150 with a wider width than voltage wiring in the display area, as taught by Hong, in order to reduce resistive voltage drop. Increasing conductor width to reduce resistance and IR drop is a well-understood and predictable electrical design principle. Applying Hong’s known structural technique to the non-active-area voltage wire of Lee ’542/Lee ’150 would have predictably improved voltage uniformity, consistent with the shared objective of reducing voltage drop across the display panel.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JENNIFER L ZUBAJLO/ Examiner, Art Unit 2627 2/17/2026
/KE XIAO/ Supervisory Patent Examiner, Art Unit 2627