DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 7-9, 11-14, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable by SRINIVASAN et al. (US 20200333399 A1) (“SRINIVASAN”).
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Regarding claim 1, SRINIVASAN teaches a built-in self-test (BIST) system (Figures 1-3 item 10 discloses test circuitry 10 includes built-in self- test (BIST) in Paragraph [0014]) for an electronic circuit, comprising:
test circuitry (Figures 1-3 item 14 discloses the data path between the BIST logic 14 and memory 15 in Paragraph [0026]) for applying a test procedure (Figures 1-3 item scan signal between 13or 14 and 15) to the electronic circuit (Figures 1-3 item 15 discloses BIST_CLK path are checked during a single pass of scan testing, and that faults on both the data path between the BIST logic 14 and memory 15 in Paragraph [0026]); and
a clock circuit (Figures 1-3 item 11 discloses a first on chip clock (OCC1) source 11 in Paragraph [0015]) configured to:
provide a clock signal (Figures 1-3 item 11 discloses a first on chip clock (OCC1) source 11 in Paragraph [0015]) to the test circuitry (Figures 1-3 item 13 & 14 discloses BIST_CLK path are checked during a single pass of scan testing the data path between the BIST logic 14 and memory 15 and mux 13 in Paragraph [0026]); and
SRINIVASAN does not explicitly teach adjust a clock frequency of the clock signal;
However, SRINIVASAN teaches adjust a clock frequency of the clock signal (Figures 1-3 item 11 and 11T discloses a first on chip clock (OCC1) source 11 and distributed by a clock tree 11 t which provides phase shift in Paragraph [0015-0016]).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claimed invention, to modify detecting a test circuitry includes built-in self-test logic in SRINIVASAN, by substituting a shift phase in the clock signal by SRINIVASAN to provide checking for faults of the clock tree to the memory in Paragraph [0018]).
Regarding claim 2, SRINIVASAN teaches the BIST system of claim 1, wherein the test circuitry (Figures 1-3 item 13 or 14) is configured to apply the test procedure (Figures 1-3 item scan signal between 13 or 14 and 15) to the electronic circuit (Figures 1-3 item 15) during a power up phase (Figures 1-3 item 53 discloses scan signal will be high, and flip flop 53 will be set to logical one at POR (power on reset) in Paragraph [0029]).
Regarding claim 3, SRINIVASAN teaches the BIST system of claim 1, wherein the test circuitry is a digital logic circuit (Figures 1-3 item 13 & 14 discloses built-in self -test (BIST) logic 14 in Paragraph [0014]).
Regarding claim 7, SRINIVASAN teaches the BIST system of claim 1, wherein the BIST system and the electronic circuit (Figures 1-3 item 15) are implemented in an integrated circuit (Figures 1-3 item 13 or 14).
Regarding claim 8, SRINIVASAN teaches the BIST system of claim 7, wherein the integrated circuit is a microcontroller unit (MCU) (Figures 1-3 item 13 & 14 discloses built-in self- test (BIST) logic 14 which is considered a microcontroller in Paragraph [0014]) or a system-on-chip (SoC).
Regarding claim 9, SRINIVASAN teaches the BIST system of claim 1, wherein the BIST system is configured to:
be operable in a first mode or a second mode (Figures 1-3 discloses the test circuit is operating in the scan test mode or test circuit is operating in the BIST mode.t in Paragraph [0008]); and
switch between the first mode and the second mode (Figures 1-3 discloses the test circuit is operating in the scan test mode or switches test circuit is operating in the BIST mode.t in Paragraph [0008]);
wherein:
the clock circuit (Figures 1-3 item 11 & 12 discloses a first on chip clock (OCC1) source 11 and on chip clock (OCC2) source 12 in Paragraph [0015]) is configured to:
adjust the clock frequency of the clock signal to a first frequency value (Figures 1-3 item 11 & 11 t discloses a first on chip clock (OCC1) source 11 and distributed by a clock tree 11 t in Paragraph [0015]) during the first mode (Figures 1-3 discloses the test circuit is operating in the scan test mode or test circuit is operating in the BIST mode.t in Paragraph [0008]); and/or
adjust the clock frequency of the clock signal to a second frequency value (Figures 1-3 item 112 & 12 t discloses a second on chip clock (OCC2) source 12 and distributed by a clock tree 12 t in Paragraph [0015]) during the second mode (Figures 1-3 discloses the test circuit is operating in the scan test mode or test circuit is operating in the BIST mode.t in Paragraph [0008]).
Regarding claim 11, SRINIVASAN teaches the BIST system of claim 9, wherein the clock circuit is configured to provide the clock signal having an initial frequency value (Figures 1-3 item 11 discloses a first on chip clock (OCC1) source 11 in Paragraph [0015]) prior to adjusting the clock frequency of the clock signal (Figures 1-3 item 112 & 12 t discloses a second on chip clock (OCC2) source 12 and distributed by a clock tree 12 t in Paragraph [0015]).
Regarding claim 12, SRINIVASAN teaches the BIST system of claim 11, further comprising a memory element (Figures 1-3 item 15 discloses a memory 15 in Paragraph [0014]) for storing the initial frequency value, wherein the clock circuit is configured to receive the initial frequency value (Figures 1-3 item 11 discloses a first on chip clock (OCC1) source 11 in Paragraph [0015]) from the memory element (Figures 1-3 item 15 discloses a memory 15 in Paragraph [0014]).
Regarding claim 13, SRINIVASAN teaches the B BIST system of claim 12, wherein the memory element comprises a non-volatile memory element (Figures 1-3 item 15 discloses a memory 15 in Paragraph [0014]).
Regarding claim 14, SRINIVASAN teaches the BIST system of claim 13, wherein:
the non-volatile memory element is flash memory (Figures 1-3 item 15 discloses a memory 15 in Paragraph [0014]) comprising option bytes; and
the initial frequency value is stored in the option bytes (Figures 1-3 item 11 discloses provides the FUNC_CLK to the memory 15 in Paragraph [0014]).
Regarding claim 19, SRINIVASAN teaches an apparatus comprising:
an electronic circuit (Figures 1-3 item 15 discloses BIST_CLK path are checked during a single pass of scan testing, and that faults on both the data path between the BIST logic 14 and memory 15 in Paragraph [0026]); and
a built-in self-test (BIST) system (Figures 1-3 item 10 discloses test circuitry 10 includes built-in self- test (BIST) in Paragraph [0014]) for the electronic circuit (Figures 1-3 item 15) the BIST system comprising:
test circuitry (Figures 1-3 item 13 & 14 discloses the data path between the BIST logic 14 and memory 15 in Paragraph [0026]) for applying a test procedure (Figures 1-3 item scan signal between 13or 14 and 15) to the electronic circuit (Figures 1-3 item 15 discloses BIST_CLK path are checked during a single pass of scan testing, and that faults on both the data path between the BIST logic 14 and memory 15 in Paragraph [0026]); and
a clock circuit (Figures 1-3 item 11 discloses a first on chip clock (OCC1) source 11 in Paragraph [0015]) configured to:
provide a clock signal (Figures 1-3 item 11 discloses a first on chip clock (OCC1) source 11 in Paragraph [0015]) to the test circuitry (Figures 1-3 item 14 discloses BIST_CLK the data path between the BIST logic 14 and clock 11 in Paragraph [0026]); and
adjust a clock frequency of the clock signal provided to the test circuitry
SRINIVASAN does not explicitly teach adjust a clock frequency of the clock signal provided to the test circuitry;
However, SRINIVASAN teaches adjust a clock frequency of the clock signal (Figures 1-3 item 11 and 11T discloses a first on chip clock (OCC1) source 11 and distributed by a clock tree 11 t which provides phase shift in Paragraph [0015-0016]) provided to the test circuitry (Figures 1-3 item 13 & 14 discloses the data path between the BIST logic 14 and memory 15 in Paragraph [0026]);
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claimed invention, to modify detecting a test circuitry includes built-in self-test logic in SRINIVASAN, by substituting a shift phase in the clock signal by SRINIVASAN to provide checking for faults of the clock tree to the memory in Paragraph [0018]).
Regarding claim 20, SRINIVASAN teaches a method of performing a test procedure on an electronic circuit using a built-in self-test (BIST) system (Figures 1-3 item 10 discloses test circuitry 10 includes built-in self- test (BIST) in Paragraph [0014]), the method comprising:
applying a test procedure (Figures 1-3 item scan signal between 13or 14 and 15) to the electronic circuit (Figures 1-3 item 15 discloses BIST_CLK path are checked during a single pass of scan testing, and that faults on both the data path between the BIST logic 14 and memory 15 in Paragraph [0026]) using test circuitry (Figures 1-3 item 13 & 14 discloses the data path between the BIST logic 14 and memory 15 in Paragraph [0026]);
providing a clock signal (Figures 1-3 item 11 discloses a first on chip clock (OCC1) source 11 in Paragraph [0015]) to the test circuitry (Figures 1-3 item 13 & 14 in Paragraph [0026]) using a clock circuit (Figures 1-3 item 11 discloses a first on chip clock (OCC1) source 11 in Paragraph [0015]); and
SRINIVASAN does not explicitly teach adjusting a clock frequency of the clock signal provided to the test circuitry using the clock circuit.
However, SRINIVASAN teaches adjusting a clock frequency of the clock signal (Figures 1-3 item 11 and 11T discloses a first on chip clock (OCC1) source 11 and distributed by a clock tree 11 t which provides phase shift in Paragraph [0015-0016]) provided to the test circuitry (Figures 1-3 item 13 & 14 discloses the data path between the BIST logic 14 and memory 15 in Paragraph [0026]) using the clock circuit (Figures 1-3 item 11 discloses a first on chip clock (OCC1) source 11 in Paragraph [0015]).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claimed invention, to modify detecting a test circuitry includes built-in self-test logic in SRINIVASAN, by substituting a shift phase in the clock signal by SRINIVASAN to provide checking for faults of the clock tree to the memory in Paragraph [0018]).
Claims 4-6 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over SRINIVASAN et al. (US 20200333399 A1)) In view of KUROSAWA et al. (US 20160266199 A1).
Regarding claim 4, SRINIVASAN teaches the BIST system of claim 1,
SRINIVASAN does not explicitly teach wherein the BIST system is configured to be couplable to a power supply.
However, KUROSAWA teaches wherein the BIST system (Figures 1-2 discloses a BIST control circuit in Paragraph [0017 & 0021]) is configured to be couplable to a power supply (Figures 1-2 item 3 discloses a power supply or battery 3 in Paragraph [0017 & 0019]).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claimed invention, to modify detecting a test circuitry includes built-in self-test logic in SRINIVASAN, by substituting a BIST system is configured to be couplable to a power supply by KUROSAWA to provide success or failure of a BIST corresponding to the operation of circuit in Paragraph [0014])
Regarding claim 5, SRINIVASAN teaches the BIST system of claim 4.
SRINIVASAN does not explicitly teach wherein the power supply comprises a battery.
However, SHIMA teaches wherein the power supply comprises a battery (Figures 1-2 item 3 discloses a power supply or battery 3in Paragraph [0017 & 0019]),
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claimed invention, to modify detecting a test circuitry includes built-in self-test logic in SRINIVASAN, by substituting a BIST system is configured to be couplable to a power supply by KUROSAWA to provide success or failure of a BIST corresponding to the operation of circuit in Paragraph [0014])
Regarding claim 6, SRINIVASAN teaches the BIST system of claim 1,
SRINIVASAN does not explicitly teach wherein the BIST system is configured to be couplable to a power supply.
However, SHIMA teaches wherein the BIST system is configured to be couplable to a power supply (Figures 1-2 item 3 discloses a power supply or battery 3in Paragraph [0017 & 0019]).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claimed invention, to modify detecting a test circuitry includes built-in self-test logic in SRINIVASAN, by substituting a BIST system is configured to be couplable to a power supply by KUROSAWA to provide success or failure of a BIST corresponding to the operation of circuit in Paragraph [0014])
Regarding claim 10, SRINIVASAN teaches the BIST system of claim 9.
SRINIVASAN does not explicitly teach the first mode is a high-power mode;
the second mode is a low-power mode; and
the first frequency value is greater than the second frequency value.
However, SHIMA teaches the first mode is a high-power mode (Figures 1-3 item s20 discloses a current mode operates with the largest current consumption (S20) in Paragraph [0028]);
the second mode is a low-power mode (Figures 1-3 item s22 discloses a current mode operates with the second largest current consumption (S22)) in Paragraph [0028]); and
the first frequency value is greater than the second frequency value (Figures 1-3 item s20 is greater than (S20) in Paragraph [0028]).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claimed invention, to modify detecting a test circuitry includes built-in self-test logic in SRINIVASAN, by substituting a BIST system is configured to be couplable to a power supply by KUROSAWA to provide success or failure of a BIST corresponding to the operation of circuit in Paragraph [0014])
Claims 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over SRINIVASAN et al. (US 20200333399 A1)) In view of Duggal et al. (US 20190041440 A1).
Regarding claim 15, SRINIVASAN teaches the BIST system of claim 1, unit configured to:
receive the clock signal from a clock signal generator (Figures 1-3 item 11 discloses a first on chip clock (OCC1) source 11 in Paragraph [0015]);
adjust the clock frequency of the clock signal (Figures 1-3 item 11 and 11T discloses a first on chip clock (OCC1) source 11 and distributed by a clock tree 11 t which provides phase shift in Paragraph [0015-0016]) received from the clock signal generator (Figures 1-3 item 11 discloses a first on chip clock (OCC1) source 11 in Paragraph [0015]); and
provide the clock signal having the adjusted clock frequency (Figures 1-3 item 11 and 11T discloses a first on chip clock (OCC1) source 11 and distributed by a clock tree 11 t which provides phase shift in Paragraph [0015-0016]) to the test circuitry (Figures 1-3 item 13 & 14 discloses the data path between the BIST logic 14 and memory 15 in Paragraph [0026]) for applying a test procedure (Figures 1-3 item scan signal between 13or 14 and 15).
SRINIVASAN does not explicitly teach wherein the clock circuit comprises a frequency adjustment
However, Duggal teaches wherein the clock circuit comprises a frequency adjustment (Figures 8E item 850 discloses a frequency adjuster 850 in Paragraph [0111]).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claimed invention, to modify detecting a test circuitry includes built-in self-test logic in SRINIVASAN, by substituting a clock circuit comprises a frequency adjustment circuit by Duggal to provide a frequency monitor capable of operating in a self-test mode in Paragraph [0025]).
Regarding claim 16, SRINIVASAN teaches the BIST system of claim 15.
SRINIVASAN does not explicitly teach wherein the frequency adjustment unit comprises a prescaler.
However, Duggal teaches wherein the frequency adjustment unit comprises a prescaler (Figures 1-3 item 210 discloses a down counter 210 receives the clock signal 122 and lowers the signal in Paragraph [0050]).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claimed invention, to modify detecting a test circuitry includes built-in self-test logic in SRINIVASAN, by substituting a clock circuit comprises a frequency adjustment circuit by Duggal to provide a frequency monitor capable of operating in a self-test mode in Paragraph [0025]).
Regarding claim 17, SRINIVASAN teaches the BIST system of claim 15, wherein the clock circuit comprises the clock signal generator (Figures 1-3 item 11 discloses a first on chip clock (OCC1) source 11 in Paragraph [0015]).
Regarding claim 18, SRINIVASAN teaches the BIST system of claim 15, wherein the electronic circuit (Figures 1-3 item 15 discloses BIST_CLK path are checked during a single pass of scan testing, and that faults on both the data path between the BIST logic 14 and memory 15 in Paragraph [0026]) is configured to receive the clock signal from the clock signal generator (Figures 1-3 item 11 discloses a first on chip clock (OCC1) source 11 in Paragraph [0015]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRENT J ANDREWS whose telephone number is (571)272-6101. The examiner can normally be reached 10am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached at (571)272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRENT J ANDREWS/Examiner, Art Unit 2858
/JUDY NGUYEN/Supervisory Patent Examiner, Art Unit 2858
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