DETAILED ACTION
Status of Claims
Claims 1 – 20 are pending.
Claims 1, 8, and 15 are independent.
This office action is Non-Final.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1- 11, 13, 15 -18 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 - 20 of U.S. Patent No. 12,135,592. Although the claims at issue are not identical, they are not patentably distinct from each other because they are both directed to embedding resistive thermal device between layers of a printed circuit board wherein the RTD at least partially overlaps a mounted electrical component.
The similarities of the claims have been provided in the table below [emphasis made by the examiner].
Instant Application No. ‘894
Patent No. ‘592
1. A printed circuit board comprising: a first layer; a second layer on the first layer; a component surface-mounted to the first layer; and a resistive thermal device (RTD) between the first and second layers, wherein the RTD at least partially overlaps the component.
1. An electronic device comprising: a first substrate layer; a second substrate layer on the first substrate layer; an electrical component surface-mounted to the first substrate layer; and a resistive thermal device (RTD) that is disposed between the first substrate layer and the second substrate layer and that at least partially overlaps the electrical component.
5. The electronic device of claim 1, further comprising: a printed circuit board that includes the first substrate layer and the second substrate layer.
2. The printed circuit board of claim 1, wherein the RTD comprises: a flexible printed circuit between the first and second layers; and a conductive trace on the flexible printed circuit.
2. The electronic device of claim 1, wherein the RTD comprises: a flexible printed circuit substrate layered between the first substrate layer and the second substrate layer; and conductive traces on the flexible printed circuit.
3. The printed circuit board of claim 2, wherein the conductive trace comprises one or more bends.
3. The electronic device of claim 2, wherein the conductive traces have one or more bends.
4. The printed circuit of claim 3, wherein the conductive trace follows a meandering path.
14. The electronic device of claim 8, wherein the RTD comprises meandering conductive traces.
5. The printed circuit of claim 4, wherein the conductive trace has a resistance that varies linearly as a function of temperature across a range of temperatures.
7. The printed circuit board of claim 1, wherein the component is soldered to one or more contact pads on the first layer.1
15. A printed circuit board configured to receive a surface-mounted electrical component, the printed circuit board comprising: stacked layers; a first contact pad and a second contact pad embedded within the stacked layers; and a meandering conductive trace embedded within the stacked layers and extending from the first contact pad to the second contact pad, the meandering conductive trace having a resistance that varies linearly as a function of temperature across a range of operating temperatures associated with the surface-mounted electrical component.
6. The printed circuit board of claim 1, wherein an entirety of the RTD overlaps the component.
4. The electronic device of claim 1, wherein an entirety of the RTD overlaps the electrical component.
8. Apparatus comprising: a first dielectric layer; a second dielectric layer; a component mounted to a surface of the first dielectric layer; and a resistive thermal device (RTD) laminated between the first and second dielectric layers.
8. An electronic device comprising: a printed circuit board; an electrical component surface-mounted to the printed circuit board; and a resistive thermal device (RTD) that is laminated within the printed circuit board.
9. The apparatus of claim 8, wherein the RTD is configured to measure heat produced by the component.
9. The electronic device of claim 8, wherein the RTD is configured to measure heat produced by the electrical component.
10. The apparatus of claim 8, wherein the RTD at least partially overlaps the component.
10. The electronic device of claim 8, wherein the RTD at least partially overlaps the electrical component.
11. The apparatus of claim 8, wherein the component is adjustable based on a temperature measured using the RTD.
11. The electronic device of claim 8, wherein the electrical component is adjustable based on a temperature measured using the RTD.
13. The apparatus of claim 8, wherein the first and second dielectric layers are rigid.
16. The printed circuit board of claim 15, wherein the stacked layers are rigid.
15. A printed circuit board comprising: a stack of layers including a first layer and a second layer; at least one contact on the first layer and configured to receive a surface-mounted component; first and second contact pads between the first and second layers; and a meandering conductive trace extending from the first contact pad to the second contact pad, the meandering conductive trace having a resistance that varies linearly as a function of temperature across a range of operating temperatures.
15. A printed circuit board configured to receive a surface-mounted electrical component, the printed circuit board comprising: stacked layers; a first contact pad and a second contact pad embedded within the stacked layers; and a meandering conductive trace embedded within the stacked layers and extending from the first contact pad to the second contact pad, the meandering conductive trace having a resistance that varies linearly as a function of temperature across a range of operating temperatures associated with the surface-mounted electrical component.
16. The printed circuit board of claim 15, wherein the range of operating temperatures comprises a range of operating temperatures of the surface-mounted component.
15. A printed circuit board configured to receive a surface-mounted electrical component, the printed circuit board comprising: stacked layers; a first contact pad and a second contact pad embedded within the stacked layers; and a meandering conductive trace embedded within the stacked layers and extending from the first contact pad to the second contact pad, the meandering conductive trace having a resistance that varies linearly as a function of temperature across a range of operating temperatures associated with the surface-mounted electrical component.
17. The printed circuit board of claim 16, wherein the meandering conductive trace at least partially overlaps the at least one contact pad on the first layer.
17. The printed circuit board of claim 15, wherein the meandering conductive trace at least partially overlaps the surface-mounted electrical component.
18. The printed circuit board of claim 15, wherein the meandering conductive trace at least partially overlaps the at least one contact pad on the first layer.
17. The printed circuit board of claim 15, wherein the meandering conductive trace at least partially overlaps the surface-mounted electrical component.
20. The printed circuit board of claim 15, further comprising: a flexible printed circuit substrate between the first and second layers, wherein the first and second contact pads and the meandering trace are disposed on the flexible printed circuit substrate.
19. The printed circuit board of claim 15, further comprising: a flexible printed circuit substrate embedded in the stacked layers, the meandering conductive trace being disposed on the flexible printed circuit substrate.
Allowable Subject Matter
Claims 12, 14 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERRELL S JOHNSON whose telephone number is (571)270-3485. The examiner can normally be reached 10AM-7PM EST M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TERRELL S JOHNSON/Primary Examiner, Art Unit 2176
1 Soldering an electrical component to a contact pad on a printed circuit board is very well known and conventional method to mount the component to a board/device.