DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-7 in the reply filed on 07/10/2026 is acknowledged. Claims 8-20 are canceled and correspond to non-elected Groups II and III. Newly-added independent claims 21 and 29 each recite controlling a ramping voltage based on a number of cells similarly as independent claim 1, and thus correspond to elected Group I. Claims 1-7 and 21-33 are examined on the merit.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-7 and 21-33 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 12,112,801. Although the claims at issue are not identical, they are not patentably distinct from each other because when claims in the pending application are broader than the ones in the patent, the broad claims in the pending application are rejected under obviousness type double patenting over previously patented narrow claims, In re Van Ornum and Stang, 214 USPQ 761.
Instant App
Claim number
Pat ‘801
Claim number
1. (Original) A device comprising: a memory array having a plurality of cells; and a controller configured to: apply a ramping voltage to read the plurality of cells; determine a difference between a current number and a previous number of the cells at a first logic state; and end, based on comparing the difference to a threshold, the ramping voltage.
11. A memory device comprising: a memory array having a first and second plurality of cells; a controller configured to: apply a first ramping voltage with a first predetermined increment for each of a plurality of ramping steps of the first ramping voltage to read the first plurality of cells; count, among the first plurality of cells at each ramping step of the first ramping voltage, a first number of cells at a logic 1 state; compare the first number with a first predetermined threshold at each ramping step of the first ramping voltage; determine a first voltage reached by the first ramping voltage, at the first voltage the first number becoming equal to or higher than the first predetermined threshold; apply a second voltage to read the second plurality of cells, the second voltage being lower than the first voltage by a first predetermined amount; and apply a second ramping voltage ramping up from the second voltage with a second predetermined increment for each ramping step to read the second plurality of cells, the second predetermined increment being lower than the first predetermined increment by a second predetermined amount.
21. (New) A device comprising: a plurality of cells; and a controller configured to control a ramping voltage based on a number of the cells at a first logic state.
11
29. (New) A method comprising: applying a ramping voltage to read a plurality of cells; determining a difference between a current number and a previous number of the cells at a first logic state; and ending, based on comparing the difference to a threshold, the ramping voltage.
1. A method for reading a memory array having a first and second plurality of cells, the method comprising: applying a first ramping voltage with a first predetermined increment for each of a plurality of ramping steps of the first ramping voltage to read the first plurality of cells; counting, among the first plurality of cells at each ramping step of the first ramping voltage, a first number of cells at a logic 1 state; comparing the first number with a first predetermined threshold at each ramping step of the first ramping voltage; determining a first voltage reached by the first ramping voltage, at the first voltage the first number becoming equal to or higher than the first predetermined threshold; applying a second voltage to read the second plurality of cells, the second voltage being lower than the first voltage by a first predetermined amount; and applying a second ramping voltage ramping up from the second voltage with a second predetermined increment for each ramping step to read the second plurality of cells, the second predetermined increment being lower than the first predetermined increment by a second predetermined amount.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7, 25 and 31 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 7, 25 and 31, the limitation “an operating context of the memory device” is indefinite because it’s unclear what “an operating context” refers to.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7 and 21-33 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by TW202131325 (Umberto et al hereinafter Umberto).
Regarding claims 1, 21-24 and 29, Umberto discloses a device (figs. 1-14) comprising: a memory array having a plurality of cells (page 4, 5th para.: “FIG.1 … Each memory unit 105 can be programmable to store two or more states…. For example, the memory unit 105 can be configured to store one bit of digital logic (eg, logic 0 and logic 1) at a time. In some cases, a single memory cell 105 (eg, a multi-level memory cell) may be configured to store more than one bit of digital logic (eg, logic 00, logic 01, logic 10, or logic 11) at a time.); and a controller configured to: apply a ramping voltage to read the plurality of cells (page 3, 3rd para. :“ Under the control of the memory controller, each memory cell with an address code word is accessed, and it generates a voltage based on the previously programmed state in the memory cell. The voltage generated by each memory cell is compared with a reference voltage to determine the logic state of the memory cell. The generated cell voltage can be maintained on a capacitor, for example. Modify the reference voltage (for example, increase or decrease in a ramp-like manner, or divide the reference voltage range by dichotomy) until the count of memory cells that have been determined to be in a predefined logic state meets the criterion; the criterion may be in a predetermined logic state The count of the cells in the state matches the expected number as retrieved by the memory controller. For example, select a reduced reference voltage ramp (based on no bit transitions during the programming operation), and determine the number of memory cells in logic state 1 during the reference voltage ramp; the reference voltage is reduced until it is in logic state 1 The count of the cells is the same as the number of cells programmed to that logic state.“, page 24, 4th para.: “The memory controller 1215 may be an example of the memory controller 165 as described herein, and may be configured to activate the word line 1220, the plate line 1225, or the digit line 1240 by applying voltage to various nodes. For example, the bias component 1265 can be configured to apply a voltage to operate the memory cell 1210 to read or write the memory cell 1210, as described above. In some examples, the memory controller 1215 may include one or more of the column component 125, the row component 135, or the plate component 145 as described with reference to FIG. 1, or may perform the reference column component 125, the row component in other ways 135 or plate assembly 145 describes one or more operations, or can communicate with the column assembly 125, the row assembly 135, the plate assembly 145, or a combination thereof in other ways, which can enable the memory controller 1215 to access one or more A memory unit 1210. The bias component 1265 can provide a voltage (for example, a voltage source) for coupling with the memory cell 1210. Additionally or alternatively, the biasing component 1265 may provide a voltage (for example, a voltage source) for operating the sensing component 1250 or the reference component 1235.“ ); determine a difference between a current number and a previous number of the cells at a first logic state ( abstract, page, 23, 3rd and 4th para., page 33, 1st para.); and end, based on comparing the difference to a threshold, the ramping voltage (page 3, 3rd para., page 26, 2nd para.).
Regarding claims 2 and 33, Umberto also teaches wherein the first logic state is a logic 1 state (page 4, 5th para.: “FIG.1 illustrates an example of a memory die 100 according to an example as disclosed herein. In some cases, the memory die 100 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 100 may include one or more memory cells 105 that can be programmed to store different logic states. Each memory unit 105 can be programmable to store two or more states. For example, the memory unit 105 can be configured to store one bit of digital logic (eg, logic 0 and logic 1) at a time. In some cases, a single memory cell 105 (eg, a multi-level memory cell) may be configured to store more than one bit of digital logic (eg, logic 00, logic 01, logic 10, or logic 11) at a time.”)
Regarding claim 3, Umberto also teaches wherein the cells are data cells (page 4, 5th and 6th para.).
Regarding claims 4 and 30, Umberto also shows wherein the threshold corresponds to a distribution slope (figs. 7 and 8).
Regarding claims 5 and 26, Umberto also teaches wherein the controller is further configured to apply the ramping voltage in steps (fig. 7, page 16-17).
Regarding claims 6 and 27, Umberto also teaches wherein the controller is further configured to determine, at each of the steps, a difference between a current number and a previous number of the cells at the first logic state (page 17, 1st, 2nd and 3rd para.).
Regarding claims 7, 25, and 31, as best understood 112 2nd rejection above, Umberto also shows wherein the controller is further configured to determine a magnitude of the steps based on an operating context of a memory device (fig. 7, pages 16-17).
Regarding claim 28, Umberto also shows wherein the ramping voltage is controlled based on evaluating a number of the cells at the first logic state based on a distribution slope (fig. 7, pages 16-17).
Regarding claim 32, Umberto also teaches further comprising changing a step size of the ramping voltage based on a number of the cells at the first logic state (fig. 7, pages 16-17).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN D NGUYEN whose telephone number is (571)272-8163. The examiner can normally be reached 6:30-3:00 PM.
Examiner interviews are available via telephone and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TUAN D NGUYEN/Primary Examiner, Art Unit 2824
Prosecution Insights