Prosecution Insights
Last updated: July 17, 2026
Application No. 18/904,078

APPARATUS AND METHOD FOR REDUCING OR ADJUSTING UNBALANCED PERFORMANCE BASED ON BAD BLOCKS IN A MEMORY DEVICE

Non-Final OA §112
Filed
Oct 02, 2024
Priority
May 28, 2024 — RE 10-2024-0069548
Examiner
CHOWDHURY, SUBIR KUMAR
Art Unit
2132
Tech Center
2100 — Computer Architecture & Software
Assignee
SK hynix Inc.
OA Round
3 (Non-Final)
78%
Grant Probability
Favorable
3-4
OA Rounds
5m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
25 granted / 32 resolved
+23.1% vs TC avg
Moderate +9% lift
Without
With
+9.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
27 currently pending
Career history
66
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
86.6%
+46.6% vs TC avg
§102
7.8%
-32.2% vs TC avg
§112
4.3%
-35.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 32 resolved cases

Office Action

§112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/04/2026 has been entered. Response to Amendment The office action is responding to the arguments filed on 05/04/2026. Claims 1- 20 are pending. Foreign priority claim is acknowledged in Bib datasheet. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1, 10 and 16 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The added limitation in the amended claims 1, 10 and 16 “wherein the inactive area is not only an unused or not working area for data input or output but is also not included in storage capacity” does not have sufficient support in the specification. The specification discloses the "bad blocks in the seventh memory block 326 can have a size of 7% of the total capacity" in paragraph [0093] and also “the controller 210 can set an unused super block to 7% of the total capacity for each of the fourth memory die 318B” in paragraph [0106] for Fig 5 but not specifically bad blocks, unused blocks or area are not included in storage capacity. Claim 1, 10 and 16 are therefore rejected under 35 U.S.C. 112 (pre-AIA ), first paragraph as failing to comply with the written description requirement. Dependent claims 2-9, 11-15 and 17-20 are rejected based on their dependency on rejected claims 1, 10 and 16. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 1, 10 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre- AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 1, 10 and 16 amendment states “wherein the inactive area is not only an unused or not working area for data input or output but is also not included in storage capacity” where inactive area is defined by either unused or not working which is unclear and also examiner considers unused and not working are contrary to each other where unused can be used, reserved for future if it’s not bad but may be working fine whereas not working clearly means bad blocks. Dependent claims 2-9, 11-15 and 17-20 are rejected based on their dependency on rejected claims 1, 10 and 16. Allowable Subject Matter Claims 1, 10 and 16 are allowable if the 35 U.S.C. 112(a) and 112(b) rejections set forth above are overcome. Examiner has conducted update search and given considerations to applicant’s arguments and/or requests. The prior art does not teach “wherein the inactive area is not only an unused or not working area for data input or output but is also not included in storage capacity; and a controller configured to check a bad block occurring or found in at least one of the plural memory dies and adjust an inactive area size in the at least one of the plural memory dies based on the bad block to equal a sum of a bad block size and the inactive area size in the at least one of the plural memory dies to another sum of a bad block size and an inactive area size in another memory die among the plural memory dies” limitations of claims 1, 10 and 16. The closest prior art KIM et al. (US 20160148656 A1) does teach memory dies may include active and inactive regions where total active regions of memory dies may equal to memory capacity or in other words inactive regions may not be included in total memory capacity. Also, SHIN et al. (US 20180018091 A1) does teach controller may determine a reference value RV for selecting a victim block using valid page and bad block information reflecting weight of bad blocks and inactive area and weight can be adjusted based on number of bad blocks included. But none of the prior arts appear to teach inactive area is not included in total storage capacity and controller may adjust an inactive area size in the at least one of the plural memory dies based on the bad block to equal a sum of a bad block size and the inactive area size in the at least one of the plural memory dies to another sum of a bad block size and an inactive area size in another memory die among the plural memory dies. Therefore, claims 1, 10 and 16 and their dependent claims are allowed. Response to Arguments Applicant’s arguments filed on 05/04/2026 have been fully considered and are Persuasive. However, in the current action, Claim(s) 1, 10 and 16 have been rejected under 35 U.S.C. 112(a) for failing to comply with the written description requirement and 35 U.S.C. 112(b) for contradicting language and unclear definition of inactive regions of memory. Claims 1, 10 and 16 would be allowed if the 35 USC 112(a) and 35 U.S.C. 112(b) rejections are overcome. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUBIR K CHOWDHURY whose telephone number is (703)756-1207. The examiner can normally be reached Monday-Friday 8:30 - 5:00 CST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571)-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /S.K.C./Examiner, Art Unit 2132 /HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
Read full office action

Prosecution Timeline

Oct 02, 2024
Application Filed
Oct 01, 2025
Non-Final Rejection mailed — §112
Jan 02, 2026
Response Filed
Feb 04, 2026
Final Rejection mailed — §112
May 04, 2026
Request for Continued Examination
May 06, 2026
Response after Non-Final Action
Jun 10, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12669941
METHOD FOR DETECTING TEMPERATURE IN A FLASH MEMORY DEVICE AND THE FLASH MEMORY DEVICE THEREOF
2y 5m to grant Granted Jun 30, 2026
Patent 12638980
MEMORY SYSTEMS, METHODS, AND MEDIA HAVING A DYNAMIC SYSTEM AREA
2y 5m to grant Granted May 26, 2026
Patent 12625814
GRAPHICS PROCESSOR MEMORY ACCESS ARCHITECTURE WITH ADDRESS SORTING
4y 7m to grant Granted May 12, 2026
Patent 12566564
EFFICIENT USAGE OF REDUNDANT COLUMNS IN FLASH MEMORY
2y 6m to grant Granted Mar 03, 2026
Patent 12535967
BUFFERING DEVICE AND CONTROL METHOD THEREOF
2y 1m to grant Granted Jan 27, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
78%
Grant Probability
87%
With Interview (+9.0%)
2y 3m (~5m remaining)
Median Time to Grant
High
PTA Risk
Based on 32 resolved cases by this examiner. Grant probability derived from career allowance rate.

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