Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The office action is responding to the arguments filed on 01/02/2026. Claims 1-
20 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (US 20160148656 A1) in view of SHIN et al. (US 20180018091 A1) hereinafter KIM and SHIN.
Regarding claim 1, KIM teaches A memory system comprising: a memory
device comprising plural memory dies, (see Fig 1, paragraph [0063], illustrates memory device 10 may include a plurality of dies 100 and 200)
each memory die comprising plural memory blocks including an active area and an inactive area; and (see Fig 3, paragraph [0070], illustrates memory region 150 may include active region 151 and inactive region 152)
KIM teaches bad block management for memory devices above. However, KIM does not explicitly teach a controller configured to check a bad block occurring or found in at least one of the plural memory dies and
adjust an inactive area size in the at least one of the plural memory dies based on the bad block to equal a sum of a bad block size and the inactive area size in the at least one of the plural memory dies to another sum sums of a bad block size and an inactive area size in another memory die among the plural memory dies
On the other hand, SHIN which also relates to bad block management for
memory devices teaches a controller configured to check a bad block occurring or found in at least one of the plural memory dies and (see Fig 1, paragraph [0110], illustrates controller 130 may decide bad blocks among the memory blocks included in each of the super blocks, and generate information on the bad blocks)
adjust an inactive area size in the at least one of the plural memory dies based on the bad block to equal a sum of a bad block size and the inactive area size in the at least one of the plural memory dies to another sum sums of a bad block size and an inactive area size in another memory die among the plural memory dies (see Fig 6B and 7, paragraph [0112], illustrates at 710 and 710 controller 130 may determine a reference value RV for selecting a victim block using valid page and bad block information at step 730 reflecting weight of bad blocks and inactive area and weight can be adjusted based on number of bad blocks included)
Both KIM and SHIN relate to bad block management for memory devices (see
KIM, abstract, and see SHIN, abstract, regarding bad block management for memory
devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine KIM with SHIN by incorporating
bad block management for memory devices by making determination of
bad blocks in plurality of dies, as taught by SHIN; to illustrate controller 130 may decide bad blocks among the memory blocks included in each of the super blocks, and generate information on the bad blocks and also controller 130 may determine a reference value RV for selecting a victim block using valid page and bad block information at step 730 reflecting weight of bad blocks and inactive area and weight can be adjusted based on number of bad blocks included. The combined
system of KIM – SHIN allows a controller suitable to set super blocks each including respective memory blocks that belong to two or more memory arrays among the plurality of the memory arrays and performing a garbage collection operation on the super blocks based on a valid page information and a wearing level of each super block as mentioned in paragraph [0006]. Therefore, the combination of KIM - SHIN improves wear-leveling in a memory device. See SHIN, paragraph [0117].
Regarding claim 2, KIM in view of SHIN teaches bad block management for memory devices above. However, KIM - SHIN combination does not explicitly teach The memory system according to claim 1, wherein the controller is configured to determine an inactive area size of a first memory die according to a bad block size in the first memory die, so that a sum of the inactive area size and the bad block size for the first memory becomes a same as a sum for another memory die
On the other hand, KIM which also relates to bad block management for
memory devices teaches The memory system according to claim 1, wherein the controller is configured to determine an inactive area size of a first memory die according to a bad block size in the first memory die, so that a sum of the inactive area size and the bad block size for the first memory becomes a same as a sum for another memory die. (see Fig 9, paragraph [0105], illustrates two memory dies having two deactivated regions based on failed regions where half memory capacity each and full memory capacity may be implemented)
The same motivation that was utilized for combining KIM – SHIN combination
with Qiu as set forth in claim 1 is equally applicable to claim 2.
Regarding claim 10, KIM teaches A memory system comprising: a memory device comprising a plurality of memory dies, each memory die comprising a plurality of memory blocks; (see Fig 1, paragraph [0063], illustrates memory device 10 may include a plurality of dies 100 and 200)
KIM teaches bad block management for memory devices above. However, KIM does not explicitly teach a controller configured to check a bad block occurring or found in at least one of the plural memory dies and
perform at least one of adjusting scheduling of data input/output operations to be performed in at least one of the plurality of memory dies or adjusting an inactive area size in each of the plurality of memory dies, based on a difference in bad block sizes of the plurality of memory dies
On the other hand, SHIN which also relates to bad block management for
memory devices teaches a controller configured to check a bad block occurring or found in at least one of the plural memory dies and (see Fig 1, paragraph [0110], illustrates controller 130 may decide bad blocks among the memory blocks included in each of the super blocks, and generate information on the bad blocks)
perform at least one of adjusting scheduling of data input/output operations to be performed in at least one of the plurality of memory dies or adjusting an inactive area size in each of the plurality of memory dies, based on a difference in bad block sizes of the plurality of memory dies (see Fig 6B and 7, paragraph [0112], illustrates at 710 and 710 controller 130 may determine a reference value RV for selecting a victim block using valid page and bad block information at step 730 reflecting weight of bad blocks and inactive area and weight can be adjusted based on number of bad blocks included)
Both KIM and SHIN relate to bad block management for memory devices (see
KIM, abstract, and see SHIN, abstract, regarding bad block management for memory
devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine KIM with SHIN by incorporating
bad block management for memory devices by making determination of
bad blocks in plurality of dies, as taught by SHIN; to illustrate controller 130 may decide bad blocks among the memory blocks included in each of the super blocks, and generate information on the bad blocks and also controller 130 may determine a reference value RV for selecting a victim block using valid page and bad block information at step 730 reflecting weight of bad blocks and inactive area and weight can be adjusted based on number of bad blocks included. The combined
system of KIM – SHIN allows a controller suitable to set super blocks each including respective memory blocks that belong to two or more memory arrays among the plurality of the memory arrays and performing a garbage collection operation on the super blocks based on a valid page information and a wearing level of each super block as mentioned in paragraph [0006]. Therefore, the combination of KIM - SHIN improves wear-leveling in a memory device. See SHIN, paragraph [0117].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of SHIN and further in view of SOHN et al. (US 20150134895 A1) hereinafter SOHN.
Regarding claim 3, KIM in view of SHIN teaches bad block management for memory devices in claim 1. However, KIM - SHIN combination does not explicitly teach The memory system according to claim 1, wherein the controller is configured to determine, as the inactive area, at least one cell string among a plurality of cell strings included in each of the plurality of memory dies
On the other hand, SOHN which also relates to bad block management for memory devices teaches The memory system according to claim 1, wherein the controller is configured to determine, as the inactive area, at least one cell string among a plurality of cell strings included in each of the plurality of memory dies. (see Fig 1, paragraph [0032], illustrates bad block includes one or more rows and one bad row may include at least one bad cell)
Both KIM, SHIN and SOHN relate to bad block management for memory devices (see KIM, abstract, see SHIN, abstract, and see SOHN, abstract, regarding bad block management for memory devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine KIM - SHIN combination with SOHN by incorporating bad block management for memory devices by making determination of
bad blocks in plurality of dies, as taught by SOHN; to illustrate bad block may include one or more rows and one bad row may include at least one bad cell. The combined system of KIM - SHIN – SOHN allows bad block management for memory devices by making determination of bad blocks in plurality of dies where bad block may include one or more rows and one bad row may include at least one bad cell providing a structure and functionality of bad block as mentioned in paragraph [0033]. Therefore, the combination of KIM - SHIN - SOHN improves performance. See SOHN, paragraph [0003].
Regarding claim 4, KIM in view of SHIN teaches bad block management for memory devices in claim 1. However, KIM - SHIN combination does not explicitly teach The memory system according to claim 1, wherein the controller is configured to determine, as the inactive area, memory cells coupled to at least one word line among a plurality of word lines included in each of the plurality of memory dies.
On the other hand, SOHN which also relates to bad block management for memory devices teaches The memory system according to claim 1, wherein the controller is configured to determine, as the inactive area, memory cells coupled to at least one word line among a plurality of word lines included in each of the plurality of memory dies. (see Fig 1, paragraph [0032], illustrates bad block includes one or more rows or word lines and one bad word line may include at least one bad cell)
Both KIM, SHIN and SOHN relate to bad block management for memory devices (see KIM, abstract, see SHIN, abstract, and see SOHN, abstract, regarding bad block management for memory devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine KIM - SHIN combination with SOHN by incorporating bad block management for memory devices by making determination of bad blocks in plurality of dies, as taught by SOHN; to illustrate bad block may include one or more rows or word lines and one bad word line may include at least one bad cell. The combined system of KIM - SHIN – SOHN allows bad block management for memory devices by making determination of bad blocks in plurality of dies where bad block may include one or more rows or word lines and one bad word line may include at least one bad cell providing a structure and functionality of bad block as mentioned in paragraph [0033]. Therefore, the combination of KIM - SHIN - SOHN improves performance. See SOHN, paragraph [0003].
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of SHIN and further in view of CAMP et al. (US 20170242592 A1) hereinafter CAMP.
Regarding claim 5, KIM in view of SHIN teaches bad block management for memory devices in claim 1. However, KIM - SHIN combination does not explicitly teach The memory system according to claim 1, wherein the memory device comprises an over provisioning area including at least the inactive area and the bad blocks in each of the plurality of memory dies, and
wherein the controller is configured to determine sizes of the over provisioning areas in the plurality of memory dies to be equal to each other
On the other hand, CAMP which also relates to bad block management for memory devices teaches The memory system according to claim 1, wherein the memory device comprises an over provisioning area including at least the inactive area and the bad blocks in each of the plurality of memory dies, and (see Fig 11, paragraph [0068], illustrates memory system 150 may have over-provisioning space for three simulated workloads without compression)
wherein the controller is configured to determine sizes of the over provisioning areas in the plurality of memory dies to be equal to each other. (see Fig 16, paragraph [0077] and [0078], illustrates flash controller provisioning manager may determine over-provisioning space using workload characteristics)
Both KIM, SHIN and SOHN relate to bad block management for memory devices (see KIM, abstract, see SHIN, abstract, and see SOHN, abstract, regarding bad block management for memory devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine KIM - SHIN combination with CAMP by incorporating bad block management for memory devices by making determination of bad blocks in plurality of dies, as taught by CAMP; to illustrate memory system may have over-provision space using workload characteristics and enable flash controller provisioning manager may determine over-provisioning space using workload characteristics. The combined system of KIM - SHIN – CAMP allows bad block management for memory devices by making determination of bad blocks in plurality of dies where memory system may have over-provision space using workload characteristics and inactive data and enable flash controller provisioning manager may determine over-provisioning space using workload characteristics and dynamic over-provisioning as mentioned in paragraph [0034]. Therefore, the combination of KIM - SHIN - CAMP improves performance. See CAMP, paragraph [0033].
Claim(s) 6-7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of SHIN and further in view of CHO et al. (US 20220075542 A1) hereinafter CHO.
Regarding claim 6, KIM in view of SHIN teaches bad block management for memory devices in claim 1. However, KIM - SHIN combination does not explicitly teach The memory system according to claim 1, wherein the controller is further configured to adjust data input/output performance of each of the plurality of memory dies to be equal
On the other hand, CHO which also relates to bad block management for memory devices teaches The memory system according to claim 1, wherein the controller is further configured to adjust data input/output performance of each of the plurality of memory dies to be equal. (see Fig 7, paragraph [0135], illustrates input/output operating performance can be changed for all dies connected to a particular channel. In other words, performance in same channel is same for all dies connected to the channel)
Both KIM, SHIN and SOHN relate to bad block management for memory devices (see KIM, abstract, see SHIN, abstract, and see CHO, abstract, regarding bad block management for memory devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine KIM - SHIN combination with CHO by incorporating bad block management for memory devices by making determination of bad blocks in plurality of dies, as taught by CHO; to enable input/output operating performance to be changed for all dies connected to a particular channel or performance in same channel to be same for all dies connected to the channel. The combined system of KIM - SHIN – CHO allows bad block management for memory devices by making determination of bad blocks in plurality of dies where input/output operating performance to be changed for all dies connected to a particular channel or performance in same channel to be same for all dies connected to the channel and calibration operation for data communication between a controller and a memory die as mentioned in paragraph [0039]. Therefore, the combination of KIM - SHIN - CHO improves reliability. See CHO, paragraph [0026].
Regarding claim 7, KIM in view of SHIN and further in view of CHO teaches bad block management for memory devices in claim 6. However, KIM - SHIN - CHO combination does not explicitly teach The memory system according to claim 6, wherein the controller is further configured to determine the data input/output performance based on a random data writing operation performed on each of the plurality of memory dies.
On the other hand, CHO which also relates to bad block management for memory devices teaches The memory system according to claim 6, wherein the controller is further configured to determine the data input/output performance based on a random data writing operation performed on each of the plurality of memory dies. (see Fig 1, paragraph [0070], illustrates memory device 150 may perform a write operation to store data to perform data I/O operation. In other words, I/O performance may be based on write operations)
The same motivation that was utilized for combining KIM - SHIN combination and CHO as set forth in claim 6 is equally applicable to claim 7.
Regarding claim 15, KIM in view of SHIN teaches bad block management for memory devices in claim 10. However, KIM - SHIN combination does not explicitly teach The memory system according to claim 10, wherein the controller is configured to adjust random data write performance of each of the plurality of memory dies to be substantially a same
On the other hand, CHO which also relates to bad block management for memory devices teaches The memory system according to claim 10, wherein the controller is configured to adjust random data write performance of each of the plurality of memory dies to be substantially a same. (see Fig 7, paragraph [0135], illustrates input/output operating performance can be changed for all dies connected to a particular channel. In other words, performance in same channel is same for all dies connected to the channel)
Both KIM, SHIN and SOHN relate to bad block management for memory devices (see KIM, abstract, see SHIN, abstract, and see CHO, abstract, regarding bad block management for memory devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine KIM - SHIN combination with CHO by incorporating bad block management for memory devices by making determination of bad blocks in plurality of dies, as taught by CHO; to enable input/output operating performance to be changed for all dies connected to a particular channel. The combined system of KIM - SHIN – CHO allows bad block management for memory devices by making determination of bad blocks in plurality of dies where input/output operating performance to be changed for all dies connected to a particular channel and calibration operation for data communication between a controller and a memory die as mentioned in paragraph [0039]. Therefore, the combination of KIM - SHIN - CHO improves reliability. See CHO, paragraph [0026].
Claim(s) 8-9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of SHIN and further in view of Kryvaltsevich et al. (US 20170285945 A1) hereinafter Kryvaltsevich.
Regarding claim 8, KIM in view of SHIN teaches bad block management for memory devices in claim 2. However, KIM - SHIN combination does not explicitly teach The memory system according to claim 2, wherein the controller is further configured to control a throttling level for the first memory die according to the bad block size in the first memory die
On the other hand, Kryvaltsevich which also relates to bad block management for memory devices teaches The memory system according to claim 2, wherein the controller is further configured to control a throttling level for the first memory die according to the bad block size in the first memory die. (see Fig 8, paragraph [0110] - [0121], illustrates throttling mode may be calculated based on bad blocks, valid and invalid blocks)
Both KIM, SHIN and SOHN relate to bad block management for memory devices (see KIM, abstract, see SHIN, abstract, and see Kryvaltsevich, abstract, regarding bad block management for memory devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine KIM - SHIN combination with Kryvaltsevich by incorporating bad block management for memory devices by making determination of bad blocks in plurality of dies, as taught by Kryvaltsevich; to enable throttling mode to be calculated based on bad blocks, valid and invalid blocks. The combined system of KIM - SHIN – Kryvaltsevich allows bad block management for memory devices by making determination of bad blocks in plurality of dies where throttling mode to be calculated based on bad blocks, valid and invalid blocks and balanced throttling of the memory system as mentioned in paragraph [0032]. Therefore, the combination of KIM - SHIN - Kryvaltsevich improves performance consistency and stabilize the memory system. See Kryvaltsevich, paragraph [0036].
Regarding claim 9, KIM in view of SHIN teaches bad block management for memory devices in claim 2. However, KIM - SHIN combination does not explicitly teach The memory system according to claim 2, wherein the controller is further configured to adjust a ratio of host write operations and garbage collection write operations for the first memory die according to the bad block size in the first memory die.
On the other hand, Kryvaltsevich which also relates to bad block management for memory devices teaches The memory system according to claim 2, wherein the controller is further configured to adjust a ratio of host write operations and garbage collection write operations for the first memory die according to the bad block size in the first memory die. (see Fig 14, paragraph [0161], illustrates in step 1406 calculating garbage collection and host ratio based on invalid of bad blocks for adjusting throttling parameters where host is involved in sending write commands)
Both KIM, SHIN and SOHN relate to bad block management for memory devices (see KIM, abstract, see SHIN, abstract, and see Kryvaltsevich, abstract, regarding bad block management for memory devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine KIM - SHIN combination with Kryvaltsevich by incorporating bad block management for memory devices by making determination of bad blocks in plurality of dies, as taught by Kryvaltsevich; to enable calculating garbage collection and host ratio based on invalid of bad blocks for adjusting throttling parameters where host is involved in sending write commands. The combined system of KIM - SHIN – Kryvaltsevich allows bad block management for memory devices by making determination of bad blocks in plurality of dies and calculating garbage collection and host ratio based on invalid of bad blocks for adjusting throttling parameters where host is involved in sending write commands and balanced throttling of the memory system as mentioned in paragraph [0032]. Therefore, the combination of KIM - SHIN - Kryvaltsevich improves performance consistency and stabilize the memory system. See Kryvaltsevich, paragraph [0036].
Regarding claim 11, KIM in view of SHIN teaches bad block management for memory devices in claim 10. However, KIM - SHIN combination does not explicitly teach The memory system according to claim 10, wherein, when adjusting the scheduling of the data input/output operations, the controller is configured to adjust at least one of throttling levels for at least one of the plurality of memory dies and a ratio of host write operations and garbage collection write operations performed on at least one of the plurality of memory dies
On the other hand, Kryvaltsevich which also relates to bad block management for memory devices teaches The memory system according to claim 10, wherein, when adjusting the scheduling of the data input/output operations, the controller is configured to adjust at least one of throttling levels for at least one of the plurality of memory dies and a ratio of host write operations and garbage collection write operations performed on at least one of the plurality of memory dies. (see Fig 14, paragraph [0161], illustrates in step 1406 calculating garbage collection and host ratio based on invalid of bad blocks for adjusting throttling parameters where host is involved in sending write commands)
Both KIM, SHIN and Kryvaltsevich relate to bad block management for memory devices (see KIM, abstract, see SHIN, abstract, and see Kryvaltsevich, abstract, regarding bad block management for memory devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine KIM - SHIN combination with Kryvaltsevich by incorporating bad block management for memory devices by making determination of bad blocks in plurality of dies, as taught by Kryvaltsevich; to enable calculating garbage collection and host ratio based on invalid of bad blocks for adjusting throttling parameters where host is involved in sending write commands. The combined system of KIM - SHIN – Kryvaltsevich allows bad block management for memory devices by making determination of bad blocks in plurality of dies and calculating garbage collection and host ratio based on invalid of bad blocks for adjusting throttling parameters where host is involved in sending write commands and balanced throttling of the memory system as mentioned in paragraph [0032]. Therefore, the combination of KIM - SHIN - Kryvaltsevich improves performance consistency and stabilize the memory system. See Kryvaltsevich, paragraph [0036].
Claim(s) 12 is rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of SHIN and further in view of LEE et al. (US 20200211665 A1) hereinafter LEE.
Regarding claim 12, KIM in view of SHIN teaches bad block management for memory devices in claim 10. However, KIM - SHIN combination does not explicitly teach The memory system according to claim 10, wherein the controller is configured to: determine a first memory die including a greatest number of bad blocks among the plurality of memory dies, set the first memory die to include no inactive area; and determine an inactive area size in each of remaining memory dies other than the first memory die among the plurality of memory dies based on a difference in bad block sizes of the first memory die and each of the remaining memory dies
On the other hand, LEE which also relates to bad block management for memory devices teaches The memory system according to claim 10, wherein the controller is configured to: determine a first memory die including a greatest number of bad blocks among the plurality of memory dies, set the first memory die to include no inactive area; and determine an inactive area size in each of remaining memory dies other than the first memory die among the plurality of memory dies based on a difference in bad block sizes of the first memory die and each of the remaining memory dies. (see Fig 6 and 7, paragraph [0088] and [0091], illustrates in step S604 controller 130 may generate a bad lists like 702 and 704 containing number of bad blocks in each die containing normal blocks and bad blocks)
Both KIM, SHIN and LEE relate to bad block management for memory devices (see KIM, abstract, see SHIN, abstract, and see LEE, abstract, regarding bad block management for memory devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine KIM - SHIN combination with LEE by incorporating bad block management for memory devices by making determination of bad blocks in plurality of dies, as taught by LEE; to enable controller to generate a bad lists containing number of bad blocks in each die containing normal blocks and bad blocks. The combined system of KIM - SHIN – LEE allows bad block management for memory devices by making determination of bad blocks in plurality of dies where controller to generate a bad lists containing number of bad blocks in each die containing normal blocks and bad blocks and controller detecting bad super memory blocks each including at least one bad block, among the plurality of super memory blocks as mentioned in paragraph [0008]. Therefore, the combination of KIM - SHIN - LEE improves performance of operations. See LEE, paragraph [0101].
Claim(s) 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of SHIN and further in view of LEE and further in view of SOHN.
Regarding claim 13, KIM in view of SHIN and further in view of LEE teaches bad block management for memory devices in claim 12. However, KIM - SHIN - LEE combination does not explicitly teach The memory system according to claim 12, wherein the controller is configured to determine, as the inactive area, at least one cell string among a plurality of cell strings in each of the plurality of memory dies
On the other hand, SOHN which also relates to bad block management for memory devices teaches The memory system according to claim 12, wherein the controller is configured to determine, as the inactive area, at least one cell string among a plurality of cell strings in each of the plurality of memory dies. (see Fig 1, paragraph [0032], illustrates bad block includes one or more rows and one bad row may include at least one bad cell)
Both KIM, SHIN, LEE and SOHN relate to bad block management for memory devices (see KIM, abstract, see SHIN, abstract, see LEE, abstract, and see SOHN, abstract regarding bad block management for memory devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine KIM - SHIN - LEE combination with SOHN by incorporating bad block management for memory devices by making determination of bad blocks in plurality of dies, as taught by SOHN; to illustrate bad block includes one or more rows and one bad row may include at least one bad cell. The combined system of KIM - SHIN – LEE - SOHN allows bad block management for memory devices by making determination of bad blocks in plurality of dies where bad block includes one or more rows and one bad row may include at least one bad cell providing a structure and functionality of bad block as mentioned in paragraph [0033]. Therefore, the combination of KIM - SHIN - LEE - SOHN improves performance. See SOHN, paragraph [0003].
Regarding claim 14, KIM in view of SHIN and further in view of LEE teaches bad block management for memory devices in claim 12. However, KIM - SHIN - LEE combination does not explicitly teach The memory system according to claim 12, wherein the controller is configured to determine, as the inactive area, memory cells coupled to at least one word line among a plurality of word lines in each of the plurality of memory dies.
On the other hand, SOHN which also relates to bad block management for memory devices teaches The memory system according to claim 12, wherein the controller is configured to determine, as the inactive area, memory cells coupled to at least one word line among a plurality of word lines in each of the plurality of memory dies. (see Fig 1, paragraph [0032], illustrates bad block includes one or more rows or word lines and one bad word line may include at least one bad cell)
Both KIM, SHIN, LEE and SOHN relate to bad block management for memory devices (see KIM, abstract, see SHIN, abstract, see LEE, abstract, and see SOHN, abstract regarding bad block management for memory devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine KIM - SHIN - LEE combination with SOHN by incorporating bad block management for memory devices by making determination of bad blocks in plurality of dies, as taught by SOHN; to illustrate bad block includes one or more rows or word lines and one bad word line may include at least one bad cell. The combined system of KIM - SHIN – LEE - SOHN allows bad block management for memory devices by making determination of bad blocks in plurality of dies where bad block includes one or more rows or word lines and one bad word line may include at least one bad cell providing a structure and functionality of bad block as mentioned in paragraph [0033]. Therefore, the combination of KIM - SHIN - LEE - SOHN improves performance. See SOHN, paragraph [0003].
Claim(s) 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 20250147880 A1) in view of CHO et al. (US 20220075542 A1) hereinafter CHO.
Regarding claim 16, Zhang teaches wherein the controller is configured to: adjust first inactive area sizes in the plurality of first memory dies based on first bad block sizes in the plurality of first memory dies; and adjust second inactive area sizes in the plurality of second memory dies based on second bad block sizes occurring or found in the plurality of second memory dies. (see Fig 3A, paragraph [0081], illustrates controller 300 may determine total number of expected used or inactive spaces and may adjust a predetermined threshold based on needs or actual sizes. In other words, controller can adjust a saturation threshold of used or inactive areas based on needs or actual sizes)
Zhang teaches bad block management for memory devices. However, Zhang does not explicitly teach A memory system comprising: a memory device comprising a plurality of first memory dies and a plurality of second memory dies; and a controller coupled to the plurality of first memory dies through a first channel and coupled to the plurality of second memory dies through a second channel
On the other hand, CHO which also relates to bad block management for memory devices teaches A memory system comprising: a memory device comprising a plurality of first memory dies and a plurality of second memory dies; and a controller coupled to the plurality of first memory dies through a first channel and coupled to the plurality of second memory dies through a second channel, (see Fig 7, paragraph [0135], illustrates CH1 is coupled to plurality of dies and CH2 is connected to plurality of dies)
Both Zhang and CHO relate to bad block management for memory devices (see Zhang, abstract, and see CHO, abstract, regarding bad block management for memory devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Zhang with CHO by incorporating
bad block management for memory devices by making determination of bad blocks in plurality of dies, as taught by CHO; to illustrate CH1 is coupled to plurality of dies and CH2 is connected to plurality of dies. The combined system of Zhang – CHO allows bad block management for memory devices by making determination of bad blocks in plurality of dies where CH1 is coupled to plurality of dies and CH2 is connected to plurality of dies and calibration operation for data communication between a controller and a memory die as mentioned in paragraph [0039]. Therefore, the combination of Zhang - CHO improves reliability. See CHO, paragraph [0026].
Regarding claim 19, Zhang in view of CHO teaches bad block management for memory devices in claim 16. However, Zhang - CHO combination does not explicitly teach The memory system according to claim 16, wherein the controller is further configured to adjust scheduling of data input/output operations performed on the plurality of first memory dies and the plurality of second memory dies, based on a difference between a first sum of the first bad block sizes and the first inactive area sizes in the plurality of first memory dies and a second sum of the second bad block sizes and the second inactive area sizes in the plurality of second memory dies.
On the other hand, CHO which also relates to bad block management for memory devices teaches The memory system according to claim 16, wherein the controller is further configured to adjust scheduling of data input/output operations performed on the plurality of first memory dies and the plurality of second memory dies, based on a difference between a first sum of the first bad block sizes and the first inactive area sizes in the plurality of first memory dies and a second sum of the second bad block sizes and the second inactive area sizes in the plurality of second memory dies. (see Fig 7, paragraph [0138], illustrates controller 130 may selectively perform input/output operation and calibration based on error bits. In other words, controller is configured to perform input/output operation based on bad blocks which is valid for all dies)
Both Zhang and CHO relate to bad block management for memory devices (see Zhang, abstract, and see CHO, abstract, regarding bad block management for memory devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Zhang with CHO by incorporating
bad block management for memory devices by making determination of bad blocks in plurality of dies, as taught by CHO; to enable controller to selectively perform input/output operation and calibration based on error bits. The combined system of Zhang – CHO allows bad block management for memory devices by making determination of bad blocks in plurality of dies where controller to selectively perform input/output operation and calibration based on error bits and calibration operation for data communication between a controller and a memory die as mentioned in paragraph [0039]. Therefore, the combination of Zhang - CHO improves reliability. See CHO, paragraph [0026].
Claim(s) 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of CHO and further in view of SOHN.
Regarding claim 17, Zhang in view of CHO teaches bad block management for memory devices in claim 16. However, Zhang - CHO combination does not explicitly teach The memory system according to claim 16, wherein the controller is configured to: determine, as the first inactive areas, at least one cell string among a plurality of cell strings in at least one of the plurality of first memory dies; and determine, as the second inactive area, at least one cell string of a plurality of cell strings in at least one of the plurality of second memory dies
On the other hand, SOHN which also relates to bad block management for memory devices teaches The memory system according to claim 16, wherein the controller is configured to: determine, as the first inactive areas, at least one cell string among a plurality of cell strings in at least one of the plurality of first memory dies; and determine, as the second inactive area, at least one cell string of a plurality of cell strings in at least one of the plurality of second memory dies. (see Fig 1, paragraph [0032], illustrates bad block includes one or more rows and one bad row may include at least one bad cell which is valid for all dies)
Both Zhang, CHO and SOHN relate to bad block management for memory devices (see Zhang, abstract, see CHO, abstract, and see SOHN, abstract regarding bad block management for memory devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Zhang - CHO combination with SOHN by incorporating bad block management for memory devices by making determination of bad blocks in plurality of dies, as taught by SOHN; to illustrate bad block includes one or more rows and one bad row may include at least one bad cell which is valid for all dies. The combined system of Zhang - CHO - SOHN allows bad block management for memory devices by making determination of bad blocks in plurality of dies where bad block includes one or more rows and one bad row may include at least one bad cell which is valid for all dies providing a structure and functionality of bad block as mentioned in paragraph [0033]. Therefore, the combination of Zhang - CHO - SOHN improves performance. See SOHN, paragraph [0003].
Regarding claim 18, Zhang in view of CHO teaches bad block management for memory devices in claim 16. However, Zhang - CHO combination does not explicitly teach The memory system according to claim 16, wherein the controller is configured to: determine, as the first inactive areas, memory cells coupled to at least one word line among a plurality of word lines in at least one of the plurality of first memory dies; and determine, as the second inactive areas, memory cells coupled to at least one word line among a plurality of word lines in at least one of the plurality of second memory dies
On the other hand, SOHN which also relates to bad block management for memory devices teaches The memory system according to claim 16, wherein the controller is configured to: determine, as the first inactive areas, memory cells coupled to at least one word line among a plurality of word lines in at least one of the plurality of first memory dies; and determine, as the second inactive areas, memory cells coupled to at least one word line among a plurality of word lines in at least one of the plurality of second memory dies. (see Fig 1, paragraph [0032], illustrates bad block includes one or more rows or word lines and one bad word line may include at least one bad cell which is valid for all dies)
Both Zhang, CHO and SOHN relate to bad block management for memory devices (see Zhang, abstract, see CHO, abstract, and see SOHN, abstract regarding bad block management for memory devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Zhang - CHO combination with SOHN by incorporating bad block management for memory devices by making determination of bad blocks in plurality of dies, as taught by SOHN; to illustrate bad block includes one or more rows or word lines and one bad word line may include at least one bad cell which is valid for all dies. The combined system of Zhang - CHO - SOHN allows bad block management for memory devices by making determination of bad blocks in plurality of dies where bad block includes one or more rows or word lines and one bad word line may include at least one bad cell which is valid for all dies providing a structure and functionality of bad block as mentioned in paragraph [0033]. Therefore, the combination of Zhang - CHO - SOHN improves performance. See SOHN, paragraph [0003].
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of Zhang and further in view of Kryvaltsevich.
Regarding claim 20, Zhang in view of CHO teaches bad block management for memory devices in claim 19. However, Zhang - CHO combination does not explicitly teach The memory system according to claim 19, wherein the controller is further configured to adjust the scheduling of the data input/output operations by at least one of: adjusting throttling levels for the plurality of first or second memory dies; and adjusting a ratio of host write operations and garbage collection write operations performed on the plurality of first or second memory dies
On the other hand, Kryvaltsevich which also relates to bad block management for memory devices teaches The memory system according to claim 19, wherein the controller is further configured to adjust the scheduling of the data input/output operations by at least one of: adjusting throttling levels for the plurality of first or second memory dies; and adjusting a ratio of host write operations and garbage collection write operations performed on the plurality of first or second memory dies. (see Fig 14, paragraph [0161], illustrates in step 1406 calculating garbage collection and host ratio based on invalid of bad blocks for adjusting throttling parameters where host is involved in sending write commands which is valid for all dies)
Both Zhang, CHO and Kryvaltsevich relate to bad block management for memory devices (see Zhang, abstract, see CHO, abstract, and see Kryvaltsevich, abstract, regarding bad block management for memory devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Zhang - CHO combination with Kryvaltsevich by incorporating bad block management for memory devices by making determination of bad blocks in plurality of dies, as taught by Kryvaltsevich; to enable calculating garbage collection and host ratio based on invalid of bad blocks for adjusting throttling parameters where host is involved in sending write commands. The combined system of Zhang - CHO – Kryvaltsevich allows bad block management for memory devices by making determination of bad blocks in plurality of dies and calculating garbage collection and host ratio based on invalid of bad blocks for adjusting throttling parameters where host is involved in sending write commands and balanced throttling of the memory system as mentioned in paragraph [0032]. Therefore, the combination of Zhang - CHO - Kryvaltsevich improves performance consistency and stabilize the memory system. See Kryvaltsevich, paragraph [0036].
Response to Arguments
Applicant’s arguments filed on 01/02/2026 have been fully considered but they
are not persuasive.
Applicant’s first argument is claim 1 and 10 amendments mapping by primary reference KIM in page 13 of the response: KIM does not disclose "a controller configured to check a bad block occurring or found in at least one of the plural memory dies and adjust an inactive area size in the at least one of the plural memory dies based on the bad block to equal a sum of a bad block size and an inactive area size in the at least one of plural memory dies to another sum of a bad block size and an inactive area size in another memory die among the plural memory dies" as claimed in claim 1 and similarly claimed in claim 10
In summary, applicant argued that primary reference KIM does not teach amended limitations of claim 1 and 10. The amendment
necessitates adding another secondary reference SHIN in this regard. For further
clarification examiner cites portion from SHIN. Also, for applicant’s understanding
examiner would like to explain the teachings of SHIN and examiner’s interpretation in
more detail here. See Fig 1, paragraph [0110], SHIN teaches controller 130 may decide bad blocks among the memory blocks included in each of the super blocks, and also see Fig 6B and 7, paragraph [0112], SHIN teaches generate information on the bad blocks and also controller 130 may determine a reference value RV for selecting a victim block using valid page and bad block information at step 730 reflecting weight of bad blocks and inactive area and weight can be adjusted based on number of bad blocks included. The cited portion clearly teaches controller 130 may decide bad blocks among the memory blocks and controller may also determine a reference value RV for selecting a victim block using valid page and bad block information reflecting weight of bad blocks and inactive area and weight can be adjusted based on number of bad blocks included. Thus, the rejection of amended claims 1 and 10 is maintained.
Applicant’s second argument is claim 16 mapping by reference Zhang in page 15 of the response: Zhang's predetermined threshold is used for performing garbage collection GC, not bad block management. Even if Zhang's controller 300 adjusts the predetermined threshold, scheduling the garbage collection GC could be changed to secure a free block (e.g., an available block for storing new data). Zhang's predetermined threshold is NOT relevant to the claimed bad block size or the claimed inactive area size. Accordingly, CHO and Zhang, either individually or in combination, do not disclose "wherein the controller is configured to: adjust first inactive area sizes in the plurality of first memory dies based on first bad block sizes in the plurality of first memory dies; and adjust second inactive area sizes in the plurality of second memory dies based on second bad block sizes occurring or found in the plurality of second memory dies" as claimed in claim 16
In summary, applicant argued that reference Zhang does not teach controller adjusting inactive area of dies based on bad block sizes. Examiner respectfully disagrees. For further clarification examiner cites portion from Zhang. Also, for applicant’s understanding examiner would like to explain the teachings of Zhang and examiner’s interpretation in more detail here. See Fig 3A and 5, paragraph [0070] and [0082], Zhang teaches in GC method 500 controller 300 may determine total number of expected used or inactive spaces and may adjust GC triggering based on foreground tasks of bad blocks management. In other words, controller can adjust used or inactive areas based on foreground tasks needs or actual sizes including bad blocks. Thus, the rejection of claim 16 is maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.K.C./Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132