DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant’s arguments with respect to the claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 9-10, 12-15, 17-18, & 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KR20150096909A hereafter referred to as Moon.
In regards to claim 1, Moon discloses
A multilayer ceramic capacitor comprising:
an element body (110 – fig. 1; [0032]) portion including a first principal surface and a second principal surface opposite to each other in a thickness direction, a first side surface and a second side surface opposite to each other in a width direction, and a first end surface and a second end surface opposite to each other in a length direction (fig. 1-3), and including a plurality of dielectric layers (111 – fig. 2-3; [0032]) and a plurality of internal electrode layers (121-122 – fig. 2-3; [0032]) stacked in the thickness direction;
a first external electrode (131 – fig. 2; [0032]) on the first end surface; and
a second external electrode (132 – fig. 2; [0032]) on the second end surface; wherein
the plurality of internal electrode layers include a plurality of first internal electrode layers (121 – fig. 2) connected to the first external electrode, and a plurality of second internal electrode layers (122 – fig. 2) connected to the second external electrode;
each of the plurality of internal electrode layers includes an opposing portion opposed, in the thickness direction, to an adjacent internal electrode layer of the plurality of internal electrode layers (seen in fig. 2-3);
a third internal electrode layer (121’ – fig. 2; [0032]) is located in a space between the opposing portion and at least one of the first side surface and the second side surface, in the width direction, and
a thickness of the third internal electrode layer in the thickness direction is smaller than a thickness of the plurality of internal electrode layers in the thickness direction (fig. 2; [0064]).
In regards to claim 2, Moon discloses
The multilayer ceramic capacitor according to claim 1, wherein a fourth internal electrode layer (121’ & 122’ – fig. 3; [0064]) is located in at least one of a space between the first internal electrode layer and the second end surface, and a space between the second internal electrode layer and the first end surface, in the length direction.
In regards to claim 3, Moon discloses
The multilayer ceramic capacitor according to claim 2, wherein the fourth internal electrode layer located in the space between the first internal electrode layer and the second end surface in the length direction is located at a same or substantially a same position in the thickness direction as the first internal electrode layer (fig. 3).
In regards to claim 4, Moon discloses
The multilayer ceramic capacitor according to claim 2, wherein Ni is diffused in a peripheral region of the fourth internal electrode layer, the peripheral region excluding a region extending from the fourth internal electrode layer by about one-third of a thickness of the fourth internal electrode layer ([0049] & [0095] – it is noted that when the electrode is formed of Ni, Ni will diffuse to a peripheral region during sintering).
In regards to claim 5, Moon discloses
The multilayer ceramic capacitor according to claim 2, wherein a grain size in a peripheral region of the fourth internal electrode layer is smaller than a grain size in a vicinity of an outermost surface of the element body portion ([0049] & [0095] – it is noted that when the electrode is formed of Ni, Ni will diffuse to a peripheral region during sintering and said diffusion of Ni in said region will inhibit grain growth (i.e. smaller grains will be present)).
In regards to claim 6, Moon discloses
The multilayer ceramic capacitor according to claim 1, wherein Ni is diffused in a peripheral region of the third internal electrode layer, the peripheral region excluding a region extending from the third internal electrode layer by about one-third of a thickness of the third internal electrode layer ([0049] & [0095] – it is noted that when the electrode is formed of Ni, Ni will diffuse to a peripheral region during sintering).
In regards to claim 7, Moon discloses
The multilayer ceramic capacitor according to claim 1, wherein the third internal electrode layer is located at a same or substantially a same position in the thickness direction as the opposing portion (fig. 2).
In regards to claim 9, Moon discloses
The multilayer ceramic capacitor according to claim 1, wherein each of the first and second external electrodes includes a base electrode layer ([0053]) and a plating layer ([0054]) on the base electrode layer; and
the thickness of the third internal electrode layer in the thickness direction is approximately one-third or more and approximately one-half or less than the thickness of the plurality of internal electrode layers in the thickness direction ([0091-0094]).
In regards to claim 10, Moon discloses
The multilayer ceramic capacitor according to claim 9, wherein the base electrode layer includes a baked layer including glass and metal ([0053]).
In regards to claim 12, Moon discloses
The multilayer ceramic capacitor according to claim 10, wherein the metal includes Ni, Cu, Ag, Pd, or Au, or an alloy including at least one of Ni, Cu, Ag, Pd, or Au ([0098]).
In regards to claim 13, Moon discloses
A multilayer ceramic capacitor comprising:
an element body (110 – fig. 1; [0032]) portion including a first principal surface and a second principal surface opposite to each other in a thickness direction, a first side surface and a second side surface opposite to each other in a width direction, and a first end surface and a second end surface opposite to each other in a length direction (fig. 1-3), and including a plurality of dielectric layers (111 – fig. 2-3; [0032]) and a plurality of internal electrode layers (121-122 – fig. 2-3; [0032]) stacked in the thickness direction;
a first external electrode (131 – fig. 2; [0032]) on the first end surface; and
a second external electrode (132 – fig. 2; [0032]) on the second end surface; wherein
the plurality of internal electrode layers include a plurality of first internal electrode layers (121 – fig. 2) connected to the first external electrode, and a plurality of second internal electrode layers (122 – fig. 2) connected to the second external electrode;
each of the plurality of internal electrode layers includes an opposing portion opposed, in the thickness direction, to an adjacent internal electrode layer of the plurality of internal electrode layers (seen in fig. 2-3);
a fourth internal electrode layer (121’ – fig. 2; [0032]) is located in at least one of a space between the first internal electrode layer and the second end surface, and a space between the second internal electrode layer and the first end surface, in the length direction,
a thickness of the fourth internal electrode layer in the thickness direction is smaller than a thickness of the plurality of internal electrode layers in the thickness direction (fig. 2; [0064]).
In regards to claim 14, Moon discloses
The multilayer ceramic capacitor according to claim 13, wherein the fourth internal electrode layer located in the space between the first internal electrode layer and the second end surface in the length direction is located at a same or substantially a same position in the thickness direction as the first internal electrode layer (fig. 3).
In regards to claim 15, Moon discloses
The multilayer ceramic capacitor according to claim 13, wherein Ni is diffused in a peripheral region of the fourth internal electrode layer, the peripheral region excluding a region extending from the fourth internal electrode layer by about one-third of a thickness of the fourth internal electrode layer ([0049] & [0095] – it is noted that when the electrode is formed of Ni, Ni will diffuse to a peripheral region during sintering).
In regards to claim 17, Moon discloses
The multilayer ceramic capacitor according to claim 1, wherein each of the first and second external electrodes includes a base electrode layer ([0053]) and a plating layer ([0054]) on the base electrode layer; and
the thickness of the fourth internal electrode layer in the thickness direction is approximately one-third or more and approximately one-half or less than the thickness of the plurality of internal electrode layers in the thickness direction ([0091-0094]).
In regards to claim 18, Moon discloses
The multilayer ceramic capacitor according to claim 9, wherein the base electrode layer includes a baked layer including glass and metal ([0053]).
In regards to claim 20, Moon discloses
The multilayer ceramic capacitor according to claim 10, wherein the metal includes Ni, Cu, Ag, Pd, or Au, or an alloy including at least one of Ni, Cu, Ag, Pd, or Au ([0098]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 8 & 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moon in view of JP2002299145A hereafter referred to as Koizumi.
In regards to claim 8,
Moon discloses wherein a grain size in a peripheral region of the third internal electrode layer is smaller than a grain size in a vicinity of an outermost surface of the element body portion ([0049] & [0095] – it is noted that when the electrode is formed of Ni, Ni will diffuse to a peripheral region during sintering). Moon fails to disclose the grain size in the peripheral region of the third internal electrode layer is about 0.02 µm or more and about 0.1 µm or less.
Koizumi discloses the grain size in the peripheral region of the third internal electrode layer is about 0.02 µm or more and about 0.1 µm or less ([0028] & table 1).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the grains around the peripheral of the internal electrodes of Moon to have a size as taught by Koizumi to obtain a capacitor whose withstand voltage can be improved by a method where the thickness of an insulator layer is made uniform and its surface roughness (Ra) is reduced, even if the insulator layer is made thin.
In regards to claim 16, Moon discloses
A multilayer ceramic capacitor comprising:
an element body (110 – fig. 1; [0032]) portion including a first principal surface and a second principal surface opposite to each other in a thickness direction, a first side surface and a second side surface opposite to each other in a width direction, and a first end surface and a second end surface opposite to each other in a length direction (fig. 1-3), and including a plurality of dielectric layers (111 – fig. 2-3; [0032]) and a plurality of internal electrode layers (121-122 – fig. 2-3; [0032]) stacked in the thickness direction;
a first external electrode (131 – fig. 2; [0032]) on the first end surface; and
a second external electrode (132 – fig. 2; [0032]) on the second end surface;
wherein the plurality of internal electrode layers include a plurality of first internal electrode layers (121 – fig. 2) connected to the first external electrode, and a plurality of second internal electrode layers (122 – fig. 2) connected to the second external electrode;
a fourth internal electrode layer (121’ & 122’ – fig. 2; [0032]) is located in at least one of a space between the first internal electrode layer and the second end surface, and a space between the second internal electrode layer and the first end surface, in the length direction;
a grain size in a peripheral region of the fourth internal electrode layer is smaller than a grain size in a vicinity of an outermost surface of the element body portion ([0049] & [0095] – it is noted that when the electrode is formed of Ni, Ni will diffuse to a peripheral region during sintering). Moon fails to disclose the grain size in the peripheral region of the fourth internal electrode layer is about 0.02 µm or more and about 0.1 µm or less.
Koizumi discloses the grain size in the peripheral region of the fourth internal electrode layer is about 0.02 µm or more and about 0.1 µm or less ([0028] & table 1).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the grains around the peripheral of the internal electrodes of Moon to have a size as taught by Koizumi to obtain a capacitor whose withstand voltage can be improved by a method where the thickness of an insulator layer is made uniform and its surface roughness (Ra) is reduced, even if the insulator layer is made thin.
Claim(s) 11 & 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moon in view of Kisumi et al. (US 2014/0347783).
In regards to claim 11 & 19,
Moon fails to disclose wherein the glass includes Si.
Kisumi ‘783 discloses wherein the glass includes Si (abstract)
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the external electrodes of Moon using the conductive paste of Kisumi ‘778 to obtain electrodes which simultaneously have good humidity/plating solution resistance and plating adhesion properties without causing any structural defects.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIMOTHY J DOLE can be reached at (571)272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David M Sinclair/Primary Examiner, Art Unit 2847
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