DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are: “control logic” and “addressing logic” in claims 12, 15, and 16.
Because these claim limitations are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. Support for these limitations can be found in figure 6, paragraphs [0044], [0047]-[0048], [0051], [0056], [0068], and [0070] of the applicant’s specification.
If applicant does not intend to have these limitations interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitations to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitations recite sufficient structure to perform the claimed function so as to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 12-20 recite an MxN array. However, the ranges M and N are not properly defined in the claims, thus making it unclear as to what the range of M and N are. For the purpose of proper examination of the claims, the examiner is interpreting M and N as numbers greater than or equal to one (i.e., M≥1, N≥1).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 of U.S. Patent No. 12,130,378.
Application No. 18/904,286
U.S. Patent No. 12,130,378
Claim 1. A device comprising:
a first buffer that includes an input and an output;
a first butterfly circuit that includes: a first input coupled to receive a set of sample values; a second input coupled to the output of the first buffer;
a first output coupled to the input of the first buffer; and
a second output;
and a second buffer that includes an input and an output;
a second butterfly circuit that includes: a first input; a second input coupled to the output of the second buffer; a first output coupled to the input of the second buffer;
and
a second output, wherein each of the first butterfly circuit and the second butterfly circuit is configured to operate in a first mode and a second mode, in which operating in the first mode includes providing, at the first output, a value at the first input, and providing, at the second output, a value at the second input, and in which operating in the second mode includes providing, at the first output, a difference of a value at the first input and a value at the second input, and providing, at the second output, a sum of a value at the first input and a value at the second input.
Claim 1. A device comprising:
a first pipeline stage that includes: a first buffer that includes an input and an output;
a first butterfly circuit that includes: a first input coupled to receive a set of sample values; a second input coupled to the output of the first buffer;
a first output coupled to the input of the first buffer; and
a second output;
and a first multiplier that includes: an input coupled to the second output of the first butterfly circuit; and
an output; and
a second pipeline stage that includes: a second buffer that includes an input and an output; a second butterfly circuit that includes: a first input coupled to the output of the first multiplier; a second input coupled to the output of the second buffer;
a first output coupled to the input of the second buffer; and
a second output; and a second multiplier that includes: an input coupled to the second output of the second butterfly circuit; and an output, wherein at least one of the first butterfly circuit and the second butterfly circuit is configured to operate in a first mode and a second mode, in which operating in the first mode includes providing, at the first output, a value at the first input, and providing, at the second output, a value at the second input, and in which operating in the second mode includes providing, at the first output, a difference of a value at the first input and a value at the second input, and providing, at the second output, a sum of a value at the first input and a value at the second input.
Claim 2
Claim 2
Claim 3
Claim 1
Claim 4
Claim 1
Claim 5
Claim 4
Claim 6
Claim 5
Claim 7
Claim 5
Claim 8
Claim 7
Claim 9
Claim 8
Claim 10
Claim 9
Claim 11
Claim 10
Although the claims at issue are not identical, they are not patentably distinct from each other because patent claims include all the limitations of the instant application claims, respectively (see table above showing the patent claims that correspond to the instant application claims). The patent claims also include additional limitations. Hence, the instant application claims are generic to the species of invention covered by the respective patent claims. As such, the instant application claims are anticipated by the patent claims and are therefore not patentably distinct therefrom (See Eli Lilly and Co. v. Barr Laboratories Inc., 58 USPQ2D 1869, " a later genus claim limitation is anticipated by, and therefore not patentably distinct from, an earlier species claim", In re Goodman, 29 USPQ2d 2010, "Thus, the generic invention is 'anticipated' by the species of the patented invention" and the instant “application claims are generic to species of invention covered by the patent claim, and since without terminal disclaimer, extant species claim preclude issuance of generic application claims”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mattingly US 10,984,072 discloses a fast Fourier transform (FFT) circuit with an integrated half-bin offset for performing both an FFT and a half-bin offset on an input signal. The FFT circuit is configured to receive input samples of the input signal and generate output signals via butterfly circuits and one or more twiddle stage multiplier circuits of the FFT circuit, wherein the output signals are signals representing a frequency spectrum of the input signal. The one or more butterfly circuits of the butterfly circuits are configured to implement a first portion of both the half-bin offset and the FFT by integrating a first set of computations for both the half-bin offset and the FFT within the one or more of the butterfly circuits. At least one of the one or more twiddle stage multiplier circuits is configured to implement a second portion of both the half-bin offset and the FFT by integrating a second set of computations of both the half-bin offset and the FFT within the twiddle stage multiplier circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to OLUMIDE T AJIBADE AKONAI whose telephone number is (571)272-6496. The examiner can normally be reached Monday-Friday 8AM-4PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Resha Desai can be reached at 571-270-7792. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/OLUMIDE AJIBADE AKONAI/Primary Examiner, Art Unit 3648
Prosecution Insights