DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/02/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 14 is/are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Nakada et al. (US 20210226620).
Nakada et al. disclose a power switching circuit configured for coupling with a gate driver circuit, the power switching circuit comprising: a transistor (14) including: a first terminal configured for coupling with a load (D); a second terminal (S) configured for coupling with an inductance (L2); and a control terminal (G) configured for coupling with the gate driver circuit (13); a feedback circuit (11) including at least one resistive element (R2) and at least one capacitive element (Ca), wherein the feedback circuit is configured for coupling with the gate driver circuit (through the controller 12).
Allowable Subject Matter
Claims 1-13 and 17-20 are allowed.
Claims 15 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 1-10 and 13; prior art fails to disclose or fairly suggest, inter alia, a power switching circuit comprising: a feedback circuit coupled with the switch and including at least one resistive element, wherein the switch is configured for coupling, based on a control signal, the feedback circuit with the gate driver circuit.
Claims 11 and 12; prior art fails to disclose or fairly suggest, inter alia, a power switching circuit comprising: a pair of Zener diodes, connected in opposition; and a feedback circuit coupled with the pair of Zener diodes and including at least one resistive element, wherein the feedback circuit is coupled with the gate driver circuit.
Claim 15 and 16; prior art fails to disclose or fairly suggest, inter alia, the at least one resistive element and the at least one capacitive element includes: a first resistive element coupled in series with a first capacitive element; and a second resistive element coupled in parallel with the first resistive element and the first capacitive element.
Claims 17-20 prior art fails to disclose or fairly suggest, inter alia, a power switching circuit comprising: a bidirectional switch including a first transistor and a second transistor; a second gate driver circuit coupled with the first transistor and the second transistor, second gate driver circuit configured for generating control signals to the first transistor and the second transistor; and a feedback circuit coupled with the bidirectional switch and including at least one resistive element, wherein the bidirectional switch is configured for coupling, based on the control signals, the feedback circuit with the first gate driver circuit.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 9948290 Mari Curbelo et al. disclose a gate driver circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GARY L LAXTON whose telephone number is (571)272-2079. The examiner can normally be reached Monday-Friday, 8 am-4 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached at 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GARY L LAXTON/Primary Examiner, Art Unit 2838 6/23/2026
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