Last updated: July 17, 2026

Application No. 18/904,757

STRATEGIC MEMORY CELL RELIABILITY MANAGEMENT

Non-Final OA

Filed

Oct 02, 2024

Priority

Jul 19, 2021 — provisional 63/223,219 +1 more

Examiner

DINH, MINH D

Art Unit

2827

Tech Center

2800 — Semiconductors & Electrical Systems

Assignee

Micron Technology Inc.

OA Round

1 (Non-Final)

Interview Optional

— +0.8% interview lift. Interview already conducted in this application's prosecution history. This examiner has a 96% grant rate with +0.8% interview lift. Since an interview has already been tried, recommend written response with narrowed claims based on precedent claim evolution patterns.

Based on 395 resolved cases, 2023–2026

Examiner Intelligence

DINH, MINH D View full profile →

Grants 96% — above average

Career Allowance Rate

381 granted / 395 resolved

+28.5% vs TC avg

Minimal +1% lift

Without

With

+0.8%

Interview Lift

resolved cases with interview

Fast prosecutor

1y 7m

Avg Prosecution

3 currently pending

Career history

403

Total Applications

across all art units

Statute-Specific Performance

§101

0.4%

-39.6% vs TC avg

§103

67.1%

+27.1% vs TC avg

§102

11.8%

-28.2% vs TC avg

§112

5.3%

-34.7% vs TC avg

Black line = Tech Center average estimate • Based on career data from 395 resolved cases

Prosecution Timeline

Oct 02, 2024

Application Filed

Apr 02, 2026

Non-Final Rejection mailed

Apr 14, 2026

Interview Requested

Apr 24, 2026

Applicant Interview (Telephonic)

Apr 24, 2026

Examiner Interview Summary

Precedent Cases

Applications granted by this same examiner with similar technology

18/815,547

Patent 12682968

METHOD OF OPERATING A THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE

1y 10m to grant Granted Jul 14, 2026

18/420,867

Patent 12676206

MEMORY DEVICE FOR CONTROLLING A DATA OUTPUT ORDER AND AN OPERATING METHOD THEREOF

2y 5m to grant Granted Jul 07, 2026

18/793,177

Patent 12666879

VARIABLE RESISTANCE MEMORY DEVICE

1y 10m to grant Granted Jun 23, 2026

18/390,423

Patent 12658277

ENHANCED ERROR CORRECTION CODE FOR ERROR DETECTION AND CORRECTION IN MULTI-LEVEL CELL-BASED MEMORY DEVICES

2y 5m to grant Granted Jun 16, 2026

18/533,922

Patent 12646539

POWER-AWARE MEMORY CONTROL

2y 5m to grant Granted Jun 02, 2026

Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.

Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2

Expected OA Rounds

96%

Grant Probability

97%

With Interview (+0.8%)

1y 7m (~0m remaining)

Median Time to Grant

Low

PTA Risk

Based on 395 resolved cases by this examiner. Grant probability derived from career allowance rate.