DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Preliminary Amendment
Acknowledgement is made of applicant’s Preliminary Amendment, filed October 02, 2024. The changes and remarks disclosed therein were considered.
Claims 1-20 are cancelled. Claims 21-38 are pending. Claim 21 and claim 32 are independent.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file (KR10-2020-0185741 Republic of Korea 12/29/2020).
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statements (IDS) filed on October 02, 2024; May 07, 2025; November 07, 202; and July 20, 2026. These IDSs have been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claim 24 objected to because of the following informalities: The phrase "to skip to write" is unclear and appears to be erroneous. It is unclear whether the applicant intended to recite "to not write" or other language. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21-38 are reject on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-20 of U.S Patent No. 12,136,463 B2 (‘463). Although the conflicting claims are not identical, they are not patentably distinct from each other because the instant application claims are obvious variants of the ‘463 claims.
Application Claim 21 is anticipated by U.S. Patent 12136463, claims 1 and 3. Application Claim 21 is also anticipated by U.S. Patent 11615861, claims 1 and 3.
Application Claim 22 is anticipated by U.S. Patent 12136463, claim 1. Application Claim 22 is also anticipated by U.S. Patent 11615861, claim 1.
Application Claim 23 is anticipated by U.S. Patent 12136463, claims 1 and 3. Application Claim 23 is also anticipated by U.S. Patent 11615861, claims 1 and 3.
For purposes of this examination, “skip to write back” is interpreted as having the same scope as “not write back”. Therefore, Application Claim 24 is anticipated by U.S. Patent 12136463, claims 1 and 4. Application Claim 24 is also anticipated by U.S. Patent 11615861, claims 1 and 4.
Application Claim 25 is anticipated by U.S. Patent 12136463, claims 1 and 2. Application Claim 25 is also anticipated by U.S. Patent 11615861, claims 1 and 2.
Application Claim 26 would have been obvious over the subject matter claimed in U.S. Patent 12136463, claims 1, 5, and 11. Application Claim 26 would have been obvious over the subject matter claimed in U.S. Patent 11615861, claims 1 and 11.
Application Claim 27 would have been obvious over the subject matter claimed in U.S. Patent 12136463, claims 1, 5, and 6. Application Claim 27 would have been obvious over the subject matter claimed in U.S. Patent 11615861, claims 1 and 16.
Application Claim 28 would have been obvious over the subject matter claimed in U.S. Patent 12136463, claims 1 and 7. Application Claim 28 would have been obvious over the subject matter claimed in U.S. Patent 11615861, claims 1 and 5.
Application Claim 29 would have been obvious over the subject matter claimed in U.S. Patent 12136463, claims 1, 7 and 8. Application Claim 29 would have been obvious over the subject matter claimed in U.S. Patent 11615861, claims 1, 5, and 6.
Application Claim 30 would have been obvious over the subject matter claimed in U.S. Patent 12136463, claims 1, 7 and 9. Application Claim 30 would have been obvious over the subject matter claimed in U.S. Patent 11615861, claims 1, 5, and 7.
Application Claim 31 would have been obvious over the subject matter claimed in U.S. Patent 12136463, claims 1 and 11. Application Claim 31 would have been obvious over the subject matter claimed in U.S. Patent 11615861, claims 1 and 11.
Application Claim 32 would have been obvious over the subject matter claimed in U.S. Patent 12136463, claims 13 and 16. Application Claim 32 would have been obvious over the subject matter claimed in U.S. Patent 11615861, claim 18.
Application Claim 33 would have been obvious over the subject matter claimed in U.S. Patent 12136463, claims 13 and 15. Application Claim 33 would have been obvious over the subject matter claimed in U.S. Patent 11615861, claim 18.
Application Claim 34 is anticipated by U.S. Patent 12136463, claims 13 and 14.
Application Claim 35 would have been obvious over the subject matter claimed in U.S. Patent 11615861, claims 18 and 19.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
This application includes one or more claim limitations that use recite functional language but are not interpreted under 35 U.S.C. 112(f). Such claim limitation(s) is/are:
Apparatus claims 21-27’s “error correction code circuit”, “control logic circuit”, “scrubbing control circuit” that is “configured to” perform recited operations.
Because these claim limitation(s) are not being interpreted under 35 U.S.C. 112(f), they are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21-22, 25-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cha et al. (US 20190371391 A1; hereinafter “Cha”).
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Regarding independent claim 21, Cha, for example in Figs. 1 -24, discloses a semiconductor memory device (see Examiner’s Markup Cha Fig. 1, e.g. SEMICONDUCTOR MEMORY DEVICE 200; see also other related Figs. 2-24) comprising:
a memory cell array (see Examiner’s Markup Cha Fig. 1, e.g. MCA 300; see also other related Figs. 2-24) including a plurality of memory cell rows (see Examiner’s Markup Cha Fig. 2, e.g. WL1, WLm; see also other related Figs. 3-24), each memory cell row of the plurality of memory cell rows including memory cells (see US 20190371391 A1, Fig. 3, e.g. MC) coupled to a plurality of bit-lines (see US 20190371391 A1, Fig. 3, e.g. BTL1, BTLn);
an error correction code (ECC) circuit (see Examiner’s Markup Cha Fig. 1; e.g. ECC ENGINE 400, see also other related Figs. 2-24) configured to detect one or more errors in codewords stored in a first memory cell row of the plurality of memory cell rows to count a number of error occurrences in the first memory cell row (see for example in Fig.1 and other related Figs. 2-24; paragraph [0004+]); and
a control logic circuit (see Examiner’s Markup Cha Fig. 1, e.g. CONTROL LOGIC CIRCUIT 210; see also other related Figs. 2-24) configured to compare the counted number of error occurrences with a threshold value (via Fig. 1, ECC ENGINE 400’s function; see also other related Figs. 2-24),
wherein the ECC circuit is configured to write back one or more corrected codewords in the first memory cell row in response to a result of the comparison between the counted number of error occurrences and the threshold value (see for example in Figs. 1, 9; see also other related Figs. 2-8, 10-24; see paragraph [0004]).
The structure disclosed in the prior art (Cha) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 22, Cha, for example in Figs. 1-24, discloses a semiconductor memory device (see Examiner’s Markup Cha Fig. 1, e.g. SEMICONDUCTOR MEMORY DEVICE 200; see also other related Figs. 2-24), further comprising: a scrubbing control circuit (see Examiner’s Markup Cha Fig. 1, e.g. CONTROL LOGIC CIRCUIT 500; see also other related Figs. 2-24) configured to generate at least one scrubbing address associated with the first memory cell row in response to the counted number of error occurrences being greater than or equal to 1 (see for example in Figs. 1, 9; see also other related Figs. 2-8, 10-24; see paragraph [0004]).
The structure in of the prior art (Cha) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 25, Cha, for example in Figs. 1-24, discloses a semiconductor memory device of claim 21 (see Examiner’s Markup Cha Fig. 1, e.g. SEMICONDUCTOR MEMORY DEVICE 200; see also other related Figs. 2-24), further comprising: an ECC engine (see Examiner’s Markup Cha Fig. 1, e.g. ECC ENGINE 400; see also other related Figs. 2-24) configured to detect one or more errors in codewords stored in a second memory cell row of the plurality of memory cell rows to count a number of error occurrences in the second memory cell row in response to the number of error occurrences in the first memory cell row being a zero, the second memory cell row being different from the first memory cell row (see for example in Figs. 1, 9; see also other related Figs. 2-8, 10-24; see paragraph [0005]).
The structure in of the prior art (Cha) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 26, Cha, for example in Figs. 1 -24, discloses a semiconductor memory device of claim 21 (see Examiner’s Markup Cha Fig. 1, e.g. SEMICONDUCTOR MEMORY DEVICE 200; see also other related Figs. 2-24), further comprising a control logic circuit (see Examiner’s Markup Cha Fig. 1, e.g. CONTROL LOGIC CIRCUIT 210; see also other related Figs. 2-24) configured to control the ECC circuit to perform a row fault detection operation to selectively store a row address of the first memory cell row in a fault address register as a row fault address based on the number of error occurrences in the first memory cell row.
The structure in of the prior art (Cha) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 23-24, 31-36, and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Cha (US 20190371391 A1) in view of Parkinson et al. (US 20190221273 A1; hereinafter "Parkinson").
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Regarding claim 23, Cha and Parkinson, as combined, discloses wherein the control logic circuit (see Examiner’s Markup Cha Fig. 2, e.g. CONTROL LOGIC CIRCUIT 210; see also other related Figs. 1, 3-24) is configured to write back the one or more corrected codewords in the first memory cell row in response to the number of error occurrences being greater than zero (see for example in Figs. 1, 9; see also other related Figs. 2-8, 10-24; see paragraph [0004]).
However, Cha is silent with respect to limiting write-back of corrected codewords when the counted number of error occurrences is smaller than the threshold value.
Parkinson teaches that the error metric may comprise “a number of bit errors in the ECC codeword” (see US 20190221273 A1, claim 3), that the maintenance circuit rewrites data “in response to an error metric satisfying an error threshold” (see US 20190221273 A1, claim 1; see also paragraph [0129], and Examiner’s Markup Parkinson Figure 11, e.g. 1108).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Cha with the teachings of Parkinson such that the number of error occurrences are compared to a threshold value to determine whether corrected codewords should be written back during the scrubbing operation in order to reduce unnecessary write-back and improve memory reliability.
The structure in of the prior art (Cha and Parkinson) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 24, Cha and Parkinson, as combined, discloses wherein the control logic circuit (see Examiner’s Markup Cha Fig. 2, e.g. CONTROL LOGIC CIRCUIT 210; see also other related Figs. 1, 3-24) is configured to write back the one or more corrected codewords in the first memory cell row in response to the number of error occurrences.
However, Cha is silent with respect to not write back the one or more corrected codewords in the first memory cell row in response to the number of error occurrences being equal to or greater than the threshold value.
Parkinson teaches that the error metric may comprise “a number of bit errors in the ECC codeword” (see US 20190221273 A1, claim 3), that the maintenance circuit rewrites data “in response to an error metric satisfying an error threshold” (see US 20190221273 A1, claim 1; see also paragraph [0129], and Examiner’s Markup Parkinson Fig. 11, e.g. 1108). Thus, Parkinson teaches to not write back the one or more corrected codewords in the first memory cell row in response to the number of error occurrences being equal to or greater than the threshold value, as claimed.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Cha with the teachings of Parkinson such that the number of error occurrences are compared to a threshold value to determine whether corrected codewords should be written back during the scrubbing operation in order to reduce unnecessary write-back and improve memory reliability.
The structure in of the prior art (Cha and Parkinson) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 31, Cha and Parkinson, as combined, discloses a scrubbing control circuit (see Examiner’s Markup Cha Fig. 2, e.g. SCRUBBING CONTROL CIRCUIT 500; see also other related Figs. 1, 3-24) that outputs an error address (EADDR) or a victim address (VCT_ADDR) stored in an address storing table as a weak codeword address (WCADDR). The WCADDR includes a weak codeword row address (WCRA) and a weak codeword column address (WCCA), (see US 20190371391 A1, paragraph [0063]).
However, Cha is silent with respect to the mentioned action being in response to the number of error occurrences in the first memory cell row being greater than or equal to the threshold value.
Parkinson teaches determining an error metric, wherein the error metric may comprise “a number of bit errors in the ECC codeword” (see US 20190221273 A1, claim 3), that the maintenance circuit rewrites data “in response to an error metric satisfying an error threshold” (see US 20190221273 A1, claim 1; see also paragraph [0129], and Examiner’s Markup Parkinson Fig. 11, e.g. 1108). Thus, Parkinson teaches the use of applying threshold values to determine when to store error addresses.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Cha with the teachings of Parkinson such that the number of error occurrences are compared to a threshold value to determine whether corrected codewords should be written back during the scrubbing operation in order to reduce unnecessary write-back and improve memory reliability.
The structure in of the prior art (Cha and Parkinson) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding independent method claim 32, discloses “wherein: the row operations are refresh operations on the memory cell rows; the M column operations are scrubbing operations which are sequentially performed on M codewords included in the first memory cell row; and an error correction code (ECC) engine included in the semiconductor memory device is configured to perform the scrubbing operations by reading each of the M codewords, correcting at least one error bit in each of the M codewords, and writing back corrected each codeword in a memory location stored a corresponding each codeword” (see US 20190371391 A1, claim 19).
However, Cha is silent with respect to not writing back one or more corrected codewords in the first memory cell row based on the counted number of error occurrences being greater than or equal to a threshold value.
Parkinson discloses: “A method comprising: reading data from a region of a non-volatile memory; correcting errors in the read data; buffering the error corrected read data in response to the number of corrected errors satisfying an error threshold; and writing the buffered error corrected read data back to the same region of the non-volatile memory in response to receiving a refresh command at the non-volatile memory from a controller over a bus” (see US 20190221273 A1, claim 12; see also Examiner’s Markup Parkinson Fig. 11, e.g. 1108). Thus, Parkinson’s method teaches to not write back the one or more corrected codewords in the first memory cell row in response to the number of error occurrences being equal to or greater than the threshold value, as claimed.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Cha to control whether corrected codewords are written back based on comparison between the number of error occurrences and a threshold value, as taught by Parkinson, in order to selectively rewrite corrected data based on the detected error condition, thereby improving memory reliability while avoiding unnecessary rewrite operations.
Regarding claim 33, Cha and Parkinson, as combined, discloses further comprising: performing the scrubbing operation on the first memory cell row including writing back the one or more corrected codewords in the first memory cell row (see US 20190371391 A1, claim 19).
However, Cha is silent with respect to not writing back the one or more corrected codewords in the first memory cell row in response to the counted number of error occurrences being less than the threshold value and greater than zero.
Parkinson discloses: “A method comprising: reading data from a region of a non-volatile memory; correcting errors in the read data; buffering the error corrected read data in response to the number of corrected errors satisfying an error threshold; and writing the buffered error corrected read data back to the same region of the non-volatile memory in response to receiving a refresh command at the non-volatile memory from a controller over a bus” (see US 20190221273 A1, claim 12; see also Examiner’s Markup Parkinson Fig. 11, e.g. 1108). Thus, Parkinson’s method teaches to not write back the one or more corrected codewords in the first memory cell row in response to the number of error occurrences being equal to or greater than the threshold value, as claimed.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Cha to control whether corrected codewords are written back based on comparison between the number of error occurrences and a threshold value, as taught by Parkinson, in order to selectively rewrite corrected data based on the detected error condition, thereby improving memory reliability while avoiding unnecessary rewrite operations.
Regarding claim 34, Cha and Parkinson, as combined, discloses performing scrubbing operations on codewords in a selected memory cell row using an ECC engine. Cha further discloses reading each codeword, correcting at least one error bit, and writing back the corrected codeword (see US 20190371391 A1, claims 18 and 19).
However, Cha is silent with respect to detecting errors in codewords stored in a second memory cell row in response to the number of error occurrences in the first memory cell being zero, without performing the scrubbing operation on the first memory row.
Parkinson discloses reading data from a memory region, correcting errors in the read data, and buffering and writing back the corrected data only when the number of corrected errors satisfies an error threshold. Parkinson further discloses that the memory region may comprise an ECC codeword (see US20190221273 A1, claims 12 and 17).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cha’s sequential scrubbing method in view of Parkinson’s threshold-based corrective operation so that, when no errors are detected in the first memory cell row, the method proceeds to detect errors in a different memory cell row without performing an unnecessary write-back operation on the first memory cell row, thereby reducing unnecessary memory operations and improving scrubbing efficiency.
Regarding claim 35, Cha and Parkinson, as combined, discloses performing sequential scrubbing operations on codewords in memory cell rows using an ECC engine (see US 20190371391 A1, claims 18 and 19). Cha further discloses an error address or victim address stored in an address storing table and output as a weak codeword address, wherein the weak codeword address includes a weak codeword row address (see US 20190371391 A1, paragraph [0063]).
However, Cha is silent with respect to storing the row address of the first memory cell row as a row fault address in response to the number of error occurrences in the first memory cell row being greater than or equal to a threshold value.
Parkinson discloses reading data, correcting errors in the read data, and buffering the error-corrected data in response to the number of corrected errors satisfying an error threshold. Parkinson further discloses that the memory region may comprise an ECC codeword (see US 20190221273 A1, claims 12 and 17).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cha so that the row address associated with the detected errors is stored in Cha’s address storing table when the number of corrected errors satisfies the threshold taught by Parkinson, thereby retaining the addresses of memory rows exhibiting excessive errors for subsequent fault handling or maintenance.
Regarding claim 36, Cha discloses sequentially performing scrubbing operations on memory cell rows and storing an error address or victim address in an address storing table (see US 20190371391 A1, claims 18 and 19; see also paragraph [0063]).
However, Cha is silent with respect to comparing an access row address with each row fault address in a set of stored row fault addresses and performing the error-detection operation only when the access row address does not match a stored row fault address.
Parkinson discloses threshold-based buffering and rewriting of corrected ECC data (see US 20190221273 A1, claims 12 and 17).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cha’s scrubbing method with Parkinson’s threshold-based rewrite technique to improve memory reliability while reducing unnecessary write-back operations.
Regarding claim 38, Cha and Parkinson, as combined, discloses wherein the threshold value is 2 (implied that is preventing error bits from being accumulated; see paragraph [0007+] of Cha, as discussed above).
Claims 27 and 37 are rejected under 35 U.S.C. 103 as being unpatentable over Cha (US 20190371391 A1) in view of Parkinson et al. (US 20190221273 A1; hereinafter "Parkinson") and further in view of Lee et al. (US 11989106 B2; hereinafter "Lee").
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Regarding claim 27, Cha and Parkinson, as combined, disclose a control logic circuit (see Examiner’s Markup Cha Fig. 1, e.g. CONTROL LOGIC CIRCUIT 210; see also other related Figs. 2-24).
However, Cha and Parkinson are silent with respect to the control logic circuit performing a soft post-package repair (Soft PPR) on a memory cell row corresponding to the row fault address by storing data stored in the memory cell row corresponding to the row fault address in a redundancy region of the memory cell array.
Lee discloses an internal controller (see Examiner’s Markup Lee Fig. 3, e.g. CONTROLLER 350) that executes a post-package repair (PPR) mode by transferring data contents from a failed memory row (see Examiner’s Markup Lee Fig. 3, e.g. ROWS 342) to an internal scratchpad memory (see Examiner’s Markup Lee Fig. 3, e.g. INTERNAL SCRATCHPAD 334); and thereafter transferring the data to a spare memory row (see Examiner’s Markup Lee Fig. 3, e.g. SPARES 344; see also US 11989106 B2, claim 1). Lee further teaches that the PPR mode comprises a Soft Post-Package Repair (SPPR) mode (see US 11989106 B2, claim 2). Thus, Lee teaches performing Soft PPR by transferring data stored in a failed memory row to a spare memory row, which is a redundancy region of the memory array.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Cha and Parkinson with the teachings of Lee to modify Cha’s control logic circuit to perform Soft PPR operation taught by Lee in order to improve memory reliability and preserve data during repair of defective memory rows using known Soft PPR techniques.
The structure in of the prior art (Cha, Parkinson and Lee) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 37, Cha and Parkinson, as combined, discloses performing sequential scrubbing operations on memory cell rows, wherein an ECC engine reads codewords, corrects one or more error bits, and writes back corrected codewords (see US 20190371391 A1, claims 18 and 19).
However, Cha and Parkinson are silent with respect to storing data associated with a row fault address in a redundancy region.
Lee discloses storing data associated with a faulty memory row in a redundancy region and remapping subsequent accesses to a redundant memory row (Soft PPR).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the methods of Cha and Parkinson, with the methods of Lee, to store data associated with a row fault address in a redundancy region as taught by Lee, thereby improving memory reliability by allowing data associated with faulty memory rows to be preserved and accessed through redundant memory rows.
Allowable Subject Matter
Claims 28-30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, if corrected to overcome the objections/rejections set forth above and a terminal disclaimer is filed.
Conclusion
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/KATHY KIEU NGUYEN/Examiner, Art Unit 2825
/THA-O H BUI/ Primary Examiner, Art Unit 2825
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