DETAILED ACTION
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claims because the examined application claim is either anticipated by, or would have been obvious over, the reference claims.
Independent claims 1, 12 and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 11,243,896. Although the claims at issue are not identical, they are not patentably distinct from each other because present application merely claims a broader scope of the same communication interface operating at first and second speeds as in the ‘896 patent.
All features of claims 1, 12 and 19 are able to found directly from the claims 1-19 in the ‘896 patent. Dependent claims are also similarly recited to the ‘896 patent; thus they are rejected for the same reason as ser forth above.
Independent claims 1, 12 and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 of U.S. Patent No. 12,111,777. Although the claims at issue are not identical, they are not patentably distinct from each other because present application merely claims a broader scope of the same communication interface operating at first and second speeds as in the ‘777 patent.
All features of claims 1, 12 and 19 are able to found directly from the claims 1-7 in the ‘777 patent. Dependent claims are also substantially similar to the ‘777 patent; thus they are rejected for the same reason as ser forth above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Olarig (US 11,018,444).
Referring to claims 1, 12 and 19, Olarig discloses a device (fig. 1, device 100), comprising:
memory cells (figs. 3A/3B, NAND SSD 314/316/334);
a communication interface (fig. 3A, U.2 interface 312);
an integrated circuit package (fig. 3A, NVMeoF device 300) to enclose the memory cells and the communication interface; and
a plurality of connectors (fig. 3A, Ethernet 304/306/308/310 of U.2 interface connector 312; fig. 3B, PCIe/Ethernet 336/338) coupled to the communication interface to provide connections from the communication interface to outside of the integrated circuit package (fig. 3, Ethernet ports provide connections to outside of package 300);
wherein the communication interface uses the plurality of connectors in a first configuration (fig. 5, 50G/100G modes uses SAS0/SAS1/PCIe0/PCIe1/PCIe2/PCIe3, e.g., rows 6-7) to access the memory cells from the outside of the integrated circuit package at a first speed (fig. 5, 50G or 100G), and
uses the plurality of connectors in a second configuration (fig. 5, 10G/25G modes uses SAS0/PCIe0/PCIe1/PCIe3, e.g., rows 4-5) to access the memory cells from the outside of the integrated circuit package at a second speed (fig. 5, 10G or 25G) different from the first speed;
wherein the plurality of connectors includes a first subset (fig. 5, connector 312 without using SAS1 308, PCIe2 310) and a second subset (fig. 5, connector 312 with using SAS1 308 and PCIe2 310) different from the first subset.
As to claim 2, Olarig discloses the device of claim 1, wherein
when in the first configuration, the communication interface is to provide access to the memory cells using an entire set of the plurality of connectors at the first speed; and
when in second first configuration, the communication interface is to provide access to the memory cells using a subset of the plurality of connectors at the second speed.
As to claims 3 and 13, Olarig discloses the device of claim 1,
wherein the plurality of connectors includes a first subset (fig. 5, 50G/100G modes uses SAS0/SAS1/PCIe0/PCIe1/PCIe2/PCIe3, e.g., rows 6-7) and a second subset (fig. 5, 10G/25G modes uses SAS0/PCIe0/PCIe1/PCIe3, e.g., rows 4-5) different from the first subset;
when in the first configuration, the communication interface is to use the first subset in data transmission at the first speed (fig. 5, 50G or 100G); and
when in the second configuration, the communication interface is to use the second subset in data transmission at the second speed (fig. 5, 10G or 25G).
As to claims 4 and 14, Olarig discloses the device of claim 3, wherein
the first subset has a first count of connectors (fig. 5, 50G/100G modes uses SAS0/SAS1/PCIe0/PCIe1/PCIe2/PCIe3, e.g., rows 6-7);
the second subset has second count of connectors (fig. 5, 10G/25G modes uses SAS0/PCIe0/PCIe1/PCIe3, e.g., rows 4-5);
the first count and the second count are different; and
the first configuration and the second configuration operate at a same frequency (fig. 5, frequency of SAS/PCIe lanes).
As to claims 5 and 15, Olarig discloses the device of claim 1, wherein
when in the first configuration, a first connector in the plurality of connectors (fig. 5, 50G/100G modes uses SAS0/SAS1/PCIe0/PCIe1/PCIe2/PCIe3, e.g., rows 6-7) transmits a first type of communications (fig. 5, 50G or 100G speed); and
when in the second configuration, the first connector in the plurality of connectors (fig. 5, 10G/25G modes uses SAS0/PCIe0/PCIe1/PCIe3, e.g., rows 4-5) transmits a second type of communications different from the first type (fig. 5, 10G or 25G speed).
As to claims 6 and 16, Olarig discloses the device of claim 5, wherein the first type and the second type of communication are different ones of a plurality of types (fig. 5, Ethernet and/or control Port).
As to claims 7-8, Olarig discloses the device of claim 7,
wherein the integrated circuit package is to enclose the controller (fig. 3A, FPGA ASIC 302 within device 300); and
the controller is to receive the commands via the communication interface from the host (9:4-31, FPGA ASIC 302 interface; fig. 6A1, from motherboard 601).
As to claims 9, 17 and 20, Olarig discloses the device of claim 7, comprising:
a memory cell (fig. 4, CPLD with eSpeed[1:0] 402) to store data identifying a configuration to operate the plurality of connectors (figs. 6A1/6B1, CPLD 630 configuring Ethernet A/B/C/D).
As to claims 10-11 and 18, Olarig discloses the device of claim 9,
wherein the controller or the communication interface is to determine a current configuration (10:47-67, Ethernet speed by eSpeed[1:0]) under which the plurality of connectors are currently being used.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f), because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
Such claim limitations are:
“integrated circuit package” in claims 1 and 19,
“communication interface” in claim 2,
“first configuration” and “second configuration” in claims 4 and 14,
“first connector” in claims 5 and 15,
“controller” in claim 7, and
“memory cell” in claim 9.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f), it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f).
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Cheng-Yuan Tseng whose telephone number is (571)272-9772, and fax number is (571)273-9772. The examiner can normally be reached on Monday through Friday from 09:00 to 17:30 Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alicia Harrington can be reached on (571)272-2330. The fax phone number for the organization where this application or proceeding is assigned is (571)273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866)217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800)786-9199 (IN USA OR CANADA) or (571)272-1000.
/CHENG YUAN TSENG/Primary Examiner, Art Unit 2615
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