DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102
and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same
under either status.
Response to Arguments
Applicant's arguments filed 05/04/2026 regarding the prior art rejections of Claims 1 - 20 have been fully considered, but they are not persuasive.
The Remarks argue that:
Applicant submits Ergott, Volpe, and Lillibridge do not disclose all limitations in claims 1, 11, and 19 and the rejections should be withdrawn. Insofar as claims 2-10, 12-15, 17, 18, and 20 depend from claim 1, 11 or 19, the 103 rejections of claims 2-10, 12-15, 17, 18, and 20 should be withdrawn for the same reasons.
Ergott fails to disclose that an interruption circuit providing a safety vector to a processing circuit in response to an interruption signal being enabled. Ergott also fails to disclose that in response to a processing circuit receiving the safety vector, the processing circuit enters an error analysis mode to analyze the case of the error event and perform a debug operation.
The same claimed feature lacking in Ergott cannot be found in Volpe, and Lillibridge.
According to paragraph [0016] of the present application, when the health level of the microcontroller 120 is not good, the microcontroller 120 may perform an interruption operation or a reset operation to enter an error analysis mode. In the error analysis mode, the microcontroller 120 analyses the collected error information. The microcontroller 120 may issue a warning message or perform a debug operation to protect the entire analysis system.
However, Ergott, Volpe, and Lillibridge do not disclose or teach these features.
The Examiner disagrees Ergott, Volpe, and Lillibridge do teach all limitations in combination with one another. Ergott doesn’t explicitly disclose that an interruption circuit providing a safety vector to a processing circuit in response to an interruption signal being enabled, but does suggest it. In the presented application, the interruption circuit and the safety vector are defined broadly. From the Examiner’s interpretation, the safety and user vectors are the corresponding error information based on the value/threshold of the error flag. According to paragraphs, 0042 – 0043, the interruption circuit is just a component of “the microcontroller circuit 200C.” Additionally, “when the value of the error flag 280 is equal to the specific value, the interruption circuit 290 uses a safety vector SV as an interruption vector IV.” Ergott teaches a controller circuit and different functions and processes based on a voltage threshold. (Abstract & 8, In the event of a short duration power interruption, the memory system enters a hold mode in which data maintenance power is supplied to the SRAM by discharging a backup capacitor, and accessing of the SRAM by a host computer is halted. If the backup capacitor voltage does not fall below a threshold before power is restored, the hold mode is terminated and accessing by the host computer continues. If the backup capacitor voltage falls below the threshold, operating power is supplied to the SRAM, E.sup.2 PROM, and associated circuitry to download all data and row and column parity data into the E.sup.2 PROM by further discharging of the backup capacitor. downloading is initiated if the voltage stored on the backup capacitor falls below the predefined threshold, typically about 80% below the nominal backup energy level. In this event, the controller circuit 22 applies full power from the energy storage circuit 6 to all or nearly all of the circuitry in FIG. 1 to effectuate downloading of the entire contents of SRAM 2 into E.sup.2 PROM 8. Controller circuit 22 controls the sequence of all transfers of data between SRAM 2 and E.sup.2 PROM 8. Controller circuit 22 also controls all I/O functions and built-in self test and housekeeping functions.)
The Examiner agrees Ergott fails to independently disclose that in response to a processing circuit receiving the safety vector, the processing circuit enters an error analysis mode to analyze the case of the error event and perform a debug operation.
The Examiner disagrees as Volpe discloses “in response to a processing circuit receiving the safety vector, the processing circuit enters an error analysis mode to analyze the case of the error event and perform a debug operation.” Volpe teaches debugging and error analysis. (84 & 90, The debug module 620 may be used for debugging the offload engine 108 in instances when the performance or the health of the offload engine 108 is outside an acceptable range based on the threshold. The debug module 620 may help identify a component of the integrated circuit device in the offload engine 108, which may be defective or may not be performing optimally. In some examples, the debug module 620 may access one or more registers in the offload engine 108 to test a particular accelerator or the data movement processor while other accelerators and the data movement processors are still executing. based on the information, if the number of cycles in the waiting state is more than a threshold for a first error type, or if the number of correctable ECC errors generated within a time period are more than a threshold for a second error type, the microcontroller 110 may send the collected data to the remote management server 122 for analysis using the communication module 622. The remote management server 122 may provide new configuration values to reconfigure the accelerator 202a, reset the accelerator 202a, or shut down the accelerator 202a;))
In conclusion, one skilled in the art could use Ergott, Volpe, and Lillibridge in combination to conclude the limitations of amended independent claims 1, 11, and 19. The previous prior art rejection is maintained.
Claims 2 – 10 which depend from claim 1, have been considered and rejected.
Claims 11 - 18 which depend from claim 11, have been considered and rejected.
Claim 20 which depends from claim 19, has been considered and rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 15 & 16 - 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ergott (US 4965828 A) in view of Volpe (US 10949321 B1) in view of Lillibridge (US 10776192 B2). Claim 16 has been canceled.
In regards to claim 1, Ergott teaches:
a detection circuit enabling a trigger signal and outputting error information in response to an occurrence of an error event; (5 & 34, Error detection circuitry 18 includes standard Hamming code double bit detection, single bit correction circuitry to "scrub" errors from data read out of SRAM 2. Error detection and correction circuitry 20 includes row and column parity circuitry and correction circuitry which efficiently "scrubs" errors from data read out of E.sup.2 PROM 8. Control circuit 101 receives data error information 102A from Data In parity check circuit 102, and also receives external read and external write signals and control signals on bus 101A.) a storage circuit (4, Power is supplied to SRAM 2 via a power bus from an energy storage circuit 6); a comparison circuit enabling an interruption signal in response to the count value reaching a threshold value; (45 & 12, Hamming comparator/corrector circuit 110 receives both the 16 bits of latched data on bus 112A and also receives the 6 bits of Hamming data supplied on bus 109A by Hamming code generator 109 or read out of Hamming data section 2B of SRAM 2. Hamming code generator 109 regenerates the Hamming codes. The Hamming data that is regenerated is compared to the Hamming data that was previously stored. The interruption of input power designated by section 32B of input voltage waveform 32 causes a very slow decay of backup voltage waveform 35 between points 35C and 35D. However, backup voltage waveform 35 does not fall below backup voltage threshold 36.) and a processing circuit performing a specific operation according to the interruption signal. (6, The non-volatile memory system 1 of FIG. 1 normally operates as an SRAM when the main power on conductor 10 is present. If there is a power interruption or failure, non-volatile energy system 1 acts as a backup memory that contains all of the data in SRAM 2 immediately before the interruption of input power 10.) and an interruption circuit providing a safety vector to the processing circuit in response to the interruption signal being enabled, (34, 57, & abstract, Control circuit 101 receives data error information 102A from Data In parity check circuit 102, and also receives external read and external write signals and control signals on bus 101A. If a data error is detected by data in parity check circuit 102 at the present address, data in parity check circuit 102 produces a data error signal on conductor 102A. This data error signal may be read by host computer 120 to inform it that the present data contains an error.If the backup capacitor voltage falls below the threshold, operating power is supplied to the SRAM, E.sup.2 PROM, and associated circuitry to download all data and row and column parity data into the E.sup.2 PROM)
Ergott fails to teach:
A microcontroller circuit comprising; storing the error information; wherein in response to the processing circuit receiving the safety vector, the processing circuit enters an error analysis mode to analyze the case of the error event and perform a debug operation.
However, Volpe teaches:
A microcontroller circuit comprising; (Abstract, an integrated circuit device can be performed by a microcontroller based on information associated with the notification messages generated by the integrated circuit device.) storing the error information; (15, each integrated circuit may include registers to store information associated with runtime operations of the integrated circuit. the statistics registers may store counts for the number of instructions executed, number of interrupts, number of cycles in running state, number of cycles in waiting state, number of write transactions performed, etc. For example, the metadata may identify an error or an event). wherein in response to the processing circuit receiving the safety vector, the processing circuit enters an error analysis mode to analyze the case of the error event and perform a debug operation. (84 & 90, The debug module 620 may be used for debugging the offload engine 108 in instances when the performance or the health of the offload engine 108 is outside an acceptable range based on the threshold. The debug module 620 may help identify a component of the integrated circuit device in the offload engine 108, which may be defective or may not be performing optimally. In some examples, the debug module 620 may access one or more registers in the offload engine 108 to test a particular accelerator or the data movement processor while other accelerators and the data movement processors are still executing. based on the information, if the number of cycles in the waiting state is more than a threshold for a first error type, or if the number of correctable ECC errors generated within a time period are more than a threshold for a second error type, the microcontroller 110 may send the collected data to the remote management server 122 for analysis using the communication module 622. The remote management server 122 may provide new configuration values to reconfigure the accelerator 202a, reset the accelerator 202a, or shut down the accelerator 202a;)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Ergott which teaches error detection and correction with the teaching of Volpe which teaches a microcontroller circuit storing the error information in order to identify and correct errors found in the memory. (Volpe: 61, The error management 406 may be configured to detect an error condition in the integrated circuit.)
Ergott in view of Volpe fails to teach:
an error counter circuit adjusting a count value according to the number of times that the trigger signal is enabled by the detection circuit;
However, Lillibridge teaches:
an error counter circuit adjusting a count value according to the number of times that the trigger signal is enabled by the detection circuit; (Claim 9, upon initiating the execution of the first process, trigger a synchronous error check process and an asynchronous error check process, wherein the synchronous error check process comprises: proactively accessing an error counter to determine a current value; determining that the first value was written to the memory; proactively accessing the error counter to determine an updated value; and when the current value and the updated value are different, indicating that a first error occurred in writing to the memory;)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Ergott which teaches error detection and correction with the teaching of Lillibridge which teaches an error counter according to a detected signal in order to identify errors found in the memory. (Lillibridge: 18, The error counter may be used to count the number of errors that have occurred writing to the memory 140. In other words, upon detection of an error in writing to memory, the error counter may be altered (e.g., incremented or decremented).)
In regards to claim 2, Ergott in view of Volpe in view of Lillibridge teaches the microcontroller circuit as claimed in claim 1. Ergott teaches:
wherein the specific operation is a reset operation. (5, a reset signal is produced to reset the processor.)
In regards to claim 3, Ergott in view of Volpe in view of Lillibridge teaches the microcontroller circuit as claimed in claim 2. Ergott teaches:
wherein after finishing the reset operation, the processing circuit enters error analysis mode to analyze the error information stored in the storage circuit. (3, SRAM 2 is accessed in response to control circuitry 22 and in conjunction with operation of error detection and correction circuitry 18.)
In regards to claim 4, Ergott in view of Volpe in view of Lillibridge teaches the microcontroller circuit as claimed in claim 2. Ergott teaches:
further comprising: an error flag coupled to the comparison circuit, wherein: in response to the count value reaching the threshold value, the comparison circuit sets the value of the error flag to a specific value, and in response to the value of the error flag being the specific value, the processing circuit performs the specific operation. (5, a counter is started, but normal operation of the system continues. If the unregulated DC voltage does not rise above a second threshold that is slightly higher than the first threshold before the counter times out, a processor initiates transfer of data from the volatile RAM to the non-volatile E.sup.2 PROM.)
In regards to claim 5, Ergott in view of Volpe in view of Lillibridge teaches the microcontroller circuit as claimed in claim 4. Ergott teaches:
wherein: the interruption circuit provides the safety vector to the processing circuit in response to the value of the error flag being the specific value, the interruption circuit provides a user vector to the processing circuit in response to the value of the error flag not being the specific value. (4, Power is supplied to SRAM 2 via a power bus from an energy storage circuit 6 which contains circuitry shown in FIG. 2 to supply a steady internal input power during normal operating conditions and backup power during short duration power interruptions. External power bus 10 supplies input power at, for example, +5 volts, to energy storage circuit 6.)
In regards to claim 6, Ergott in view of Volpe in view of Lillibridge teaches the microcontroller circuit as claimed in claim 1. Ergott teaches:
further comprising: an input-output pin, wherein: in response to the occurrence of the error event, the detection circuit sets a voltage level of the input-output pin to a specific level. (4, Power is supplied to SRAM 2 via a power bus from an energy storage circuit 6 which contains circuitry shown in FIG. 2 to supply a steady internal input power during normal operating conditions and backup power during short duration power interruptions. External power bus 10 supplies input power at, for example, +5 volts, to energy storage circuit 6.)
In regards to claim 7, Ergott in view of Volpe in view of Lillibridge teaches the microcontroller circuit as claimed in claim 1.
Ergott fails to teach:
further comprising: a remap circuit generating a control signal according to the count value, wherein the storage circuit stores the error information according to the control signal.
However, Lillibridge teaches:
further comprising: a remap circuit generating a control signal according to the count value, wherein the storage circuit stores the error information according to the control signal. (8, a memory write error handling technique, a process may cause a processor to execute an instruction to store a value in memory. The processor may then issue the store command to a memory controller to actually execute the storage of the value in memory. The process may then continue execution, even though the memory controller may not yet have written the value to the memory. If an error in writing occurs, the process may be notified via some type of interrupt (e.g., a signal generated by the operating system (OS)).)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Ergott which teaches error detection and correction with the teaching of Lillibridge which teaches an error counter according to a detected signal in order to identify errors found in the memory. (Lillibridge: 18, The error counter may be used to count the number of errors that have occurred writing to the memory 140. In other words, upon detection of an error in writing to memory, the error counter may be altered (e.g., incremented or decremented).)
In regards to claim 8, Ergott in view of Volpe in view of Lillibridge teaches the microcontroller circuit as claimed in claim 1. Ergott teaches:
further comprising: a reset circuit configured to reset the count value. (5, a counter is started, but normal operation of the system continues. If the unregulated DC voltage does not rise above a second threshold that is slightly higher than the first threshold before the counter times out, a processor initiates transfer of data from the volatile RAM to the non-volatile E.sup.2 PROM. If the regulated supply voltage falls below a third threshold at which the processor is no longer able to reliably maintain its operating conditions, a reset signal is produced to reset the processor. The third threshold is set low enough that all data is safely transferred from the volatile RAM to the non-volatile E.sup.2 PROM before the reset signal is generated.)
In regards to claim 9, Ergott in view of Volpe in view of Lillibridge teaches the microcontroller circuit as claimed in claim 8. Ergott teaches:
wherein the processing circuit triggers the reset circuit at fixed time intervals. (34, Control circuit 101 receives data error information 102A from Data In parity check circuit 102, and also receives external read and external write signals and control signals on bus 101A. Control circuit 101 also receives control signals generated by host computer 120 on bus 101A. After an initial edge on the delay on a delay line following edges are produced by the conventional delay line circuitry at 25 nanosecond intervals, and suitable gain circuitry is provided to generate timing signals used to produce the sequence of handshaking required);
In regards to claim 10, Ergott in view of Volpe in view of Lillibridge teaches the microcontroller circuit as claimed in claim 8.
Ergott fails to teach:
further comprising: a power-on reset circuit configured to trigger the reset circuit.
However, Volpe teaches:
further comprising: a power-on reset circuit configured to trigger the reset circuit. (27 & 79, each statistics register may be reset to zero at power up and after each read of the register. the configuration module 612 may be used to write the system configuration registers 308a to configure the notification queues, or to enable the generation of notification messages. The configuration module 612 may also be used to initialize different components of the offload engine 108, e.g., the data movement processors 206a-206p, the accelerators 202a-202n, the memory controllers 214, by writing to associated registers after power on reset.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Ergott which teaches error detection and correction with the teaching of Volpe which teaches a microcontroller circuit storing the error information in order to identify and correct errors found in the memory. (Volpe: 61, The error management 406 may be configured to detect an error condition in the integrated circuit.)
In regards to claim 11, Ergott in view of Volpe in view of Lillibridge teaches the analysis system. The claim corresponds to claim 1 as analyzed accordingly.
In regards to claim 12, Ergott in view of Volpe in view of Lillibridge teaches the analysis system as claimed in claim 11.
Ergott fails to teach:
wherein in response to the detection circuit enabling the trigger signal, the measuring instrument reads the error information from the storage circuit.
However, Volpe teaches:
wherein in response to the detection circuit enabling the trigger signal, the measuring instrument reads the error information from the storage circuit. (15, each integrated circuit may include registers to store information associated with runtime operations of the integrated circuit.)
It would have been obvious to one of ordinary skill in the before the effective filing date of the claimed invention to modify the method of Ergott which teaches error detection and correction with the teaching of Volpe which teaches a microcontroller circuit storing the error information in order to identify and correct errors found in the memory. (Volpe: 61, The error management 406 may be configured to detect an error condition in the integrated circuit.)
In regards to claim 13, Ergott in view of Volpe in view of Lillibridge teaches the analysis system as claimed in claim 11.
Ergott fails to teach:
wherein the debug interface is a serial wire debug (SWD) interface.
However, Volpe teaches:
wherein the debug interface is a serial wire debug (SWD) interface. (84, The debug module 620 may be used for debugging the offload engine 108 in instances when the performance or the health of the offload engine 108 is outside an acceptable range based on the threshold.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Ergott which teaches error detection and correction with the teaching of Volpe which teaches a microcontroller circuit storing the error information in order to identify and correct errors found in the memory. (Volpe: 61, The error management 406 may be configured to detect an error condition in the integrated circuit.)
In regards to claim 14, Ergott in view of Volpe in view of Lillibridge teaches the analysis system as claimed in claim 11. Ergott teaches:
wherein the microcontroller circuit further comprises: a remap circuit generating a control signal according to the count value, wherein the storage circuit stores the error information according to the control signal. (34, Error detection and correction circuitry 20 includes row and column parity circuitry and correction circuitry which efficiently "scrubs" errors from data read out of E.sup.2 PROM 8. Control circuit 101 receives data error information 102A from Data In parity check circuit 102, and also receives external read and external write signals and control signals on bus 101A.)
In regards to claim 15, Ergott in view of Volpe in view of Lillibridge teaches the analysis system as claimed in claim 14. Ergott teaches:
wherein the storage circuit comprises: a non-volatile memory; a volatile memory; and a memory controller storing the error information in the non-volatile memory or the volatile memory according to the control signal. (5, all data is safely transferred from the volatile RAM to the non-volatile E.sup.2 PROM before the reset signal is generated.)
In regards to claim 17, Ergott in view of Volpe in view of Lillibridge teaches the analysis system of claim 11. The claim corresponds to claim 8 as analyzed accordingly.
In regards to claim 18, Ergott in view of Volpe in view of Lillibridge teaches the analysis system of claim 11. The claim corresponds to claim 9 as analyzed accordingly.
In regards to claim 19, Ergott teaches:
A control method applied in a microcontroller circuit, comprising: determining whether an error event occurs; (3, SRAM 2 is accessed in response to control circuitry 22 and in conjunction with operation of error detection and correction circuitry 18.) recording the error information in a storage circuit; (4, Power is supplied to SRAM 2 via a power bus from an energy storage circuit 6); directing a processing circuit to perform a reset operation in response to the count value reaching a threshold value; (45 & 12, Hamming comparator/corrector circuit 110 receives both the 16 bits of latched data on bus 112A and also receives the 6 bits of Hamming data supplied on bus 109A by Hamming code generator 109 or read out of Hamming data section 2B of SRAM 2. Hamming code generator 109 regenerates the Hamming codes. The Hamming data that is regenerated is compared to the Hamming data that was previously stored. The interruption of input power designated by section 32B of input voltage waveform 32 causes a very slow decay of backup voltage waveform 35 between points 35C and 35D. However, backup voltage waveform 35 does not fall below backup voltage threshold 36.) and providing a safety vector to the processing circuit in response to the processing circuit finishing the reset operation. (6, The non-volatile memory system 1 of FIG. 1 normally operates as an SRAM when the main power on conductor 10 is present. If there is a power interruption or failure, non-volatile energy system 1 acts as a backup memory that contains all of the data in SRAM 2 immediately before the interruption of input power 10.)
Ergott fails to teach:
wherein in response to the processing circuit receiving the safety vector, the processing circuit enters an error analysis mode to analyze the case of the error event and perform a debug operation.
However, Volpe teaches:
wherein in response to the processing circuit receiving the safety vector, the processing circuit enters an error analysis mode to analyze the case of the error event and perform a debug operation. (84 & 90, The debug module 620 may be used for debugging the offload engine 108 in instances when the performance or the health of the offload engine 108 is outside an acceptable range based on the threshold. The debug module 620 may help identify a component of the integrated circuit device in the offload engine 108, which may be defective or may not be performing optimally. In some examples, the debug module 620 may access one or more registers in the offload engine 108 to test a particular accelerator or the data movement processor while other accelerators and the data movement processors are still executing. based on the information, if the number of cycles in the waiting state is more than a threshold for a first error type, or if the number of correctable ECC errors generated within a time period are more than a threshold for a second error type, the microcontroller 110 may send the collected data to the remote management server 122 for analysis using the communication module 622. The remote management server 122 may provide new configuration values to reconfigure the accelerator 202a, reset the accelerator 202a, or shut down the accelerator 202a;)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Ergott which teaches error detection and correction with the teaching of Volpe which teaches a microcontroller circuit storing the error information in order to identify and correct errors found in the memory. (Volpe: 61, The error management 406 may be configured to detect an error condition in the integrated circuit.)
Ergott in view of Volpe fails to teach:
adjusting the count value and generating error information in response to the error event occurring;
However, Lillibridge teaches:
adjusting the count value and generating error information in response to the error event occurring; (Claim 9, upon initiating the execution of the first process, trigger a synchronous error check process and an asynchronous error check process, wherein the synchronous error check process comprises: proactively accessing an error counter to determine a current value; determining that the first value was written to the memory; proactively accessing the error counter to determine an updated value; and when the current value and the updated value are different, indicating that a first error occurred in writing to the memory;)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Ergott which teaches error detection and correction with the teaching of Lillibridge which teaches an error counter according to a detected signal in order to identify errors found in the memory. (Lillibridge: 18, The error counter may be used to count the number of errors that have occurred writing to the memory 140. In other words, upon detection of an error in writing to memory, the error counter may be altered (e.g., incremented or decremented).)
In regards to claim 20, Ergott in view of Lillibridge teaches the control method as claimed in claim 19. Ergott teaches:
further comprising: notifying a measuring instrument and providing the error information to the measuring instrument each time the error event occurs, wherein the measuring instrument analyzes the error information to provide an analysis report. (3, SRAM 2 is accessed in response to control circuitry 22 and in conjunction with operation of error detection and correction circuitry 18.)
Prior Art Made of Record
The prior art mode of record and not relied upon is considered pertinent to
Applicant’s disclosure:
Zhou (US 2023/0083193 A1): A system can predict memory device failure through identification of correctable error patterns based on the memory architecture. The failure prediction can thus account for the circuit-level of the memory rather than the mere number or frequency of correctable errors. A failure prediction engine correlates hardware configuration of the memory device with correctable errors (CEs) detected in data of the memory device to predict an uncorrectable error (UE) based on the correlation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office
action. Applicant's arguments filed 05/04/2026 regarding the prior art rejections of Claims 1 – 20 have
been fully considered and are persuasive.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner
should be directed to VICTOR PERRY whose telephone number is (571)272-6319. The examiner can
normally be reached Monday - Friday 8:00 - 5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor,
Mark Featherstone can be reached on (571) 270-3750. The fax phone number for the organization
where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from
Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit
https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and
https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional
questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like
assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/V.P./Examiner, Art Unit 2111
/GUERRIER MERANT/Primary Examiner, Art Unit 2111 6/22/2026
Prosecution Insights