DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim(s) 2-6 and 14-17 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim(s) 1, 7-13 and 18-20 is/are rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1-7, 18-20 and 22 of U.S. Patent No. 11507513. Although the claims at issue are not identical, they are not patentably distinct from each other.
Application 18/905,305
Patent 11507513
1. A system, comprising: a cache memory; and a cache controller coupled to the cache memory and configured to: receive a histogram operation that specifies a set of data; read the set of data from the cache memory; and cause an arithmetic circuit to generate a vector representing a histogram of the set of data, wherein to generate the vector, the arithmetic circuit is configured to: initiate elements of the vector each of which corresponds to a value in the set of data; and increment an element of the vector based on occurrence of a corresponding value in the set of data.
1. A system comprising: a cache storage coupled to an arithmetic component; and a cache controller coupled to the cache storage, wherein the cache controller is operable to: receive instructions corresponding to a histogram operation that specifies a set of data; retrieve the set of data from the cache storage; utilize the arithmetic component to; determine a set of counts of respective values in the set of data; and perform the histogram operation by generating a vector representing the set of counts corresponding to respective values in the set of data to (a) initiate the vector including elements corresponding to the histogram operation and (b) update the vector by incrementing the set of counts based on the set of data; and provide the vector.
7. The system of claim 1, wherein the cache controller is configured to: prior to causing the arithmetic circuit to generate the vector, perform an error code correction (ECC) operation on the set of data.
6. The system of claim 1, wherein the arithmetic component is to obtain (a) the set of data from the cache storage via an error detection and correction circuit and (b) the histogram operation from a central processing unit via a latch.
8. The system of claim 1, wherein the cache controller is configured to provide the vector including the incremented element to a processor.
3. The system of claim 1, wherein the cache controller is operable to provide the vector to a processor.
9. The system of claim 1, wherein the cache controller is configured to store the vector including the incremented element in the cache memory.
2. The system of claim 1, wherein the cache controller is operable to provide the vector for storing in the cache storage.
10. The system of claim 1, further comprising: a store queue, wherein the arithmetic circuit is included within the store queue.
4. The system of claim 1, further including store queue circuitry coupled to the cache controller, the store queue circuitry including the arithmetic component.
11. The system of claim 1, wherein: the cache memory is a victim cache memory or a main cache memory.
5. The system of claim 1, wherein the cache storage is at least one of a main cache storage or a victim cache storage.
12. The system of claim 1, wherein the arithmetic circuit is configured to generate the vector representing the histogram of the set of data based on one single read of the set of data from the cache memory.
7. The system of claim 1, wherein the cache controller is operable to generate the vector and provide the vector to a central processing unit based on a single instruction from the central processing unit at a single cycle.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Plotnikov (US 2020/0174790): discloses method/apparatus for vectorizing histogram loops.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES J CHOI whose telephone number is (571)270-0605. The examiner can normally be reached MON-FRI: 9AM-5PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ROCIO DEL MAR PEREZ-VELEZ can be reached at 571-270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHARLES J CHOI/Primary Examiner, Art Unit 2133