Prosecution Insights
Last updated: August 17, 2026
Application No. 18/905,318

RTC MICRO-SECOND COUNTER

Non-Final OA §103
Filed
Oct 03, 2024
Examiner
GOODWIN, SCHQUITA D
Art Unit
2459
Tech Center
2400 — Computer Networks
Assignee
STMicroelectronics N.V.
OA Round
1 (Non-Final)
67%
Grant Probability
Favorable
1-2
OA Rounds
1y 7m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allowance Rate
220 granted / 330 resolved
+8.7% vs TC avg
Strong +15% interview lift
Without
With
+15.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
30 currently pending
Career history
355
Total Applications
across all art units

Statute-Specific Performance

§101
11.1%
-28.9% vs TC avg
§103
52.3%
+12.3% vs TC avg
§102
9.0%
-31.0% vs TC avg
§112
25.4%
-14.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 330 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. DETAILED ACTION This communication is in response to Application No. 18/905,318 filed on 3 October 2024. Claims 1-20 are presented for examination. Claim Interpretation Claims 1 and 8 recite “calculate a residual error if the error for the current cycle is less than the previous error” and “determine correction parameters if the residual error is non-zero.” For the purpose of this examination, Examiner interprets all the limitations to be required for the claimed invention and interprets these limitations to mean “calculate a residual error when the error for the current cycle is less than the previous error” and “determine correction parameters when the residual error is non-zero.” Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4, 6-8, 11-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over US PGPUB 2018/0249412 A1 to Zhou et al and in view of US PGPUB 2023/0164709 A1 to Ajami et al. Regarding Claim 1, Zhou discloses a method for maintaining accurate timing in a low-power electronic system (FIG. 2, STA 215), the method comprising: calculating a Timing Synchronization Function (TSF) value for a current cycle using a low-frequency clock source (FIG. 2 and 0061-0062 provides for STA 215 comprising a TSF defined for a current time slot using its own clock timing); calculating an error for the current cycle (0061 provides for STA calculating clock drift for a current time slot); and comparing the error for the current cycle to a previous error (0061 provides for comparing clock drift to a previous time slot). Zhou discloses calculating a residual error if the error for the current cycle is less than the previous error; determining correction parameters if the residual error is non-zero; and applying periodic corrections to the TSF value based on the correction parameters. Ajami, in a similar field of endeavor, discloses calculating a residual error if the error for the current cycle is less than the previous error; determining correction parameters if the residual error is non-zero; and applying periodic corrections to the TSF value based on the correction parameters (0090, 0098, and 0107 provides for STAs that adjust their timing using quit intervals to account for clock drift). One of ordinary skill in the art before the effectively filed date of the claimed invention would have recognized the ability to utilize the teachings of Ajami for updating intervals with clock timing adjustment. The clock timing adjustment of Ajami, when implemented with the synchronization beacon of the Zhou system, will allow one of ordinary skill in the art to calculate TSF timer offsets in order to correct clock drift. Therefore, the examiner concludes it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to utilize the clock timing adjustment of Ajami with the synchronization beacon of the Zhou system for the desirable purpose of correcting clock drift between intervals. Regarding Claim 2, the Zhou/Ajami system discloses the method of claim 1, wherein calculating the TSF value comprises multiplying a clock period by a counter value and taking an integer part of the result (Ajami, 0079 states “the starting time of an SP is defined as an integer value associated with a timing synchronization function (TSF) timer associated with the AP (or BSS) that schedules the SP”). Same motivation as claim 1. Regarding Claim 3, the Zhou/Ajami system discloses the method of claim 1, wherein calculating the error for the current cycle comprises finding a difference between an actual time and the calculated TSF value (Ajami, 0079 provides for TSF timer offset). Same motivation as claim 1. Regarding Claim 4, the Zhou/Ajami system discloses the method of claim 1, further comprising incrementing a counter value and recalculating the TSF value and the error for the current cycle in response to the error for the current cycle being greater than or equal to the previous error (Ajami, 0097 provides for clock drift indicates a timing error based on mean/standard deviation). Same motivation as claim 1. Regarding Claim 6, the Zhou/Ajami system discloses the method of claim 1, wherein determining the correction parameters comprises calculating a frequency at which corrections will be applied and a value of additional increments (Zhou, 0061 provides for correcting clock timing). Regarding Claim 7, the Zhou/Ajami system discloses the method of claim 1, further comprising performing a resynchronization by setting the TSF value to a sum of a previous TSF value from one second ago and 1,000,000 microseconds (Ajami, 0116 provides for any STAs associated with AP may receive resynchronized TSF timers). Same motivation as claim 1. Regarding Claim 8, similar rejection where the method of claim 1 teaches the wireless receiver of claim 8. Regarding Claim 11, similar rejection where the method of claim 2 teaches the wireless receiver of claim 11. Regarding Claim 12, similar rejection where the method of claim 3 teaches the wireless receiver of claim 12. Regarding Claim 13, similar rejection where the method of claim 4 teaches the wireless receiver of claim 13. Regarding Claim 14, the Zhou/Ajami system discloses the wireless receiver of claim 8, wherein the low-power timing circuit is configured to maintain microsecond-level accuracy while using the low-frequency clock source (Ajami, 0116 provides for any STAs associated with AP may receive resynchronized TSF timers). Same motivation as claim 1. Regarding Claim 15, similar rejection where the method of claim 1 teaches the circuit of claim 15. Regarding Claim 16, similar rejection where the method of claim 4 teaches the circuit of claim 16. Regarding Claim 18, similar rejection where the method of claim 6 teaches the circuit of claim 18. Regarding Claim 19, similar rejection where the method of claim 7 teaches the circuit of claim 19. Regarding Claim 20, the Zhou/Ajami system discloses the circuit of claim 15, wherein the control logic circuit is configured to coordinate operation of the circuit to maintain accurate timing using a low-frequency clock source (Ajami, 0116 provides for any STAs associated with AP may receive resynchronized TSF timers). Same motivation as claim 1. Claims 5 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over the Zhou/Ajami system as applied to claim 1 above, and further in view of US PGPUB 2024/0098660 A1 to Maruyama. Regarding Claim 5, the Zhou/Ajami system discloses the method of claim 1. The Zhou/Ajami system doesn’t explicitly disclose wherein calculating the residual error comprises dividing a final error by a counter value and converting the result to nanoseconds. Maruyama, in a similar field of endeavor, discloses wherein calculating the residual error comprises dividing a final error by a counter value and converting the result to nanoseconds (0159 and 0165-0167 provides for time synchronization function calculates an error/deviation based on nanoseconds). One of ordinary skill in the art before the effectively filed date of the claimed invention would have recognized the ability to utilize the teachings of Maruyama for recording information in nanoseconds. The log recording of Maruyama, when implemented with the synchronization beacon of the Zhou/Ajami system, will allow one of ordinary skill in the art to compare sensor values in order to correct clock discrepancies. Therefore, the examiner concludes it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to utilize the log recording of Maruyama with the synchronization beacon of the Zhou/Ajami system for the desirable purpose of comparing values and calculating drift. Regarding Claim 17, similar rejection where the method of claim 5 teaches the circuit of claim 17. Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over the Zhou/Ajami system as applied to claim 8 above, and further in view of US PGPUB 2021/0099966 A1 to Acher. Regarding Claim 9, the Zhou/Ajami system discloses the wireless receiver of claim 8. The Zhou/Ajami system doesn’t explicitly disclose wherein the low-power timing circuit implements the TSF using a counter inside a Real-Time Clock (RTC). Acher, in a similar field of endeavor, discloses wherein the low-power timing circuit implements the TSF using a counter inside a Real-Time Clock (RTC) (0050-0053 provides for RTC counters). One of ordinary skill in the art before the effectively filed date of the claimed invention would have recognized the ability to utilize the teachings of Acher for RTC counters for TSF synchronization. The RTC counters of Acher, when implemented with the synchronization beacon of the Zhou/Ajami system, will allow one of ordinary skill in the art to compare counter values in order to correct discrepancies in real-time. Therefore, the examiner concludes it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to utilize the RTC counters of Acher with the synchronization beacon of the Zhou/Ajami system for the desirable purpose of comparing values for RTC counters. Regarding Claim 10, the Zhou/Ajami/Acher system discloses the wireless receiver of claim 9, wherein the counter is incremented by varying amounts on different clock cycles to approximate a higher-frequency clock (Acher, 0049 provides for high frequency sample clock). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US PGPUB 2013/0188541 A1 to Fischer discloses a target wake time with WLAN devices. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCHQUITA GOODWIN whose telephone number is (571)272-5477. The examiner can normally be reached M-F 9am - 5pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tonia Dollinger can be reached on (571) 272-4170. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SCHQUITA D GOODWIN/Primary Examiner, Art Unit 2459
Read full office action

Prosecution Timeline

Oct 03, 2024
Application Filed
Jul 15, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
67%
Grant Probability
82%
With Interview (+15.1%)
3y 6m (~1y 7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 330 resolved cases by this examiner. Grant probability derived from career allowance rate.

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