Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action is in response to Applicant' s communication filed 2/12/2026 in response to the Office action dated 11/12/2025. Claims 1, 9, and 15 have been amended. Claims 1-20 are pending in this application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 14-15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Madabhushi (US 20190332298 A1) in view of Kim et al. (US 20230126807 A1), hereinafter Kim.
Regarding claim 1, Madabhushi teaches a system comprising: a memory device (Paragraph 21; Fig. 1, nonvolatile memory (NVM) array 114); and
a processing device, operatively coupled to the memory device (Paragraph 23; Fig. 1, controller 107 includes a processing device), to perform operations comprising:
identifying a set of logical addresses associated with data stored on the memory device in one or more blocks of a first type (Paragraph 37; Fig. 4, first set of logical block addresses are associated with a first partition including SLC [first] type NAND blocks 314, 324, 334);
determining a temporal metric class associated with the set of logical addresses, wherein the temporal metric class is associated with a corresponding range of predicted update characteristic of the data (Paragraph 41, determining whether certain data should be considered hot or cold [temporal metric classes] based off of a statistical analysis indicating a frequency of read/write transactions associated with the data [predicted update characteristic]);
identifying, based on the temporal metric class, a set of blocks of a second type (Paragraph 36; Fig. 4, associating cold [temporal metric class] data with a third partition including TLC or QLC [second] type NAND blocks 320, 322, 330, 332, 340, 342),
wherein a first block of the first type comprises a first plurality of memory cells having a first number of bits per cell (Paragraph 29, SLCs (single-level cells) store one [first number] bit of data), and
wherein a second block of the second type comprises a second plurality of memory cells having a second number of bits per cell that exceeds the first number of bits per cell (Paragraph 29, QLCs (quad-level cells) store four [second number] bits of data).
Madabhushi does not explicitly teach moving the data stored on the memory device in the one or more blocks of the first type to the identified set of blocks of the second type.
However, Kim teaches moving the data stored on the memory device in the one or more blocks of the first type to the identified set of blocks of the second type (Paragraph 69, based on the time elapsed since data has been written to a source block, migrating the coldest data stored in the source block within an SLC memory region [first type] to a destination block within an MLC memory region [second type]).
Madabhushi and Kim are analogous art because they are in the same field of endeavor, that being data classification. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Madabhushi to further include the moving of data from a first block type to a second block type according to the teachings of Kim. The motivation for doing so would have been to utilize non-volatile memory space more efficiently (Kim, Paragraph 69).
Regarding claim 8, Madabhushi in view of Kim teaches the system of claim 1, wherein the first number of bits per cell comprises a single bit per cell (Madabhushi, Paragraph 29, SLCs (single-level cells) store one [first number] bit of data), and
wherein the second number of bits per cell comprises four bits per cell (Madabhushi, Paragraph 29, QLCs (quad-level cells) store four [second number] bits of data).
Regarding claim 9, this is a method version of the claimed system discussed above (claim 1, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Madabhushi in view of Kim.
Regarding claim 14, this is a method version of the claimed system discussed above (claim 8, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Madabhushi in view of Kim.
Regarding claim 15, this is a non-transitory computer-readable storage medium version of the claimed system discussed above (claim 1, respectively), in which Madabhushi in view of Kim also teaches a non-transitory computer-readable storage medium comprising instructions (Madabhushi, Paragraph 53, computer or other data processing apparatus implements computer program instructions).
The remaining claim limitations have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Madabhushi in view of Kim.
Regarding claim 20, this is a non-transitory computer-readable storage medium version of the claimed system discussed above (claim 8, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Madabhushi in view of Kim.
Claims 2-7, 10-13, and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Madabhushi in view of Kim as applied to claims 1, 9, and 15 above, and further in view of Hsu et al. (US 20210019650 A1), hereinafter Hsu.
Regarding claim 2, Madabhushi in view of Kim teaches the method of claim 1, but does not explicitly teach wherein identifying the set of logical addresses and determining the temporal metric class are performed by a machine learning model trained to group host data by expected update frequency.
However, Hsu teaches wherein identifying the set of logical addresses and determining the temporal metric class are performed by a machine learning model trained to group host data by expected update frequency (Paragraphs 17, 27-29; Fig. 2, determining/predicting whether data is hot or cold based off of the addresses and timings of historical host commands (indicators of access [update] frequency) using a machine learning model implemented in hot/cold predictor 206).
Madabhushi, Kim, and Hsu are analogous art because they are in the same field of endeavor, that being data classification. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Madabhushi in view of Kim to further include the machine learning model according to the teachings of Hsu. The motivation for doing so would have been to accurately classify hot/cold data, thereby improving the efficiency and lifetime of the storage system (Hsu, Paragraphs 22, 38).
Regarding claim 3, Madabhushi in view of Kim, further in view of Hsu teaches the system of claim 2, wherein the machine learning model is trained using data collected from a tiered storage stack comprising at least one of: a volatile memory device and a non-volatile memory device (Hsu, Paragraphs 40-41; Fig. 4, step 408, determination of hot/cold data using historical commands by the machine learning model may be implemented on volatile or non-volatile memory).
Regarding claim 4, Madabhushi in view of Kim, further in view of Hsu teaches the system of claim 2, wherein the machine learning model is trained using historical data of a workload type same as a workload type of the data (Hsu, Paragraphs 37-38; Fig. 2, an input to the hot/cold predictor 206 may include op codes which indicate whether a command is write or read [workload] so as to classify similar commands).
Regarding claim 5, Madabhushi in view of Kim, further in view of Hsu teaches the system of claim 4, wherein the historical data comprises input/output commands with a set of logical addresses (Hsu, Paragraphs 24-25, 28, historical commands, including read/write commands, contain attributes such as logical block addresses),
a time difference between updates associated with the update characteristic (Hsu, Paragraphs 25, 28, historical command timings or ages indicate a timing difference between commands), and
a size of data associated with the set of logical addresses (Hsu, Paragraphs 24, 28, historical command lengths indicate a size of data associated with the command).
Regarding claim 6, Madabhushi in view of Kim, further in view of Hsu teaches the system of claim 1, wherein the temporal metric class associated with the set of logical addresses is determined in view of a size of the data associated with the set of logical addresses (Hsu, Paragraphs 24, 28, determining whether a data is hot or cold based off of the addresses and lengths [data sizes] of the historical commands).
Regarding claim 7, Madabhushi in view of Kim, further in view of Hsu teaches the system of claim 1, wherein the temporal metric class associated with the set of logical addresses is determined in view of a time difference between updates associated with the update characteristic associated with the set of logical addresses (Hsu, Paragraphs 24-25, 28, determining whether a data is hot or cold based off of the logical block addresses and timing/ages [time differences] of the historical commands).
Regarding claim 10, this is a method version of the claimed system discussed above (claim 2, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Madabhushi in view of Kim, further in view of Hsu.
Regarding claim 11, this is a method version of the claimed system discussed above (claim 3, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Madabhushi in view of Kim, further in view of Hsu.
Regarding claim 12, this is a method version of the claimed system discussed above (claim 4, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Madabhushi in view of Kim, further in view of Hsu.
Regarding claim 13, Madabhushi in view of Kim, further in view of Hsu teaches the method of claim 12, wherein the historical data comprises a set of logical addresses (Hsu, Paragraphs 24, 28; historical commands contain attributes such as logical block addresses),
a time difference between updates associated with the update characteristic (Hsu, Paragraphs 25, 28, historical command timings or ages indicate a timing difference between commands), and
a size of data associated with the set of logical addresses (Hsu, Paragraphs 24, 28, historical command lengths indicate a size of data associated with the command).
Regarding claim 16, this is a non-transitory computer-readable storage medium version of the claimed system discussed above (claim 2, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Madabhushi in view of Kim, further in view of Hsu.
Regarding claim 17, this is a non-transitory computer-readable storage medium version of the claimed system discussed above (claim 3, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Madabhushi in view of Kim, further in view of Hsu.
Regarding claim 18, this is a non-transitory computer-readable storage medium version of the claimed system discussed above (claim 4, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Madabhushi in view of Kim, further in view of Hsu.
Regarding claim 19, this is a non-transitory computer-readable storage medium version of the claimed method discussed above (claim 13, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Madabhushi in view of Kim, further in view of Hsu.
Response to Arguments
Applicant’s arguments (see page 7 of the remarks) filed 2/12/2026, with respect to the rejections of claims 1-20 under 35 U.S.C 112 have been fully considered and are persuasive. Therefore, the rejection of claims 1-20 under 35 U.S.C 112 has been withdrawn.
Applicant’s arguments (see pages 7-11 of the remarks) filed 2/12/2026, with respect to the rejections of claims 1-20 under 35 U.S.C 101 have been fully considered and are persuasive. Therefore, the rejection of claims 1-20 under 35 U.S.C 101 has been withdrawn.
Applicant’s arguments (see pages 11-12 of the remarks) filed 2/12/2026, with respect to the rejections of claims 1-9, 14-15, and 20 under 35 U.S.C 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Madabhushi and Kim.
Applicant’s arguments (see page 12 of the remarks) filed 2/12/2026, with respect to the rejections of claims 2-7, 10-13, and 16-19 under 35 U.S.C 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Madabhushi, Hsu, and Kim.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Pinga whose telephone number is (571) 272-2620. The examiner can normally be reached on M-F 8:30am-6pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla, can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/J.M.P./Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137