Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/10/2026 has been entered.
Response to Amendment
This Office action is in response to Applicant' s communication filed 7/10/2026 in response to the Office action dated 4/21/2026. Claims 1-2, 7, 11-12, and 16-17 have been amended. Claims 1-20 are pending in this application.
Information Disclosure Statement
The listing of references in the specification is not a proper information disclosure statement. 37 CFR 1.98(b) requires a list of all patents, publications, or other information submitted for consideration by the Office, and MPEP § 609.04(a) states, "the list may not be incorporated into the specification but must be submitted in a separate paper." Therefore, unless the references have been cited by the examiner on form PTO-892, they have not been considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6, 11-13, and 16 are rejected under 35 U.S.C 103 as being unpatentable over Iwasaki et al. (US 20210055878 A1), hereinafter Iwasaki, in view of Sheffi et al. (US 20170344295 A1), hereinafter Sheffi, and Jung et al. (US 20130159815 A1), hereinafter Jung.
Regarding claim 1, Iwasaki teaches a memory device (Paragraph 19; Fig. 1, memory subsystem 110 including memory components 112a…n) comprising:
a plurality of memory planes including a first memory plane and a second memory plane (Paragraph 27; Fig. 2, memory component 200 includes first plane 202 and second plane 212),
each memory plane including a plurality of memory blocks (Paragraph 27; Fig. 2, each plane is divided into multiple blocks e.g. blocks 204, 210, 214); and
a processor (Paragraph 25; Fig. 1, memory subsystem 110 is controlled by controller 115 including processor 117),
valid page data of at least one victim block in the first memory plane (Paragraphs 14, 28, 35; Figs. 2 and 3, step 302, identifying valid pages within first block 204 (victim of a data compaction/garbage collection operation) in first plane 202), wherein the processor is configured to:
determine whether at least one target block in the first memory plane is open or full (Paragraph 37; Figs. 2 and 3, step 306, determining whether second [target] block 210 in first plane 202 has the capacity to store the pages [open or full]);
selectively perform one of an internal garbage collection in the first memory plane and an external garbage collection outside the first memory plane (Paragraphs 26, 38-39; Figs. 2 and 3, steps 308 and 310, moving valid data via garbage collection to a block within the same first plane 202 [internal] or to a block in another second plane 212 [external]),
based on the determining whether the target block is open or full (Paragraphs 38-39; Figs. 2 and 3, steps 308 and 310, moving valid data to a block in the first plane 202 or a block in the second plane 212 based on determining whether second [target] block 210 has the capacity to store the pages [open or full]).
Iwasaki does not explicitly teach a processor in the memory device including a checksum calculator to calculate a partial checksum on the page data, determine whether the calculated partial checksum is less than a checksum threshold, and selectively perform one of an internal garbage collection and an external garbage collection based on the determining whether the calculated partial checksum is less than the checksum threshold.
However, Sheffi teaches a processor in the memory device including a checksum calculator (Paragraphs 20-21, 31, 52; Fig. 2A, non-volatile memory system 100 [memory device] includes controller 102, composed of one or more processors, which also comprises error correction controller ECC engine 124 that performs checksum operations)
to calculate a partial checksum on the page data (Paragraph 52; Fig. 2A, ECC engine 124 calculates a checksum on each of the pages of a block (interpreted to be partial checksums since a checksum is calculated on partial portions of a block) in order to estimate an amount of bit errors).
Iwasaki and Sheffi are analogous art because they are in the same field of endeavor, that being storage block management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device of Iwasaki to further include the checksum calculator according to the teachings of Sheffi. The motivation for doing so would have been to improve storage reliability by estimating whether data in a block is sufficiently unreadable (Sheffi, Paragraphs 51-52).
Iwasaki in view of Sheffi does not explicitly teach determine whether the calculated partial checksum is less than a checksum threshold, and selectively perform one of an internal garbage collection and an external garbage collection based on the determining whether the calculated partial checksum is less than the checksum threshold.
However, Jung teaches determine whether the calculated partial checksum is less than a checksum threshold (Paragraphs 91-92, 95-96, 98; Figs. 11-12, steps S210-S220, S310, determining whether the amount of bit errors in a valid page calculated by an ECC engine (calculated by the partial checksums of Sheffi’s ECC engine) does not exceed a [checksum] threshold value), and
selectively perform one of an internal garbage collection and an external garbage collection based on the determining whether the calculated partial checksum is less than the checksum threshold (Paragraphs 85, 97-98; Fig. 12, steps S320-S330, performing an internal or external garbage collection (copy-back) operation based on whether the amount of bit errors (calculated by the partial checksums of Sheffi’s ECC engine) exceeds or does not exceed a [checksum] threshold value).
Iwasaki, Sheffi, and Jung are analogous art because they are in the same field of endeavor, that being storage block management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device of Iwasaki in view of Sheffi to further include the selection of an internal or external garbage collection operation based on a checksum threshold according to the teachings of Jung. The motivation for doing so would have been to reduce performance reduction in consideration of storage device reliability (Jung, Paragraph 5).
Regarding claim 2, Iwasaki in view of Sheffi, further in view of Jung teaches the memory device of claim 1, wherein the processor is configured to: when it is determined that the target block is open (Iwasaki, Paragraph 38; Figs. 2 and 3, step 308, determining that the second [target] block 210 has the capacity to store the pages [open]),
and that the calculated partial checksum is less than the checksum threshold (Sheffi, Paragraphs 85, 98; Fig. 12, step S330, in response to an amount of bit errors in a unit [calculated partial checksum] being less than a threshold value, selecting an internal garbage collection (copy-back) operation),
perform the internal garbage collection to move the valid page data of the victim block in the first memory plane into the target block in the first memory plane (Iwasaki, Paragraphs 28, 35, 38; Figs. 2 and 3, steps 302 and 308, copying [moving] valid pages from a first block 204 (victim of garbage collection) in first plane 202 to a second [target] block 210 in first plane 202).
Regarding claim 3, Iwasaki in view of Sheffi, further in view of Jung teaches the memory device of claim 2, wherein the victim block is included in a victim superblock (Sheffi, Paragraph 88; Fig. 10, step S120, selecting a victim block from a plurality of data blocks that exhibit garbage collection conditions [victim superblock]), and
the target block is included in an inner target superblock (Sheffi, Paragraphs 87, 89; Fig. 10, steps S110, S130, moving valid data to a free [target] block within a plurality of free blocks that are available to store data [inner target superblock]), and
wherein each of the victim superblock and the inner target superblock includes one or more memory blocks (Sheffi, Paragraphs 87-88, the victim block is among data blocks that exhibit garbage collection conditions [collectively a victim superblock] and the free block is from a number of free blocks [collectively an inner target superblock])
of the first memory plane (Iwasaki, Paragraph 27; Fig. 2, first plane 202).
Regarding claim 6, Iwasaki in view of Sheffi, further in view of Jung teaches the memory device of claim 1, wherein the processor is configured to: when it is determined that the target block is full (Iwasaki, Paragraph 39; Figs. 2 and 3, step 310, determining that the second [target] block 210 does not have the capacity to store the pages [full]),
perform the external garbage collection to move the valid page data of the victim block in the first memory plane into an external open block in the second memory plane (Iwasaki, Paragraphs 28, 35, 39; Figs. 2 and 3, steps 302 and 310, copying [moving] valid pages from first block 204 (victim of garbage collection) in first plane 202 to a third [external open] block 214 in second plane 212).
Regarding claim 11, Iwasaki teaches a method for operating a memory device, which includes a plurality of memory planes (Paragraph 27; Fig. 2, memory component 200 includes first plane 202 and second plane 212) and
a processor (Paragraph 25; Fig. 1, memory subsystem 110 is controlled by controller 115 including processor 117), the method comprising:
determining whether at least one target block in a first memory plane among the plurality of memory planes is open or full (Paragraph 37; Figs. 2 and 3, step 306, determining whether second [target] block 210 in first plane 202 has the capacity to store the pages [open or full]);
valid page data of at least one victim block (Paragraphs 14, 28, 35; Figs. 2 and 3, step 302, identifying valid pages within first block 204 (victim of garbage collection));
and selectively performing one of an internal garbage collection in the first memory plane and an external garbage collection outside the first memory plane (Paragraphs 26, 38-39; Figs. 2 and 3, steps 308 and 310, moving valid data via garbage collection to a block within the same first plane 202 [internal] or to a block in another second plane 212 [external]),
based on the determining whether the target block is open or full (Paragraphs 38-39; Figs. 2 and 3, steps 308 and 310, moving valid data to a block in the first plane 202 or to a block in the second plane 212 based on determining whether the second [target] block 210 has the capacity to store the pages [open or full]).
Iwasaki does not explicitly teach the processor including a checksum calculator, determining whether a partial checksum on page data calculated by the checksum calculator is less than a checksum threshold; and selectively performing one of an internal garbage collection and an external garbage collection based on the determining whether the calculated partial checksum is less than the checksum threshold.
However, Sheffi teaches a processor including a checksum calculator (Paragraphs 20-21, 31, 52; Fig. 2A, controller 102, composed of one or more processors, also comprises error correction controller ECC engine 124 that performs checksum operations), and
a partial checksum on page data calculated by the checksum calculator (Paragraph 52; Fig. 2A, ECC engine 124 calculates a checksum on each of the pages of a block (interpreted to be partial checksums since a checksum is calculated on partial portions of a block) in order to estimate an amount of bit errors).
Iwasaki and Sheffi are analogous art because they are in the same field of endeavor, that being storage block management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device of Iwasaki to further include the checksum calculator according to the teachings of Sheffi. The motivation for doing so would have been to improve storage reliability by estimating whether data in a block is sufficiently unreadable (Sheffi, Paragraphs 51-52).
Iwasaki in view of Sheffi does not explicitly teach determining whether a partial checksum on page data calculated by the checksum calculator is less than a checksum threshold; and perform a garbage collection based on the determining whether the calculated partial checksum is less than the checksum threshold.
However, Jung teaches determining whether a partial checksum on page data calculated by the checksum calculator is less than a checksum threshold (Paragraphs 91-92, 95-96, 98; Figs. 11-12, steps S210-S220, S310, determining whether the amount of bit errors in a valid page calculated by an ECC engine (calculated by the partial checksums of Sheffi’s ECC engine) does not exceed a [checksum] threshold value), and
selectively performing one of an internal garbage collection and an external garbage collection based on the determining whether the calculated partial checksum is less than the checksum threshold (Paragraphs 85, 97-98; Fig. 12, steps S320-S330, performing an internal or external garbage collection (copy-back) operation based on whether the amount of bit errors (calculated by the partial checksums of Sheffi’s ECC engine) exceeds or does not exceed a [checksum] threshold value).
Iwasaki, Sheffi, and Jung are analogous art because they are in the same field of endeavor, that being storage block management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device of Iwasaki in view of Sheffi to further include the selection of an internal or external garbage collection operation based on a checksum threshold according to the teachings of Jung. The motivation for doing so would have been to reduce performance reduction in consideration of storage device reliability (Jung, Paragraph 5).
Regarding claim 12, this is a method version of the claimed memory device discussed above (claim 2, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Iwasaki in view of Sheffi, further in view of Jung.
Regarding claim 13, this is a method version of the claimed memory device discussed above (claim 3, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Iwasaki in view of Sheffi, further in view of Jung.
Regarding claim 16, this is a method version of the claimed memory device discussed above (claim 6, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Iwasaki in view of Sheffi, further in view of Jung.
Claims 4-5 and 14-15 are rejected under 35 U.S.C 103 as being unpatentable over Iwasaki in view of Sheffi, further in view of Jung as applied to claims 2 and 12 above, and further in view of Devriendt et al. (US 20210149563 A1), hereinafter Devriendt.
Regarding claim 4, Iwasaki in view of Sheffi, further in view of Jung teaches the memory device of claim 3, wherein the processor receives unit data from a memory controller (Iwasaki, Paragraphs 22, 25; Fig. 1, processor 117 executes operations for data in [receives unit data from] local memory 119 in controller 115), and
the victim block of the victim superblock (Sheffi, Paragraph 88; Fig. 10, step S120, selecting a victim block from a plurality of data blocks that exhibit garbage collection conditions [victim superblock]).
Iwasaki in view of Sheffi, further in view of Jung does not explicitly teach splits the unit data to generate multiple data entries corresponding to memory blocks, and evenly stores the multiple data entries in the memory blocks.
However, Devriendt teaches splits the unit data to generate multiple data entries corresponding to memory blocks (Paragraph 51; Fig. 5, encoder 530 disassembles [splits] a data object into equally sized data within a number of data blocks), and
evenly stores the multiple data entries in the memory blocks (Paragraphs 51-52; Fig. 5, encoder 530 stores equally sized data in the data blocks and block spreader 532 evenly distributes the data blocks among the storage elements).
Iwasaki, Sheffi, Jung, and Devriendt are analogous art because they are in the same field of endeavor, that being storage block management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device of Iwasaki in view of Sheffi, further in view of Jung to further include the splitting and storing of unit data according to the teachings of Devriendt. The motivation for doing so would have been to provide redundancy to protect against failures (Devriendt, Paragraph 50).
Regarding claim 5, Iwasaki in view of Sheffi, further in view of Jung teaches the memory device of claim 4, the valid page data (Iwasaki, Paragraph 35; Figs. 2 and 3, step 302, identifying valid pages in first data block 204), and
the processor performs the internal garbage collection to move the data into the target block in the first memory plane (Iwasaki, Paragraphs 35, 38; Figs. 2 and 3, steps 302 and 308, copying [moving] valid pages to a second [target] block 210 in the (same) first plane 202 [internal]).
Iwasaki in view of Sheffi, further in view of Jung does not explicitly teach wherein the valid page data includes multiple data entries, and moving the multiple data entries equally.
However, Devriendt teaches wherein the valid page data includes multiple data entries (Paragraph 51; Fig. 1, dividing a data object (such as the valid page data) into equally sized data within a number of data blocks), and
moving the multiple data entries equally (Paragraph 52; Fig. 5, block spreader 532 evenly distributes [equally moves] the data blocks among the storage elements).
Iwasaki, Sheffi, Jung, and Devriendt are analogous art because they are in the same field of endeavor, that being storage block management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device of Iwasaki in view of Sheffi, further in view of Jung to further include the multiple data entries according to the teachings of Devriendt. The motivation for doing so would have been to provide redundancy to protect against failures (Devriendt, Paragraph 50).
Regarding claim 14, this is a method version of the claimed memory device discussed above (claim 4, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Iwasaki in view of Sheffi, further in view of Jung and Devriendt.
Regarding claim 15, this is a method version of the claimed memory device discussed above (claim 5, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Iwasaki in view of Sheffi, further in view of Jung and Devriendt.
Claims 7-10 and 17-20 are rejected under 35 U.S.C 103 as being unpatentable over Iwasaki in view of Sheffi, further in view of Jung as applied to claims 6 and 16 above, and further in view of Muchherla et al. (US 20210034274 A1), hereinafter Muchherla.
Regarding claim 7, Iwasaki in view of Sheffi, further in view of Jung teaches the memory device of claim 6, the calculated partial checksum (Sheffi, Paragraph 52; Fig. 2A, ECC engine 124 calculates a checksum on each of the pages of a block (interpreted to be partial checksums since a checksum is calculated on partial portions of a block) in order to estimate an amount of bit errors), and
perform the external garbage collection to move the valid page data of the victim block in the first memory plane into the external open block in the second memory plane (Iwasaki, Paragraphs 28, 35, 39; Figs. 2 and 3, steps 302 and 310, copying [moving] valid pages from first block 204 (victim of garbage collection) in first plane 202 to a third [external open] block 214 in second plane 212).
Iwasaki in view of Sheffi, further in view of Jung does not explicitly teach when it is determined that the target block is open and the calculated checksum is greater than or equal to the checksum threshold, moving data out of the victim block in the first memory plane into an external open block in the second memory plane.
However, Muchherla teaches when it is determined that the target block is open and the calculated checksum is greater than or equal to the checksum threshold (Paragraphs 39-40; Fig. 4, steps 450-460, determining that the error rate (such as errors detected by checksums) is greater than a threshold criterion and finding another [target] block (open due to being able to receive data)),
moving data out of the victim block in the first memory plane into an external open block in the second memory plane (Paragraphs 39-40; Fig. 4, steps 450-460, relocating [moving] data from the initial [victim] block to another [external open] block on another plane).
The Examiner notes that Sheffi teaches detecting errors via checksums while Muchherla teaches the detected errors reaching an exceedable threshold and moving data to another plane in response.
Iwasaki, Sheffi, Jung, and Muchherla are analogous art because they are in the same field of endeavor, that being storage block management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device of Iwasaki in view of Sheffi, further in view of Jung to further include the movement of data into a second plane in response to the calculated checksum exceeding a threshold according to the teachings of Muchherla. The motivation for doing so would have been to improve reliability by avoiding the effects of a read disturb error at the memory component (Muchherla, Paragraph 17).
Regarding claim 8, Iwasaki in view of Sheffi, further in view of Jung and Muchherla teaches wherein the external open block is included in an external target superblock including one or more memory blocks of the second memory plane (Muchherla, Paragraphs 24, 40; Fig. 4, step 460, relocating data to a [external open] block on another plane comprising a plurality of blocks [external target superblock])
Regarding claim 9, Iwasaki in view of Sheffi, further in view of Jung and Muchherla teaches the memory device of claim 8, wherein the first memory plane and the second memory plane belong to a same memory die (Muchherla, Paragraphs 15, 40; Fig. 4, step 460, relocating data in a [first] plane to another block of another [second] plane on the same memory component (with one die)).
Regarding claim 10, Iwasaki in view of Sheffi, further in view of Jung and Muchherla teaches the memory device of claim 8, wherein the first memory plane and the second memory plane belong to a different memory die (Muchherla, Paragraphs 15, 40; Fig. 4, step 460, relocating data in a [first] plane to another block of another [second] plane on another memory component (consisting of dice)).
Regarding claim 17, this is a method version of the claimed memory device discussed above (claim 7, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Iwasaki in view of Sheffi, further in view of Jung and Muchherla.
Regarding claim 18, this is a method version of the claimed memory device discussed above (claim 8, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Iwasaki in view of Sheffi, further in view of Jung and Muchherla.
Regarding claim 19, this is a method version of the claimed memory device discussed above (claim 9, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Iwasaki in view of Sheffi, further in view of Jung and Muchherla.
Regarding claim 20, this is a method version of the claimed memory device discussed above (claim 10, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Iwasaki in view of Sheffi, further in view of Jung and Muchherla.
Response to Arguments
Applicant’s remaining arguments (see pages 9-15 of the remarks) filed 7/10/2026, with respect to the rejections of claims 1-20 under 35 U.S.C 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Iwasaki, Sheffi, Jung, Devriendt, and Muchherla.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Pinga whose telephone number is (571) 272-2620. The examiner can normally be reached on M-F 8:30am-6pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla, can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/J.M.P./Examiner, Art Unit 2137
/TRACY A WARREN/Primary Examiner, Art Unit 2137
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