DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
The terminal disclaimer filed on 09/03/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of US Patent No. 12141890 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Response to Amendment
This is in response to applicant’s amendment/response filed on 09/03/2026, which has been entered and made of record. Claims 1 and 14 have been amended. Claims 1-20 are pending in the application.
The amendment of specification is OK to Enter.
Response to Arguments
Applicant's arguments filed on 0089/03/2026 have been fully considered but they are not persuasive.
Applicants state that “A rejection under 35 U.S.C. 103 is only proper if the prior art actually teaches or suggests the claimed limitation that the primary reference lacks. See MPEP § 2141.01; KSR Int'l Co. V. Teleflex Inc., 550 U.S. 394, 404 (2007) (obviousness analysis requires identifying a problem and "some teaching, suggestion, or motivation, either in the cited art or elsewhere in the prior art," to modify the primary reference); In re Oetker-Pharm. Corp., 427 F.2d 437 (CCPA 1970) (a combination must be supported by an actual teaching in the prior art, not by unsupported conclusions). Where the cited support for a limitation does not exist in the cited reference, the rejection is unsupported as a matter of fact. Applicant respectfully requests that the Examiner identify the actual reference from which the quoted passage is taken, or alternatively withdraw the application of Rauchfuss et al. on the ground that it does not disclose the limitation it is invoked to teach. Furthermore, in light of this issue, applicant respectfully submits that the next Office Action cannot be properly made final”.
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The examiner disagrees. 1. Do you review par 0017 as Examiner disclosure (as shown in same page) (Please review whole prior art). 2. The prior art Rauchfuss et al. teach an interconnect fabric coupled with the first cache memory, wherein the first cache memory is associated with the graphics multiprocessor (Fig 1, par 0017-0018, “the cache 108 (that may be shared) may be a mid-level cache (MLC), a last level cache (LLC), etc. Also, each of the cores 106 may include a level 1 (L1) cache (116-1) (generally referred to herein as “L1 cache 116”) or other levels of cache such as a level 2 (L2) cache. Moreover, various components of the processor 102-1 may communicate with the cache 108 directly, through a bus (e.g., the bus 112), and/or a memory controller or hub”), a second cache memory coupled with the interconnect fabric, (Fig 1, par 0015-0018, “the cache 108 (that may be shared) may be a mid-level cache (MLC), a last level cache (LLC), etc. Also, each of the cores 106 may include a level 1 (L1) cache (116-1) (generally referred to herein as “L1 cache 116”) or other levels of cache such as a level 2 (L2) cache. Moreover, various components of the processor 102-1 may communicate with the cache 108 directly, through a bus (e.g., the bus 112), and/or a memory controller or hub ….. As shown in FIG. 1, the processor 102 may further include graphics logic 140 to perform various graphics and/or general purpose computation(s) related operations such as discussed herein. Logic 140 may have access to one or more storage devices discussed herein (such as cache 108, L1 cache 116, memory 114, register(s), or another memory in system 100) to store information relating to operations of the logic 140, such as information communicated with various components of system 100 as discussed here. Also, while logic 140 is shown inside the processor 102, it may be located elsewhere in the system 100 in various embodiments. For example, logic 140 may replace one of the cores 106, may be coupled directly to interconnection 112 and/or interconnection 104, etc.” …the prior art disclose cache 108 and interconnection 112 in Fig 1).
Applicants state that “The Office Action invokes Ryan et al. (titled "Cache Arrangement") for "the die interface including an interconnect cache to cache data transmitted via the die interface" (claim 1) and "the die interface includes an interconnect buffer to temporarily store commands or data received via the interconnect fabric" (claim 2). The phrase "interconnect buffer" does not appear in US 2013/0031313 A1. What Ryan et al. discloses is a distributed cache arrangement: a first cache arrangement 12 on a first die and a second cache arrangement 25 on a second die, connected by an interconnect 43, with a cache controller and inputs/outputs configured to receive memory requests and provide responses (see, e.g., FIG. 2). A distributed cache topology in which the caching function itself is split across two dies is not the claimed "interconnect buffer to temporarily store commands or data received via the interconnect fabric" within the die interface, nor is it the claimed "interconnect cache" as part of a die interface that couples an interconnect fabric to one or more other dies. Reading a two-die distributed cache arrangement as a single "interconnect buffer" or "interconnect cache" element in a die interface would import a structural feature the claim requires but the reference does not have”.
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The examiner disagrees. Ryan et al. teach the die interface including an interconnect cache to cache data transmitted via the die interface (Fig 1, par 0026-0027, “As is schematically shown in FIG. 1, the network-on-chip 14 is connected via a communication path 18 to a cache arrangement 12. This will be described in more detail later. The network-on-chip 14 is connected to an interface 6 via a communication path 20. The communication paths 18 and 20 may be interconnects”, Fig 2, par 0041-0045, “A first cache arrangement 12 is provided on a first die with a second cache arrangement 25 on a second die. The first cache arrangement has a cache memory 56 and a cache controller 54 for controlling the cache memory. The interconnect between the two dies is represented by reference numeral 43. Reference numeral 41 schematically represents the communication path between the cache arrangement 12 of the first die and the interconnect 43. This communication path may include the interface and/or any other circuitry between the cache arrangement 12 and the interconnect 43”….disclose a first die 2 which has a cache 12 through communication path 19 to interface 6 to connect to second a second die 4 which has a cache 25 through communication path 27 to interface 8 to perform data transfer).
Applicants state that “For the foregoing reasons, applicant respectfully submits that the combination of Targowski et al., Rauchfuss et al., Delacruz et al., and Ryan et al. does not teach or suggest the multi-chip module of claim 1 or the apparatus of claim 14, and the dependent claims are similarly not rendered obvious, primarily but not limited to because the application of Rauchfuss et al. to supply the conceded-missing "second cache memory coupled with the interconnect fabric" rests on a quoted passage that does not appear in the cited reference. Applicant respectfully requests that the rejection under 35 U.S.C. 103 be withdrawn and that the next Office Action cannot be made final”.
The examiner disagrees. Prior art Targowski et al. as modified by Rauchfuss et al., Delacruz et al., and Ryan et al. teach all the limitation of independent claims 1 and 14 (Please review the Examiner’s analysis for the previous issue raised by Applicant). So the rejection would be maintained. Same reason for all dependent claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. PGPubs 2019/0057061 to Targowski et al. in view of U.S. PGPubs 2016/0026494 to Rauchfuss et al., further in view of U.S. PGPubs 2018/0102251 to Delacruz et al., further in view of U.S. PGPubs 2013/0031313 to Ryan et al..
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Regarding claim 1, Targowski et al. teach a multi-chip module comprising (Figs 11B-12, par 0140-0142, disclose a SOC system with processors):
a package assembly comprising a plurality of semiconductor dies and a plurality of die-to-die interconnects, the plurality of semiconductor dies comprising (Fig 11B-12, par 0136-0138, “The integrated circuit package assembly 1170 illustrates an implementation of one or more processor or accelerator devices as described herein. The package assembly 1170 includes multiple units of hardware logic 1172, 1174 connected to a substrate 1180. The logic 1172, 1174 may be implemented at least partly in configurable logic or fixed-functionality logic hardware, and can include one or more portions of any of the processor core(s), graphics processor(s), or other accelerator devices described herein. Each unit of logic 1172, 1174 can be implemented within a semiconductor die and coupled with the substrate 1180 via an interconnect structure 1173. The interconnect structure 1173 may be configured to route electrical signals between the logic 1172, 1174 and the substrate 1180, and can include interconnects such as, but not limited to bumps or pillars “, par 0141, “FIG. 12 is a block diagram illustrating an exemplary system on a chip integrated circuit 1200 that may be fabricated using one or more IP cores, according to an embodiment. Exemplary integrated circuit 1200 includes one or more application processor(s) 1205 (e.g., CPUs), at least one graphics processor 1210, and may additionally include an image processor 1215 and/or a video processor 1220, any of which may be a modular IP core from the same or multiple different design facilities“ ….disclose a plurality of based die have interconnect structures):
a first semiconductor die including (Fig 11B-12, par 0136-0138) :
a plurality of graphics processing resources including a graphics multiprocessor coupled with a first cache memory (Fig 11B-12, par 0136-0138, “The integrated circuit package assembly 1170 illustrates an implementation of one or more processor or accelerator devices as described herein. The package assembly 1170 includes multiple units of hardware logic 1172, 1174 connected to a substrate 1180. The logic 1172, 1174 may be implemented at least partly in configurable logic or fixed-functionality logic hardware, and can include one or more portions of any of the processor core(s), graphics processor(s), or other accelerator devices described herein. Each unit of logic 1172, 1174 can be implemented within a semiconductor die and coupled with the substrate 1180 via an interconnect structure 1173. The interconnect structure 1173 may be configured to route electrical signals between the logic 1172, 1174 and the substrate 1180, and can include interconnects such as, but not limited to bumps or pillars“, Fig 14, par 0146-0147, “FIG. 14A illustrates a graphics core 1400 that may be included within the graphics processor 1210 of FIG. 12, and may be a unified shader core 1355A-1355N as in FIG. 13B … As shown in FIG. 14A, the graphics core 1400 includes a shared instruction cache 1402, a texture unit 1418, and a cache/shared memory 1420 that are common to the execution resources within the graphics core 1400”);
an interconnect fabric coupled with the first cache memory (par 0103, par 0107, “The graphics processor 800 has an interconnect bus, interconnect fabric, or some other interconnect mechanism that allows data and message passing amongst the major components of the processor. In some embodiments, execution units 852A-852B and associated logic units (e.g., L1 cache 851, sampler 854, texture cache 858, etc.) interconnect via a data port 856 to perform memory access and communicate with render output pipeline components of the processor”),wherein the first cache memory is associated with the graphics multiprocessor (Fig 14, par 0146-0147, “FIG. 14A illustrates a graphics core 1400 that may be included within the graphics processor 1210 of FIG. 12, and may be a unified shader core 1355A-1355N as in FIG. 13B … As shown in FIG. 14A, the graphics core 1400 includes a shared instruction cache 1402, a texture unit 1418, and a cache/shared memory 1420 that are common to the execution resources within the graphics core 1400”); and
a die interface configurable to couple the interconnect fabric with one or more of a plurality of semiconductor dies (Fig 11B-12, abstract, par 0136-0138, “The integrated circuit package assembly 1170 illustrates an implementation of one or more processor or accelerator devices as described herein. The package assembly 1170 includes multiple units of hardware logic 1172, 1174 connected to a substrate 1180. The logic 1172, 1174 may be implemented at least partly in configurable logic or fixed-functionality logic hardware, and can include one or more portions of any of the processor core(s), graphics processor(s), or other accelerator devices described herein. Each unit of logic 1172, 1174 can be implemented within a semiconductor die and coupled with the substrate 1180 via an interconnect structure 1173. The interconnect structure 1173 may be configured to route electrical signals between the logic 1172, 1174 and the substrate 1180, and can include interconnects such as, but not limited to bumps or pillars”), the plurality of semiconductor dies including a second semiconductor die that includes a third cache memory (Fig 11B, par 0136, “The logic 1172, 1174 may be implemented at least partly in configurable logic or fixed-functionality logic hardware, and can include one or more portions of any of the processor core(s), graphics processor(s), or other accelerator devices described herein”, par 0141, “FIG. 12 is a block diagram illustrating an exemplary system on a chip integrated circuit 1200 that may be fabricated using one or more IP cores, according to an embodiment … Memory interface may be provided via a memory controller 1265 for access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 1270”, par 0037, par 0048, “the processor 102 also uses an external cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC)) (not shown), which may be shared among processor cores 107 using known cache coherency techniques”, par 0043, “The internal cache units 204A-204N and shared cache units 206 represent a cache memory hierarchy within the processor 200. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, where the highest level of cache before external memory is classified as the LLC. In some embodiments, cache coherency logic maintains coherency between the various cache units 206 and 204A-204N”) and a third semiconductor die that includes an external memory (abstract, par 0039, “The memory device 120 can be a dynamic random-access memory (DRAM) device, a static random-access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory”).
But Targowski et al. keep silent for teaching a second cache memory coupled with the interconnect fabric.
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In related endeavor, Rauchfuss et al. teach an interconnect fabric coupled with the first cache memory, wherein the first cache memory is associated with the graphics multiprocessor (Fig 1, par 0017-0018, “the cache 108 (that may be shared) may be a mid-level cache (MLC), a last level cache (LLC), etc. Also, each of the cores 106 may include a level 1 (L1) cache (116-1) (generally referred to herein as “L1 cache 116”) or other levels of cache such as a level 2 (L2) cache. Moreover, various components of the processor 102-1 may communicate with the cache 108 directly, through a bus (e.g., the bus 112), and/or a memory controller or hub”), a second cache memory coupled with the interconnect fabric (Fig 1, par 0015-0018, “the cache 108 (that may be shared) may be a mid-level cache (MLC), a last level cache (LLC), etc. Also, each of the cores 106 may include a level 1 (L1) cache (116-1) (generally referred to herein as “L1 cache 116”) or other levels of cache such as a level 2 (L2) cache. Moreover, various components of the processor 102-1 may communicate with the cache 108 directly, through a bus (e.g., the bus 112), and/or a memory controller or hub ….. As shown in FIG. 1, the processor 102 may further include graphics logic 140 to perform various graphics and/or general purpose computation(s) related operations such as discussed herein. Logic 140 may have access to one or more storage devices discussed herein (such as cache 108, L1 cache 116, memory 114, register(s), or another memory in system 100) to store information relating to operations of the logic 140, such as information communicated with various components of system 100 as discussed here. Also, while logic 140 is shown inside the processor 102, it may be located elsewhere in the system 100 in various embodiments. For example, logic 140 may replace one of the cores 106, may be coupled directly to interconnection 112 and/or interconnection 104, etc.” …the prior art disclose cache 108 and interconnection 112 in Fig 1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Targowski et al. to include a second cache memory coupled with the interconnect fabric as taught by Rauchfuss et al. to provide a highly flexible solution that could be used in other applications, e.g., where workloads need to be stopped before completion to make way for higher priority operations to improve the responsiveness of hardware to application requests and also allow for the graphics logic to be multipurpose.
But Targowski et al. as modified by Rauchfuss et al. keep silent for teaching the plurality of semiconductor dies including a third semiconductor die that includes a high bandwidth memory (HBM).
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In related endeavor, Delacruz et al. teach a plurality of semiconductor dies and a plurality of die-to-die interconnects, the plurality of semiconductor dies comprising (Fig 5, abstract, par 0069-0070, “Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors…. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die): a die interface configurable to couple with one or more of a plurality semiconductor dies (Figs 1-2, and 4-5, abstract, par 006-008, par 0031- 0033, par 0045, par 0069-0072, par 0079; par 0081-0084, par 0094, par 0117-0118, “The active base die 108 uses chiplets 506 & 508 & 510 . . . n and communicatively connects them together”; par 0094, “the example native interconnection using an active base die 108 directly couples with native core-side interconnects 504, which are already natively present on the chiplet 506”; “The active base die receives native core-side signals from multiple diverse chiplets, and enables two-way communication between functional elements of the active base die and the attached chiplets “; “The native interconnects can be made during die-to-die or die-to-wafer direct-bonding that creates native interconnects between a first die, such as an active die or a chiplet, and a second die, which may be an active base die “; “The example microelectronics package 106 has functional blocks 110 & 204 & 206 coupled to the active base die 108 as chiplets, via the native interconnects 210 of the chiplets 110 & 204 & 206. The active base die 108 has incorporated functional block 202 into the active base die 108 as a purposeful part of the design “; “the example native interconnection using an active base die 108 directly couples with native core-side interconnects 504, which are already natively present on the chiplet 506”); the plurality of semiconductor dies including a second semiconductor die that includes a third cache memory (Fig 5, par 0071, par 0091, par 0118, “The active base die 108 can enable chiplets of various technologies to share one or more common memories, whereas conventionally each processor has its own dedicated coupled memory. The active base die 108 can allow external memory to be utilized as embedded memory with process sharing. In such a configuration, memory access does not need to proceed each time through a memory interface, such as the DBI bonds of the native interconnect 504 to attached chiplets 506 & 508 & 510 . . . n, but instead memory access can go straight through the active base die configuration”) and a third semiconductor die that includes a high bandwidth memory (HBM) (par 0052, “Example microelectronic device 430 includes chiplets 432 & 434 & 436 direct-bonded in a stack to an example active base die 108 of the same size or footprint as the chiplets 432 & 434 & 436. This example configuration of a microelectronic device 430 using the active base die 108 to host one or more memory controllers, for example, may be useful in fabricating or emulating various types of high bandwidth memory modules, such as DDR4 SDRAM, DDRS SDRAM, high bandwidth memory (HBM), hybrid memory cube (HMC), and so forth”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Targowski et al. as modified by Rauchfuss et al. to include the plurality of semiconductor dies including a third semiconductor die that includes a high bandwidth memory (HBM) as taught by Delacruz et al. to build direct-bonded native interconnects and active base dies to stack chiplets with same size and footprint to allow user to configure these chiplets for various type high bandwidth memory modules to build a minimal routing blockages to improve signal quality and timing.
But Targowski et al. as modified by Rauchfuss et al. and Delacruz et al. keep silent for teaching the die interface including an interconnect cache to cache data transmitted via the die interface.
In related endeavor, Ryan et al. teach the die interface including an interconnect cache to cache data transmitted via the die interface (Fig 1, par 0026-0027, “As is schematically shown in FIG. 1, the network-on-chip 14 is connected via a communication path 18 to a cache arrangement 12. This will be described in more detail later. The network-on-chip 14 is connected to an interface 6 via a communication path 20. The communication paths 18 and 20 may be interconnects”, Fig 2, par 0041-0045, “A first cache arrangement 12 is provided on a first die with a second cache arrangement 25 on a second die. The first cache arrangement has a cache memory 56 and a cache controller 54 for controlling the cache memory. The interconnect between the two dies is represented by reference numeral 43. Reference numeral 41 schematically represents the communication path between the cache arrangement 12 of the first die and the interconnect 43. This communication path may include the interface and/or any other circuitry between the cache arrangement 12 and the interconnect 43”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Targowski et al. as modified by Rauchfuss et al. and Delacruz et al. to include the die interface including an interconnect cache to cache data transmitted via the die interface as taught by Ryan et al. to provide data caching which exploits a property of data access known as temporal locality to accessible data more quickly and efficiently to increase the overall speed of data access.
Regarding claim 2, Targowski et al. as modified by Rauchfuss et al., Delacruz et al., and Ryan et al. teach all the limitation of claim 1, and Delacruz et al. further teach wherein the first semiconductor die and the one or more of the plurality of semiconductor dies couple with a package substrate via an interposer (Fig 1, par 0034, “FIG. 1 shows an example comparison between a conventional microelectronics package 100 with multiple conventional chiplets 102 on a conventional interposer 104, versus an example microelectronics package 106 rendered on an active base die 108, as described herein“, Fig 5, par 0069, par 0075-0076, “FIG. 5 shows an example active base die 108 as included within an example microelectronic device 502, such as an integrated circuit package 502. In an implementation, the native conductors 504 of dies, such as example chiplets 506 & 508 & 510 . . . n, connect directly to the active base die 108 instead of connecting to conventional components, such as industry standard interfaces 112, conventional interconnect layers, or passive interposers that conventionally connect chiplets and dies into a package”), and Ryan et al. further teach the die interface includes an interconnect buffer to temporarily store commands or data received via the interconnect fabric (par 0009-0010, “an input configured to receive a memory request from a second cache arrangement; a first cache memory for storing data; an output configured to provide a response to said memory request for said second cache arrangement ….. a second input configured to receive a response to said memory transaction; and a first cache arrangement comprising a first cache memory, a first cache controller, an input configured to receive said output from said second cache arrangement and an output configured to provide a response to said memory transaction to said second input of the second cache arrangement”, Fig 1, par 0026-0027, “As is schematically shown in FIG. 1, the network-on-chip 14 is connected via a communication path 18 to a cache arrangement 12. This will be described in more detail later. The network-on-chip 14 is connected to an interface 6 via a communication path 20. The communication paths 18 and 20 may be interconnects”, Fig 2, par 0041-0045, “A first cache arrangement 12 is provided on a first die with a second cache arrangement 25 on a second die. The first cache arrangement has a cache memory 56 and a cache controller 54 for controlling the cache memory. The interconnect between the two dies is represented by reference numeral 43. Reference numeral 41 schematically represents the communication path between the cache arrangement 12 of the first die and the interconnect 43. This communication path may include the interface and/or any other circuitry between the cache arrangement 12 and the interconnect 43”). This would be obvious for the same reason given in the rejection for claim 1.
Regarding claim 3, Targowski et al. as modified by Rauchfuss et al., Delacruz et al., and Ryan et al. teach all the limitation of claim 1, and Delacruz et al. further teach wherein the first semiconductor die and the one or more of the plurality of semiconductor dies of the multi-chip module have a 2.5-dimensional (2.5D) arrangement (par 0075, par 0087, par 0096, “DBI® (direct bond interconnect) hybrid bonding technology is applied. DBI bonding is currently available for fine-pitch bonding in 3D and 2.5D integrated circuit assembly, and can be applied to bond the native conductors 504 of the chiplets 506 & 508 & 510 . . . n to the active base die 108 (Ziptronix, Inc., an Xperi Corporation company, San Jose, Calif.)”). This would be obvious for the same reason given in the rejection for claim 1.
Regarding claim 4, Targowski et al. as modified by Rauchfuss et al., Delacruz et al., and Ryan et al. teach all the limitation of claim 1, and Delacruz et al. further teach wherein the first semiconductor die and the one or more of the plurality of semiconductor dies of the multi-chip module have a 3- dimensional (3D) arrangement (par 0075, par 0087, par 0096, “DBI® (direct bond interconnect) hybrid bonding technology is applied. DBI bonding is currently available for fine-pitch bonding in 3D and 2.5D integrated circuit assembly, and can be applied to bond the native conductors 504 of the chiplets 506 & 508 & 510 . . . n to the active base die 108 (Ziptronix, Inc., an Xperi Corporation company, San Jose, Calif.)”). This would be obvious for the same reason given in the rejection for claim 1.
Regarding claim 5, Targowski et al. as modified by Rauchfuss et al., Delacruz et al., and Ryan et al. teach all the limitation of claim 1, and further teach wherein the third cache memory of the second semiconductor die is accessible to the plurality of graphics processing resources of the first semiconductor die (Targowski et al.: par 0037, par 0048, “the processor 102 also uses an external cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC)) (not shown), which may be shared among processor cores 107 using known cache coherency techniques”, par 0043, “The internal cache units 204A-204N and shared cache units 206 represent a cache memory hierarchy within the processor 200. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, where the highest level of cache before external memory is classified as the LLC. In some embodiments, cache coherency logic maintains coherency between the various cache units 206 and 204A-204N”, par 0108, “a shared L3 cache 875 is available to all graphics components, allowing the sharing of data without the use of main system memory”, Rauchfuss et al.: par 0017-0018, “The cache 108 may store data (e.g., including instructions) that are utilized by one or more components of the processor 102-1, such as the cores 106. For example, the cache 108 may locally cache data stored in a memory 114 for faster access by the components of the processor 102 (e.g., faster access by cores 106). As shown in FIG. 1, the memory 114 may communicate with the processors 102 via the interconnection 104. In an embodiment, the cache 108 (that may be shared) may be a mid-level cache (MLC), a last level cache (LLC), etc. Also, each of the cores 106 may include a level 1 (L1) cache (116-1) (generally referred to herein as “L1 cache 116”) or other levels of cache such as a level 2 (L2) cache. Moreover, various components of the processor 102-1 may communicate with the cache 108 directly, through a bus (e.g., the bus 112), and/or a memory controller or hub”).
Regarding claim 6, Targowski et al. as modified by Rauchfuss et al., Delacruz et al., and Ryan et al. teach all the limitation of claim 5, and Delacruz et al. further teach wherein the second semiconductor die includes multiple dies associated with the third cache memory (Targowski et al.: par 0037, par 0048, “the processor 102 also uses an external cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC)) (not shown), which may be shared among processor cores 107 using known cache coherency techniques”, par 0043, “The internal cache units 204A-204N and shared cache units 206 represent a cache memory hierarchy within the processor 200. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, where the highest level of cache before external memory is classified as the LLC. In some embodiments, cache coherency logic maintains coherency between the various cache units 206 and 204A-204N”, par 0108, “a shared L3 cache 875 is available to all graphics components, allowing the sharing of data without the use of main system memory”, Rauchfuss et al.: Fig 1, par 0017-0018, “The cache 108 may store data (e.g., including instructions) that are utilized by one or more components of the processor 102-1, such as the cores 106. For example, the cache 108 may locally cache data stored in a memory 114 for faster access by the components of the processor 102 (e.g., faster access by cores 106). As shown in FIG. 1, the memory 114 may communicate with the processors 102 via the interconnection 104. In an embodiment, the cache 108 (that may be shared) may be a mid-level cache (MLC), a last level cache (LLC), etc. Also, each of the cores 106 may include a level 1 (L1) cache (116-1) (generally referred to herein as “L1 cache 116”) or other levels of cache such as a level 2 (L2) cache. Moreover, various components of the processor 102-1 may communicate with the cache 108 directly, through a bus (e.g., the bus 112), and/or a memory controller or hub”).
Regarding claim 7, Targowski et al. as modified by Rauchfuss et al., Delacruz et al., and Ryan et al. teach all the limitation of claim 1, and further teach wherein the second semiconductor die includes a memory controller coupled with the third cache memory, the memory controller to enable memory access on behalf of the plurality of graphics processing resources of the first semiconductor die (Targowski et al.: par 0037-0039, par 0042-0044, “FIG. 2 is a block diagram of an embodiment of a processor 200 having one or more processor cores 202A-202N, an integrated memory controller 214, and an integrated graphics processor 208. …. Each of processor cores 202A-202N includes one or more internal cache units 204A-204N. In some embodiments, each processor core also has access to one or more shared cached units 206”, par 0141, par 0150, “Storage may be provided by a flash memory subsystem 1260 including flash memory and a flash memory controller. Memory interface may be provided via a memory controller 1265 for access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 1270”, Rauchfuss et al.: Fig 1, par 0015, par 0017-0018, par 0046, “The cache 108 may store data (e.g., including instructions) that are utilized by one or more components of the processor 102-1, such as the cores 106. For example, the cache 108 may locally cache data stored in a memory 114 for faster access by the components of the processor 102 (e.g., faster access by cores 106). As shown in FIG. 1, the memory 114 may communicate with the processors 102 via the interconnection 104. In an embodiment, the cache 108 (that may be shared) may be a mid-level cache (MLC), a last level cache (LLC), etc. Also, each of the cores 106 may include a level 1 (L1) cache (116-1) (generally referred to herein as “L1 cache 116”) or other levels of cache such as a level 2 (L2) cache. Moreover, various components of the processor 102-1 may communicate with the cache 108 directly, through a bus (e.g., the bus 112), and/or a memory controller or hub”, Delacruz et al.: par 0052, “a microelectronic device 430 using the active base die 108 to host one or more memory controllers, for example, may be useful in fabricating or emulating various types of high bandwidth memory modules”).
Regarding claim 8, Targowski et al. as modified by Rauchfuss et al., Delacruz et al., and Ryan et al. teach all the limitation of claim 7, and Delacruz et al. further teach
wherein the second semiconductor die additionally includes a high bandwidth memory (HBM) (par 0052, “Example microelectronic device 430 includes chiplets 432 & 434 & 436 direct-bonded in a stack to an example active base die 108 of the same size or footprint as the chiplets 432 & 434 & 436. This example configuration of a microelectronic device 430 using the active base die 108 to host one or more memory controllers, for example, may be useful in fabricating or emulating various types of high bandwidth memory modules, such as DDR4 SDRAM, DDRS SDRAM, high bandwidth memory (HBM), hybrid memory cube (HMC), and so forth”). This would be obvious for the same reason given in the rejection for claim 1.
Regarding claim 9, Targowski et al. as modified by Rauchfuss et al., Delacruz et al., and Ryan et al. teach all the limitation of claim 1, and further teach wherein the third semiconductor die additionally includes a memory die associated with the third cache memory (Targowski et al.: par 0039, par 0048, “which facilitates communication between various processor components and a high-performance embedded memory module 218, such as an eDRAM module. In some embodiments, each of the processor cores 202A-202N and graphics processor 208 use embedded memory modules 218 as a shared Last Level Cache”, Rauchfuss et al.: Fig 1, par 0015, par 0017-0018, par 0046, “the processor 102-1 may include one or more processor cores 106-1 through 106-M (referred to herein as “cores 106,” or “core 106”), a cache 108, and/or a router 110. The processor cores 106 may be implemented on a single integrated circuit (IC) chip. Moreover, the chip may include one or more shared and/or private caches (such as cache 108), buses or interconnections (such as a bus or interconnection 112), graphics and/or memory controllers (such as those discussed with reference to FIGS. 6-8), or other components”, par 0052-0053, “The processors 702 and 704 may each include a local memory controller hub (MCH) 706 and 708 to enable communication with memories 710 and 712. The memories 710 and/or 712 may store various data such as those discussed with reference to the memory 612 of FIG. 6. … the processors 702 and 704 may each exchange data with a chipset 720 via individual PtP interfaces 722 and 724 using point-to-point interface circuits 726, 728, 730, and 732.”, Delacruz et al.: abstract, par 0052, “a microelectronic device 430 using the active base die 108 to host one or more memory controllers, for example, may be useful in fabricating or emulating various types of high bandwidth memory modules”).
Regarding claim 10, Targowski et al. as modified by Rauchfuss et al., Delacruz et al., and Ryan et al. teach all the limitation of claim 1, and further teach wherein the first cache memory is a level 1 (L1) cache memory, the second cache memory is a level 2 (L2) cache memory, and the third cache memory is a level 3 (L3) cache memory (Targowski et al.: par 0043, “The internal cache units 204A-204N and shared cache units 206 represent a cache memory hierarchy within the processor 200. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, where the highest level of cache before external memory is classified as the LLC”, Venishetti et al.: Fig 1, par 0017-0018, “the cache 108 (that may be shared) may be a mid-level cache (MLC), a last level cache (LLC), etc. Also, each of the cores 106 may include a level 1 (L1) cache (116-1) (generally referred to herein as “L1 cache 116”) or other levels of cache such as a level 2 (L2) cache. Moreover, various components of the processor 102-1 may communicate with the cache 108 directly, through a bus (e.g., the bus 112), and/or a memory controller or hub”).
Regarding claim 11, Targowski et al. as modified by Rauchfuss et al., Delacruz et al., and Ryan et al. teach all the limitation of claim 1, and Delacruz et al. further teach wherein the first semiconductor die couples with the second semiconductor die or the third semiconductor die (Fig. 5, par 0008, par 0045, par 0069-0072, “FIG. 5 shows an example active base die 108 as included within an example microelectronic device 502, such as an integrated circuit package 502. In an implementation, the native conductors 504 of dies, such as example chiplets 506 & 508 & 510 . . . n, connect directly to the active base die 108 instead of connecting to conventional components, such as industry standard interfaces 112, conventional interconnect layers, or passive interposers that conventionally connect chiplets and dies into a package”). This would be obvious for the same reason given in the rejection for claim 1.
Regarding claim 12, Targowski et al. as modified by Rauchfuss et al., Delacruz et al., and Ryan et al. teach all the limitation of claim 1, and Delacruz et al. further teach wherein the first semiconductor die couples with the second semiconductor die and the third semiconductor die (Fig. 5, par 0008, par 0045, par 0069-0072, “FIG. 5 shows an example active base die 108 as included within an example microelectronic device 502, such as an integrated circuit package 502. In an implementation, the native conductors 504 of dies, such as example chiplets 506 & 508 & 510 . . . n, connect directly to the active base die 108 instead of connecting to conventional components, such as industry standard interfaces 112, conventional interconnect layers, or passive interposers that conventionally connect chiplets and dies into a package”). This would be obvious for the same reason given in the rejection for claim 1.
Regarding claim 13, Targowski et al. as modified by Rauchfuss et al., Delacruz et al., and Ryan et al. teach all the limitation of claim 1, and Targowski et al. further teach wherein the graphics multiprocessor has a single instruction multiple thread (SIMT) architecture (par 0078, “Each of the execution units 608A-608N is capable of multi-issue single instruction multiple data (SIMD) execution and multi-threaded operation enables an efficient execution environment in the face of higher latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread-state”).
Regarding claim 14, Targowski et al. teach apparatus comprising: a memory device; and a multi-chip module (Fig 12, par 0140-0141, “Exemplary integrated circuit 1200 includes one or more application processor(s) 1205 (e.g., CPUs), at least one graphics processor 1210, and may additionally include an image processor 1215 and/or a video processor 1220, any of which may be a modular IP core from the same or multiple different design facilities. Integrated circuit 1200 includes peripheral or bus logic including a USB controller 1225, UART controller 1230, an SPI/SDIO controller 1235, and an I.sup.2S/I.sup.2C controller 1240. Additionally, the integrated circuit can include a display device 1245 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1250 and a mobile industry processor interface (MIPI) display interface 1255. Storage may be provided by a flash memory subsystem 1260 including flash memory and a flash memory controller. Memory interface may be provided via a memory controller 1265 for access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 1270”). The remaining limitations of the claim are similar in scope to claim 1 and rejected under the same rationale.
Regarding claims 15-20, Targowski et al. as modified by Rauchfuss et al., Delacruz et al., and Ryan et al. teach all the limitation of claim 14, the claims 15-20 are similar in scope to claims 2, 3+4, 5+6, 7, 8+9+11/12, and 10 and are rejected under the same rational.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jin Ge whose telephone number is (571)272-5556. The examiner can normally be reached 8:00 to 5:00.
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JIN . GE
Examiner
Art Unit 2619
/JIN GE/Primary Examiner, Art Unit 2619
