Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the amendment filed 5/11/2026 in which Claims 1-24 are pending.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 6, 21 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 2021/0336761 to Smith et al (“Smith”) in view of U.S. Patent Publication 2003/0161235 to Baba in further view of U.S. Patent Publication 2022/0329247 to van Ierssel et al (“van Ierssel”).
As to Claim 1, Smith teaches a receiver device comprising: an analog-to-digital converter (ADC) to sample an incoming signal to obtain samples (Sampler 121 samples analog data received via communication link 130...The ADC 122 converts sampled analog data to digital format, see ¶ 0029); and a signal processing circuit coupled to the ADC, wherein the signal processing circuit comprises an equalizer block, a phase detector block, and a jitter correction block (The DSP 123 further processes the received data-now in digital format after conversion by ADC 122. For example, DSP 123 may be configured to perform equalization, detection [phase detector block], error correction [jitter correction block], see ¶ 0029), wherein the jitter correction block is to: receive current data from the equalizer block (Figure 7 illustrates a jitter mitigation circuit 703 receiving data from EQ 702);
Smith does not expressly disclose determine a running sum value based on phase information received from the phase detector block; apply exclusively either a first gain value or a second gain value to the running sum value to obtain a phase correction value based on a sign of the running sum value, wherein the first gain value and the second gain value are different.
Baba teaches determine a running sum value based on phase information received from the phase detector block (The evaluator 25 [phase detector block] is for measuring PLL loop characteristics with a port "a" for outputting a sine wave for measurement, ports "b" and "c" for inputting signals before and after addition at the adder 22, see ¶ 0043; The evaluator 25 measures amplitude of 50 KHz component of each signal input to the ports "b" and "c". Ratio of measured amplitude of the port "c" to the port "b" (c/b) is a transfer gain of 50 KHz in loop-transfer characteristics of PLL, see ¶ 0045);
apply exclusively either a first gain value or a second gain value to the running sum value to obtain a phase correction value based on a sign of the running sum value, wherein the first gain value and the second gain value are different (The evaluator 25 outputs an inverse number of this transfer gain (inverse code with representation of dB) to the gain regulator 24. In this case, for example, if this transfer gain is -3 dB, this corresponds to the state of the curve "a" in FIG. 20 where a loop gain is low. The gain regulator 24 sets +3 dB in the gain 23 so as to make a transfer gain 0 dB. A gain set in the gain 23 is used for an operation of the multiplier 21. The multiplier 21 has a gain of +3 dB and multiplies it by an output from the phase difference detector 6, see ¶ 0046; a phase difference [phase correction value], which is an output from a phase difference detector 6, is used as a loop evaluation for PLL. Phase difference from the phase difference detector 6 is supplied to a jitter measuring device 26, which measures the jitter of a phase difference signal, see ¶ 0053; The jitter measuring device 26 measures the jitter of a phase difference at this moment, and an evaluator 25 stores the measured jitter. Next, for example, the gain regulator 24 sets -4 dB in the gain 23 [first gain value], and the evaluator 25 stores the jitter measured at the jitter measuring device 26 at this moment. The gain regulator 24 changes a gain to be set in the gain 23 like -6, -4, . . . , +2, +4 dB [first gain value] in this manner, and the evaluator 25 stores a jitter for each case in association with each set gain [apply first gain value to running sum value to obtain a phase correction value based on a sign of the running sum value], see ¶ 0054; As a gain set in the gain 23 changes like this, a jitter measured at the jitter measuring device 26 also changes as shown in FIG. 5, which results in the characteristic where the jitter increases at both the biggest end and the smallest end of the set gain [sign of the running sum value]. The evaluator 25 finds a gain crossing a reference jitter line (e.g., 5 ns) shown in FIG. 5 in the measured data and determines a set gain, see ¶ 0055. Figure 1 illustrates an evaluator that outputs a value to a gain regulator to apply a gain 23 to a multiplier which also receives an output from a phase difference detector. Only one gain value is applied and the second gain value being different from the first gain value will not be given patentable weight since “exclusively either the first gain value or the second gain value” requires a selection of gain values).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Smith with Baba to teach determine a running sum value based on phase information received from the phase detector block; apply either a first gain value or a second gain value to the running sum value to obtain a phase correction value based on a sign of the running sum value, wherein the first gain value and the second gain value are different. The suggestion/motivation would have been in order to compensate for phase difference (see Abstract).
Smith and Baba do not expressly disclose re-sample, using the phase correction value, the current data to obtain re-sampled data to reduce jitter in the current data.
Van Ierssel teaches re-sample, using the phase correction value, the current data to obtain re-sampled data to reduce jitter in the current data (Loop filter 150 filters phase-error signal phe to issue a phase-adjustment signal θ.sub.clk [phase correction value] to phase interpolator 155, which mixes clock signals of various phases from PLL 160 to phase adjust clock signal clk in a manner that reduces phase-error signal phe and thus aligns edges of clock signal clk with the incoming symbols, see ¶ 0013. Figure 1 illustrates the phase interpolator 155 receiving the phase adjustment signal and output a phase adjust clock signal clk to the error sampler 135, i.e. re-sampling using the phase correction value to obtain re-sampled data).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Smith and Baba with Van Ierssel to re-sample, using the phase correction value, the current data to obtain re-sampled data to reduce jitter in the current data. The suggestion/motivation would have been in order for accurate jitter detection (see ¶ 0022).
As to Claim 6, Smith, Baba and van Ierssel depend from Claim 1, Smith teaches wherein the equalizer block is to receive the samples from the ADC and output the current data based on the samples (Sampler 121 samples analog data received via communication link 130...The ADC 122 converts sampled analog data to digital format, see ¶ 0029),
wherein the signal processing circuit further comprises a clock recovery (CR) block comprising: the phase detector block with a timing error detector (TED) coupled to an output of the equalizer block (Figure 2 illustrates a TED 205 coupled to the output of FFE 202),
the TED to measure a sampling offset of the current data, the sampling offset to control sampling of subsequent data by the ADC (Block 205 includes a timing error detector (TED) and a loop filter (LF). The TED uses the outputs of error generator 204 and DET 203 to generate an indication of whether the sampling process is early or late [sampling offset], see ¶ 0037);
a first filter coupled to an output of the TED (Block 205 includes a timing error detector (TED) and a loop filter (LF), see ¶ 0037); and
a controlled oscillator (CO) coupled to an output of the first filter, wherein the CO is to control the sampling of the subsequent data by the ADC (Block 205 includes a timing error detector (TED) and a loop filter (LF). The TED uses the outputs of error generator 204 and DET 203 to generate an indication of whether the sampling process is early or late. The LF filters the TED output in order to generate a signal that controls the frequency of the clock generated by the DCO 206, see ¶ 0037).
As to Claim 21, Smith teaches a system for high-speed network communication, the system comprising: a processing unit; and a network interface coupled to the processing unit, wherein the network interface comprises a receiver device (Communication system 100 includes transmitter 110, receiver 120, and link 130. Transmitter 110 transmits data to receiver 120 via communication link 130. Receiver 120 includes sampler 121, analog to digital converter (ADC) 122, digital signal processor (123), see ¶ 0029. Examiner construes the communication link as the network interface coupled to the DSP [processing unit]),
wherein the receiver device comprises: an analog-to-digital converter (ADC) to sample an incoming signal to obtain samples (Sampler 121 samples analog data received via communication link 130...The ADC 122 converts sampled analog data to digital format, see ¶ 0029); and a signal processing circuit coupled to the ADC, wherein the signal processing circuit comprises an equalizer block, a phase detector block, and a jitter correction block (The DSP 123 further processes the received data-now in digital format after conversion by ADC 122. For example, DSP 123 may be configured to perform equalization, detection [phase detector block], error correction [jitter correction block], see ¶ 0029), wherein the jitter correction block is to: receive current data from the equalizer block (Figure 7 illustrates a jitter mitigation circuit 703 receiving data from EQ 702);
Smith does not expressly disclose determine a running sum value based on phase information received from the phase detector block; apply exclusively either a first gain value or a second gain value to the running sum value to obtain a phase correction value based on a sign of the running sum value, wherein the first gain value and the second gain value are different.
Smith does not expressly disclose determine a running sum value based on phase information received from the phase detector block; apply exclusively either a first gain value or a second gain value to the running sum value to obtain a phase correction value based on a sign of the running sum value, wherein the first gain value and the second gain value are different.
Baba teaches determine a running sum value based on phase information received from the phase detector block (The evaluator 25 [phase detector block] is for measuring PLL loop characteristics with a port "a" for outputting a sine wave for measurement, ports "b" and "c" for inputting signals before and after addition at the adder 22, see ¶ 0043; The evaluator 25 measures amplitude of 50 KHz component of each signal input to the ports "b" and "c". Ratio of measured amplitude of the port "c" to the port "b" (c/b) is a transfer gain of 50 KHz in loop-transfer characteristics of PLL, see ¶ 0045);
apply exclusively either a first gain value or a second gain value to the running sum value to obtain a phase correction value based on a sign of the running sum value, wherein the first gain value and the second gain value are different (The evaluator 25 outputs an inverse number of this transfer gain (inverse code with representation of dB) to the gain regulator 24. In this case, for example, if this transfer gain is -3 dB, this corresponds to the state of the curve "a" in FIG. 20 where a loop gain is low. The gain regulator 24 sets +3 dB in the gain 23 so as to make a transfer gain 0 dB. A gain set in the gain 23 is used for an operation of the multiplier 21. The multiplier 21 has a gain of +3 dB and multiplies it by an output from the phase difference detector 6, see ¶ 0046; a phase difference [phase correction value], which is an output from a phase difference detector 6, is used as a loop evaluation for PLL. Phase difference from the phase difference detector 6 is supplied to a jitter measuring device 26, which measures the jitter of a phase difference signal, see ¶ 0053; The jitter measuring device 26 measures the jitter of a phase difference at this moment, and an evaluator 25 stores the measured jitter. Next, for example, the gain regulator 24 sets -4 dB in the gain 23 [first gain value], and the evaluator 25 stores the jitter measured at the jitter measuring device 26 at this moment. The gain regulator 24 changes a gain to be set in the gain 23 like -6, -4, . . . , +2, +4 dB [first gain value] in this manner, and the evaluator 25 stores a jitter for each case in association with each set gain [apply first gain value to running sum value to obtain a phase correction value based on a sign of the running sum value], see ¶ 0054; As a gain set in the gain 23 changes like this, a jitter measured at the jitter measuring device 26 also changes as shown in FIG. 5, which results in the characteristic where the jitter increases at both the biggest end and the smallest end of the set gain [sign of the running sum value]. The evaluator 25 finds a gain crossing a reference jitter line (e.g., 5 ns) shown in FIG. 5 in the measured data and determines a set gain, see ¶ 0055. Figure 1 illustrates an evaluator that outputs a value to a gain regulator to apply a gain 23 to a multiplier which also receives an output from a phase difference detector. Only one gain value is applied and the second gain value being different from the first gain value will not be given patentable weight since “exclusively either the first gain value or the second gain value” requires a selection of gain values).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Smith with Baba to teach determine a running sum value based on phase information received from the phase detector block; apply either a first gain value or a second gain value to the running sum value to obtain a phase correction value based on a sign of the running sum value, wherein the first gain value and the second gain value are different. The suggestion/motivation would have been in order to compensate for phase difference (see Abstract).
Smith and Baba do not expressly disclose re-sample, using the phase correction value, the current data to obtain re-sampled data to reduce jitter in the current data.
Van Ierssel teaches re-sample, using the phase correction value, the current data to obtain re-sampled data to reduce jitter in the current data (Loop filter 150 filters phase-error signal phe to issue a phase-adjustment signal θ.sub.clk [phase correction value] to phase interpolator 155, which mixes clock signals of various phases from PLL 160 to phase adjust clock signal clk in a manner that reduces phase-error signal phe and thus aligns edges of clock signal clk with the incoming symbols, see ¶ 0013. Figure 1 illustrates the phase interpolator 155 receiving the phase adjustment signal and output a phase adjust clock signal clk to the error sampler 135, i.e. re-sampling using the phase correction value to obtain re-sampled data).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Smith and Santiccioli with Van Ierssel to re-sample, using the phase correction value, the current data to obtain re-sampled data to reduce jitter in the current data. The suggestion/motivation would have been in order for accurate jitter detection (see ¶ 0022).
Claim(s) 2, 22 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 2021/0336761 to Smith et al (“Smith”) in view of U.S. Patent Publication 2003/0161235 to Baba in further view of U.S. Patent Publication 2022/0329247 to van Ierssel et al (“van Ierssel”) and in further view of U.S. Patent Publication 2008/0191746 to Friedman et al (“Friedman”).
As to Claim 2, Smith, Santiccioli and van Ierssel depend from Claim 1, Smith and van Ierssel do not expressly disclose wherein the jitter correction block is further to add a static or semi-static offset value to the phase correction value before re-sampling the current data. Friedman teaches wherein the jitter correction block is further to add a static or semi-static offset value to the phase correction value before re-sampling the current data (the creation of new feedback loops for the optimization of phase-locked loops (PLL) static phase error and jitter performance is provided. Thus, the present system first enables the realization of an efficient way to automatically adjust the static phase error of a PLL, either to a minimum value or to a specific target mean value. This can be used during PLL operation, enabling the minimum or target phase error value [phase correction value] to be dynamically maintained. In another aspect, the present system enables the realization of an efficient way to automatically optimize the jitter performance of a PLL, see ¶ 0010; To enable the compensation of static phase offset, a sensing circuit that measures the offset is needed. This may be provided by employing an instantaneous phase error detector (IPED), which determines, with the arrival time of each reference clock, whether the phase offset is greater than or less than a delay, see ¶ 0045; Figure 7 illustrates IPED computing the static phase error prior to re-sampling at digital control logic 570).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Smith, Santiccioli and Van Ierssel with Friedman to teach wherein the jitter correction block is further to add a static or semi-static offset value to the phase correction value before re-sampling the current data. The suggestion/motivation would have been in order to optimize PLL jitter performance (see ¶ 0074).
As to Claim 22, Smith, Santiccioli and van Ierssel depend from Claim 21, Smith, Santiccioli and van Ierssel do not expressly disclose wherein the jitter correction block is further to add a static or semi-static offset value to the phase correction value before re-sampling the current data. Friedman teaches wherein the jitter correction block is further to add a static or semi-static offset value to the phase correction value before re-sampling the current data (the creation of new feedback loops for the optimization of phase-locked loops (PLL) static phase error and jitter performance is provided. Thus, the present system first enables the realization of an efficient way to automatically adjust the static phase error of a PLL, either to a minimum value or to a specific target mean value. This can be used during PLL operation, enabling the minimum or target phase error value [phase correction value] to be dynamically maintained. In another aspect, the present system enables the realization of an efficient way to automatically optimize the jitter performance of a PLL, see ¶ 0010; To enable the compensation of static phase offset, a sensing circuit that measures the offset is needed. This may be provided by employing an instantaneous phase error detector (IPED), which determines, with the arrival time of each reference clock, whether the phase offset is greater than or less than a delay, see ¶ 0045; Figure 7 illustrates IPED computing the static phase error prior to re-sampling at digital control logic 570).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Smith, Santiccioli and Van Ierssel with Friedman to teach wherein the jitter correction block is further to add a static or semi-static offset value to the phase correction value before re-sampling the current data. The suggestion/motivation would have been in order to optimize PLL jitter performance (see ¶ 0074).
Allowable Subject Matter
10. Claims 14-20 allowed.
11. Claims 3-5, 7-13, 23, 24 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
12. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EBONI N GILES whose telephone number is (571)270-7453. The examiner can normally be reached Monday - Friday 9 am - 6 pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, PATRICK EDOUARD can be reached at (571)272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EBONI N GILES/ Examiner, Art Unit 2622
/PATRICK N EDOUARD/ Supervisory Patent Examiner, Art Unit 2622
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