DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The prior art documents submitted by applicant in the Information Disclosure Statement filed on April 27, 2026 have all been considered and made of record (note the attached copy of form PTO-1449).
Drawings
Nine (9) sheets of drawings were filed on October 3, 2024 and have been considered by the examiner.
Specification
Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 9-10, and 14-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. (US 20230089433 A1), hereafter Li.
Regarding claim 1; Li teaches (see Figure 1A; Paragraphs [0054-0084]) a device (100) comprising:
a substrate (133) having a first attachment location (102) and a second attachment location (202);
a first photonic integrated circuit (PIC 102) mounted within the first attachment location (102);
a bridge (bridge die 202) mounted within the second attachment location (202); and
a first compute device (EIC 114) mounted on the substrate (133) and at least partially over the first attachment location (102) and the second attachment location (202; see Figure 1A, 114 overlaps both 102 and 202).
Regarding claim 2; Li teaches the device of claim 1. Li further teaches comprising a second compute device (XPU 118) mounted on the substrate (133) at least partially over the second attachment location (202; see Figure 1A, 118 overlaps 202), wherein the second compute device (118) is electrically connected to the first compute device (104) by the bridge (202; Paragraph [0067]).
Regarding claim 3; Li teaches the device of claim 1. Li further teaches (see Figure 1A) wherein the first compute device (114) includes at least one selected from the group consisting of a memory device and a processing device (EIC 114 may comprise transistors, amplifiers, microcontrollers, etc. Paragraph [0066]. Therefore, either memory devices or processing devices are taught).
Regarding claim 4; Li teaches the device of claim 1. Li further teaches (see Figure 1A) wherein a redistribution layer (Paragraph [0080]) is arranged between the first photonic integrated circuit (102) and the first compute device (114; Paragraph [0080] teaches a redistribution layer (RDL) anywhere between surfaces 170-1 and 170-2 to allow electrical connection between 102 and 114; layer 127 with electrical connections therethrough forms a redistribution layer), and wherein an optical fiber connection (optical connection 137; Paragraph [0054]) extends between a surface (170-2) of the substrate (133) and the first photonic integrated circuit (102).
Regarding claim 5; Li teaches the device of claim 1. Li further teaches (Paragraph [0071]) wherein the substrate (133) comprises at least one selected from the group consisting of glass and silicon (one example material for 133 is glass reinforced epoxy matrix materials (Paragraph [0071] which comprises glass).
Regarding claim 6; Li teaches the device of claim 1. Li further teaches (see Figure 1A) wherein the first photonic integrated circuit (102) includes a plug connector (optical surface component 140) configured to receive a bi-directional optical fiber (optical component 137; 137 is, for example, a waveguide which is capable of propagating light in either direction), wherein the bi-directional optical fiber (137; see Paragraph [0054] for more examples of optical components 137) is configured to transmit an incoming optical signal (via optical surface component 140; Paragraph [0054]) to the first photonic integrated circuit (102), and wherein the bi-directional optical fiber (137) is configured to transmit an outgoing optical signal (137 is, for example, a waveguide which is capable of propagating light in either direction) from the first photonic integrated circuit (102).
Regarding claim 9; Li teaches (see Figure 1A) a system comprising:
a substrate (133) having a first side (170-2) and a second side (170-1) opposite the first side (170-2), the first side (170-2) having a first attachment location (102) and a second attachment location (202);
a photonic integrated circuit (PIC 102) at least partially within the first attachment location (102);
a bridge (bridge 202) at least partially within the second attachment location (202);
a first compute device (IC 114) mounted on the first side (170-2) of the substrate (133); and
a first thermal via (conductive pillars 152 and interconnects 150 form a via) within the substrate (133), the first thermal via (152 and 150) extending from the second side (170-1) to the first attachment location (PIC 102; there are two pillars below PIC 102 to the second side 170-1 in Figure 1A).
Regarding claim 10; Li teaches the system of claim 9. Li further teaches (see Figure 1A) comprising a second compute device (XPU 118) mounted on the first side (170-2) of the substrate (133), wherein the second compute device (118) is coupled to the first compute device (114) via the bridge (202) within the bridge (202) at least partially within the second attachment location (202).
Regarding claim 14; Li teaches the system of claim 9. Li further teaches (see Figure 1A and Paragraph [0080]) comprising a redistribution layer (Paragraph [0080]) arranged between the photonic integrated circuit (102) and the first compute device (114; Paragraph [0080] teaches a redistribution layer (RDL) anywhere between surfaces 170-1 and 170-2 to allow electrical connection between 102 and 114; layer 127 with electrical connections therethrough forms a redistribution layer); and an optical fiber connection (137) extending between a surface of the first side (170-2) of the substrate (133) and a surface of the photonic integrated circuit (102; couples via optical surface component 140) parallel to the first side (170-2; see Figure 1A, 170-2 and 102 are substantially parallel).
Regarding claim 15; Li teaches the system of claim 9. Li further teaches (see Figure 1A) wherein the first compute device (EIC 114) is mounted at least partially over the first attachment location (102) and the second attachment location (202; see Figure 1A, 114 overlaps both 102 and 202 partially).
Regarding claim 16; Li teaches a method (see Figures 1A and 5A-5F and Paragraphs [0088-0094]) comprising: preparing a substrate (133); forming a first attachment location (102) and a second attachment location (202) within a first side (701-2) of the substrate (133); mounting a photonic integrated circuit (102) at least partially within the first attachment location (102; for example, pick-and-place, Paragraph [0090]); mounting a bridge (202) at least partially within the second attachment location (202; Paragraph [0090]); forming a redistribution layer (Paragraph [0080] teaches an RDL between surfaces 170-1 and 170-2 or at either surface; layer 127 with electrical connections therethrough forms a redistribution layer) on the first side (170-2) of the substrate (133); forming an open area in the redistribution layer (Paragraph [0080]) over the photonic integrated circuit (102); mounting a first compute device (114) on the redistribution layer (Paragraph [0080]), the first compute device (114) electrically connected to the photonic integrated circuit (102) and the bridge (202; Paragraph [0092]); mounting a second compute device (XPU 118) on the redistribution layer (Paragraph [0080]), the second compute device (118) electrically connected to the first compute device (114) via the bridge (202; Paragraph [0092]); and connecting an optical fiber (137; Paragraph [0093]) to the photonic integrated circuit (102) via the open area in the redistribution layer (Paragraph [0080]).
Regarding claim 17; Li teaches the method of claim 16. Li further teaches (see Figure 5B and Paragraph [0090]) wherein preparing the substrate (133) includes forming a thermal via (conductive pillars 152) and forming a through-substrate via (discussed in Paragraph [0090] but not shown).
Regarding claim 18; Li teaches the method of claim 16. Li further teaches (see Figure 1A) wherein the optical fiber (137) connects to a surface (via optical surface component 140) of the photonic integrated circuit (102) parallel to the first side (170-2) of the substrate (133).
Regarding claim 19; Li teaches the method of claim 16. Li further teaches (see Figure 1A) wherein the first compute device (114) comprises at least a first device and at least a second device, wherein the first device and the second device include at least one of a processing device and a memory device (EIC 114 may comprise transistors, amplifiers, microcontrollers, etc. Paragraph [0066]. Therefore, both memory devices and processing devices are taught).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Lee et al. (US 20150194413 A1), hereafter Lee.
Regarding claims 7 and 13; Li teaches the device of claim 1 and the system of claim 9. Li further teaches (see Figure 1A) a thermal via (conductive pillar 152 and interconnect 150 form a via) formed between the first attachment location (PIC 102) and a surface of the substrate (133; Paragraph [0070] also describes through-substrate-vias (TSVs) through PIC 102)
Li does not teach a fluid cooling channel formed within the substrate nor that the thermal via couples the PIC to the fluid cooling channel. However, in the same field of endeavor, Lee teaches (see Figures 2C and 4) a fluid cooling channel (402; Paragraph [0042]) formed within the substrate (204C) and wherein the thermal vias (218C and 220C) thermally couple the PIC (208C) to the fluid cooling channel (402). It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the package structure of the device taught by Li to include the fluid cooling channel taught by Lee and further to couple the PIC to the fluid cooling channel using the thermal vias already present in Li. One of ordinary skill in the art would have been motivated to include the fluid cooling channel and couple the photonic integrate circuit to the fluid cooling channel to improve thermal management of the package structure.
Claims 8 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Li.
Regarding claim 8; Li teaches the device of claim 1. Li does not teach wherein the bridge is a second photonic integrated circuit, however it would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to use a photonic integrated circuit as the bridge die in the device taught by Li. The bridge die taught by Li is a generic die used as a connection between XPU 118 and EIC 114. One of ordinary skill in the art would have been motivated to make the bridge die a photonic integrated circuit to further connect the XPU 118 and EIC 114 optically.
Regarding claims 11-12; Li teaches the system of claim 9. Li further teaches (see Figure 1A) a first thermal via (see rejection to claim 9 above) and a second thermal via (150 and 152) within the substrate (133), wherein the second thermal via (150 and 152) extends from the second side (170-1) to the second attachment location (202; there are two pillars 152 and interconnects 150 below bridge 202).
Li does not explicitly teach an attach film between the first or second thermal vias and the photonic integrated circuit or bridge die. However, Li does teach a “die attach film” in Paragraph [0095] and uses the generic “attaching bridge die 202 and PIC 102 to short pillars 153” in Paragraph [0090]. It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to use attach film to attach the conductive pillars which act as thermal vias to the PIC and bridge die. One of ordinary skill in the art would have been motivated to attach the pillars to the PIC/bridge die to promote good electrical and thermal coupling.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Li in view of von Koblinski et al. (US 20150243591 A1), hereafter von Koblinski.
Regarding claim 20; Li teaches the method of claim 16. Li does not teach wherein forming the first attachment location and the second attachment location within the first side of the substrate comprises laser milling a glass substrate. However, in the same field of endeavor, von Koblinski teaches (see Paragraph [0057]) that “The openings 115, 116 of the second glass substrate 110 can also be wet-chemically formed using a mask. Alternatively, laser milling can be used” (Paragraph [0057]). It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the attachment locations in the package structure taught by Li using laser milling as taught by von Koblinski. One of ordinary skill in the art would have recognized the teachings of von Koblinski as an alternative method for creating the attachment locations and been motivated to use laser milling over deposition techniques because von Koblinski teaches that laser milling reduces manufacturing times compared to deposition techniques (Paragraph [0003]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER L KAULFUSS whose telephone number is (571)270-7260. The examiner can normally be reached Monday-Friday, 9 AM to 5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at (571)272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/P.L.K./Examiner, Art Unit 2874
/MICHELLE R CONNELLY/Primary Examiner, Art Unit 2874
