Prosecution Insights
Last updated: October 27, 2026
Application No. 18/906,185

CMOS DEVICE WITH MULTIPLE CHANNELS VERTICALLY STACKED

Non-Final OA §103
Filed
Oct 04, 2024
Priority
Oct 11, 2023 — RE 10-2023-0134899
Examiner
ULLAH, ELIAS
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Uif (university Industry Foundation), Yonsei University
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
734 granted / 863 resolved
+17.1% vs TC avg
Moderate +8% lift
Without
With
+7.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
26 currently pending
Career history
892
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
35.9%
-4.1% vs TC avg
§102
53.1%
+13.1% vs TC avg
§112
7.4%
-32.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 863 resolved cases

Office Action

§103
DETAILED ACTION Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-2 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Ho et al. (Ho, US 2009/0256149) in view of Shen et al. (Shen, US 2021/0359099 A1). Regarding claims 1 and 2, Ho teaches a ternary CMOS device comprising: a common gate terminal (common control gate in [0030]) configured such that an input voltage is applied to the common gate terminal ([0030]); and two MOSFET regions (MOSFET array 16 in FGI. 3A and [0030]), a common drain terminal ( common drain in [0030]); and a source terminal ( source body column share a common body in [0030]). Ho fails teach a two-dimensional phase change material layer formed of a two-dimensional phase change material; a two-dimensional semiconductor material layer formed of a two-dimensional semiconductor material having a characteristic of changing into a conductor by a voltage change without separate doping and stacked on either a top or bottom of the two-dimensional phase change material layer. Shen teaches a two-dimensional phase change material layer formed of a two-dimensional phase change material; a two-dimensional semiconductor material layer formed of a two-dimensional semiconductor material having a characteristic of changing into a conductor by a voltage change without separate doping and stacked on either a top or bottom of the two-dimensional phase change material layer ([006]) and wherein the two-dimensional phase change material layer is configured to allow a constant current to flow (underlined limitations considered as function of the Ho’s MOSFET) between the common drain terminal and the source terminal regardless of a magnitude of a voltage applied to the common gate terminal. At the time the invention was made, it would have been obvious to a person having ordinary skill in the art to use a two dimensional phase change material layer, because it would have reduced the contact resistance at the contact interfaces as taught by Shen in ([0006]). Regarding claims 7-8, Ho teaches a ternary CMOS device comprising a first oxide material layer (insulated gate in [0028]) stacked between the two-dimensional semiconductor material layer and the common gate terminal ([0030]) to be positioned between the two-dimensional semiconductor material layer (see claim 1 discussions) and the common gate terminal ([0030]). Allowable Subject Matter Claims 3-6 and 9-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ELIAS ULLAH/ Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Oct 04, 2024
Application Filed
Oct 02, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12772877
PACKAGING ARCHITECTURE WITH TRENCH VIA ROUTING FOR ON-PACKAGE HIGH-SPEED INTERCONNECTS
4y 4m to grant Granted Oct 20, 2026
Patent 12772685
ORGANIC ELECTROLUMINESCENT ELEMENT, ORGANIC ELECTROLUMINESCENT DISPLAY APPARATUS, AND ELECTRONIC DEVICE
2y 7m to grant Granted Oct 20, 2026
Patent 12772898
SEMICONDUCTOR PACKAGING WITH TRANSPARENCY AND METHOD OF MANUFACTURING THE SAME
3y 3m to grant Granted Oct 20, 2026
Patent 12772906
PACKAGING STRUCTURE AND PACKAGING METHOD
3y 0m to grant Granted Oct 20, 2026
Patent 12772453
LOGIC AND MEMORY DEVICE WITH COMMON VERTICAL CHANNEL
3y 0m to grant Granted Oct 20, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
93%
With Interview (+7.7%)
2y 4m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 863 resolved cases by this examiner. Grant probability derived from career allowance rate.

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