DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “close to” in claims 1, 2, & 10 is a relative term which renders the claim indefinite. The term “close to” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. What defines “close to?” Is 1 meter “close to?” Is 1cm “close to?” Is 1mm “close to?” Is 1µm “close to?” Clarification is required. Independent claim 1 and all subsequent dependent claims are rejected because of this 112 2nd rejection.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Independent claim 1 requires a “test device for an optoelectronic integrated circuit before being co-packaged, the optoelectronic integrated circuit comprising a stack of a first photonic die and a first electronic integrated circuit, and the test device electrically connected to automatic test equipment and comprising … the test board.” What has to happen or has to be “before being co-packaged?” Is the testing being done “before being co-packaged?” What is “before being co-packaged?” The wording of the claim makes it unclear whether a task is to be performed or a device needs to be present “before being co-packaged.” Although the specification does address the topic, the claim is unclear. Clarification is required. Independent claim 1 and all subsequent dependent claims are rejected because of this 112 2nd rejection.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 requires “the first optical transmission assembly and the second optical transmission assembly are configured to send a test light signal to the first photonic die or receive a light output signal generated by the first photonic die.” This limitation does not specify which unit does which task. As written, it can be interpreted to mean that the first optical transmission assembly transmits while the second optical transmission assembly receives. It could mean that the first optical transmission assembly receives while the second optical transmission assembly transmits. It could mean that the first optical transmission assembly and the second optical transmission assembly simultaneously do both tasks of transmission and reception. Clarification is required. All subsequent dependent claims are also rejected.
Claims 2 & 2-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
There exists two distinct claims labeled as claim 2. This error creates further dependency problems throughout the claims set. In particular, claims 5 & 8 depend from claim 2 which is an unknown because it is not understood which claim 2 is being referenced. Claims 5 & 8 are therefore rejected for improper dependencies. It is also noted that it is not clear exactly how many claims are really being prosecuted, 14 or 15, because of the two claim 2’s.
Claims 3 & 10 depend from themselves, which is in error. A claim cannot depend from itself. Claim 4 depends from claim 3, which depends from itself. Claims 11 & 12 depend from claim 10 which depends from itself. Therefore, claims 1, 11, & 12 are rejected for improper and problematic dependencies.
Any claims dependent from any other claim other than claim 1 is in error because it is not clear to which claim those claims would depend. Therefore claims labeled as claims 3-5, 8, & 10-12 have unknown dependency.
Allowable Subject Matter
Claims 1-14 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter: the prior art listed does not anticipate alone or combine in an obvious manner to teach the invention claimed by applicant. The specific structural and functional limitations disclosed have not been anticipated in any single reference in the prior art of record. Further, the use of impermissible hindsight would be required even if the limitations were to be found because of the exacting manner in which they would have to be combined.
Regarding Independent claim 1, teaches:
A test device for an optoelectronic integrated circuit before being co-packaged, the optoelectronic integrated circuit comprising a stack of a first photonic die and a first electronic integrated circuit, and the test device electrically connected to automatic test equipment and comprising:
a first jig comprising a first base, a cover plate, and a plurality of first conductor elements, wherein the first base comprises a first bottom plate and a first side wall, the cover plate covers a top of the first base and forms an accommodation space with the first bottom plate and the first side wall, the first photonic die is disposed in the accommodation space, and a plurality of through holes are positioned in the first bottom plate;
a first optical transmission assembly comprising a first end portion positioned in the accommodation space and close to the first photonic die;
a second optical transmission assembly comprising a second end portion positioned in the accommodation space and close to the first photonic die, wherein the first optical transmission assembly and the second optical transmission assembly are configured to send a test light signal to the first photonic die or receive a light output signal generated by the first photonic die;
an interposer disposed on a side of the first bottom plate, wherein the first conductor elements are arranged at intervals and pass through corresponding via holes included in the interposer and the first bottom plate, and are electrically connected between the first photonic die and the first electronic integrated circuit; a test load board electrically connected to the automatic test equipment; and
a second jig disposed on the test load board and comprising a second base and a plurality of first signal conductors, wherein the second base comprises a second bottom plate, a second side wall, and a groove portion, the groove portion is located between the second side wall and the second bottom plate, the first jig and the second jig are arranged up and down in a direction perpendicular to the test load plate, the first electronic integrated circuit is disposed in the groove portion, and the first signal conductors pass through the second bottom plate and are electrically connected between the first electronic integrated circuit and the test load board.
Regarding claim 2,
The test device for the optoelectronic integrated circuit before being co- packaged of claim 1, wherein the optoelectronic integrated circuit further comprises a second electronic integrated circuit, the first jig further comprises a plurality of second signal conductors, and the second electronic integrated circuit is arranged on the interposer and located in the accommodation space, wherein the second signal conductors are arranged at intervals and pass through the corresponding through holes of the first bottom plate, and are electrically connected between the interposer and the first electronic integrated circuit.
Regarding claim 2,
The test device for the optoelectronic integrated circuit before being co- packaged of claim 1, wherein the optoelectronic integrated circuit further comprises a second photonic die, the first jig further comprises a plurality of second conductor elements, and the test device further comprises another first optical transmission assembly and another second optical transmission assembly, wherein the second photonic die is disposed in the accommodation space, the another first optical transmission assembly and the another second optical transmission assemblies are disposed in the accommodation space and close to the second photonic die, respectively, wherein the second conductor elements are arranged at intervals and pass through the corresponding via holes of the interposer and the first bottom plate and are electrically connected between the second photonic die and the first electronic integrated circuit.
Regarding claim 3,
The test device for the optoelectronic integrated circuit before being co- packaged of claim 3, wherein the first jig further comprises a retaining element disposed on a side of the first side wall or the cover plate, and the first photonic die and/or the second photonic die are fixed on the retaining element and suspended in the accommodation space.
Regarding claim 4,
The test device for the optoelectronic integrated circuit before being co- packaged of claim 3, wherein the first jig further comprises a first elastic buffer element, which is disposed on a side of the cover plate and pressed against the first photonic die and the second photonic die.
Regarding claim 5,
The test device for the optoelectronic integrated circuit before being co- packaged of claim 2, wherein the first jig further comprises a first elastic buffer element, which is disposed on a side of the cover plate and pressed against the first photonic die and the second electronic integrated circuit.
Regarding claim 6,
The test device for the optoelectronic integrated circuit before being co- packaged of claim 1, wherein the first jig further comprises a second elastic buffer element, which is disposed on a side of the interposer and is pressed against the first electronic integrated circuit.
Regarding claim 7,
The test device for the optoelectronic integrated circuit before being co- packaged of claim 1, further comprising a first connecting member and a second connecting member, and the first connecting member is detachably connected to the second connecting member to connect and fix the first jig and the second jig to the test load board.
Regarding claim 8,
The test device for the optoelectronic integrated circuit before being co- packaged of claim 2, wherein the first electronic integrated circuit comprises a first packaging structure, and the second electronic integrated circuit comprises a second packaging structure.
Regarding claim 9,
The test device for the optoelectronic integrated circuit before being co- packaged of claim 1, wherein the first side wall is arranged around the first bottom plate and the accommodation space, and the first optical transmission assembly further comprises a first optical fiber, a first plug, and a first connector, wherein the first connector is disposed on the first side wall, the first optical fiber comprises the first end portion, and the first plug is fixed on the first end portion and pluggably connected to the first connector.
Regarding claim 10,
The test device for the optoelectronic integrated circuit before being co- packaged of claim 10, wherein the first photonic die comprises a first optical waveguide, the first optical fiber is aligned with the first optical waveguide, and the first end portion is disposed close to the first optical waveguide.
Regarding claim 11,
The test device for the optoelectronic integrated circuit before being co- packaged of claim 10, wherein the first photonic die comprises a first optical waveguide, and the first connector of the first optical transmission assembly comprises an optical channel and a reflective wall, wherein the reflective wall is located at an acute angle with respect to the first optical fiber and the first photonic die, the test light signal is reflected to the first optical waveguide through the reflective wall, or the light output signal is reflected through the reflective wall to the first end portion.
Regarding claim 12,
The test device for the optoelectronic integrated circuit before being co- packaged of claim 10, wherein the first photonic die comprises a first optical waveguide, the first connector of the first optical transmission assembly comprises an optical channel, and the cover plate comprises a slot comprising an inclined portion, wherein the inclined portion includes a reflective material with a reflection coefficient greater than that of air and is located at an acute angle with respect to the first optical fiber and the first bottom plate, a part of the first connector is embedded in the slot, and the optical channel extends to the inclined portion, wherein the test light signal is reflected to the first optical waveguide through the inclined portion, or the light output signal is reflected to the first end portion through the inclined portion.
Regarding claim 13,
The test device for the optoelectronic integrated circuit before being co- packaged of claim 1, wherein the first photonic die comprises a second optical waveguide, and the second optical transmission assembly comprises a second optical fiber, a second plug, and a second connector, wherein the second optical fiber comprises the second end portion, the second connector is obliquely embedded in the cover plate, the second plug is fixed to the second end portion and is pluggably connected to the second connector, and the second end portion is located above the second optical waveguide.
Regarding claim 14,
The test device for the optoelectronic integrated circuit before being co- packaged of claim 1, further comprising a third optical transmission assembly comprising a third optical fiber, a third plug, a third connector, and an interconnecting optical fiber, wherein the third connector is embedded in the first bottom plate, the third optical fiber comprises a third end portion, the third plug is fixed to the third end portion and is pluggably connected to the third connector, one end of the interconnecting optical fiber is connected to the third connector, and the other end is connected to the first photonic die.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art listed but not cited represents the previous state of the art and analogous art that teaches some of the limitations claimed by applicant. The best references found by the examiner are to Winzer (U.S. PGPub # 2023/0077979) and to Taha et al (U.S. PGPub # 2023/0084003). Both of these address testing optoelectronic integrated circuits simultaneously. Both disclose similar structural arrangements. But none have all of the specific structural and functional limitations and the respective connections between all of the structural elements. Therefore, they represent the best references that cannot reject the limitations presented by applicant.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER P MCANDREW whose telephone number is (469)295-9025. The examiner can normally be reached Monday-Thursday 6-4:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee Rodak can be reached on 571-270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER P MCANDREW/Primary Examiner, Art Unit 2858
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