DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action is in response to amendment filed 2/11/2026. Accordingly, claims 7 and 15 were canceled, and claims 21 and 22 were added. Thus, claims 1-6, 8-14 and 16-22 are pending for examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Benisty et al. (US 2022/0229566 A1, hereinafter Benisty) in view of Arora et al. (US 2015/0121057 A1, hereinafter Arora).
Regarding claim 1, Benisty discloses a flash storage device (figure 1, 110) comprising: an array of memory cells ([0026], a plurality of NVM cells); and a controller (figure 1, 108) configured to access the array of memory cells ([0024], a memory unit of NVM 110 may receive data and a message from the controller 108 that instructs the memory unit to store the data or to retrieve data), wherein the controller is further configured to: generate a representation of a current idle time having a first value in response to the current idle time being less than a threshold time and having a second value in response to the current idle time being greater than the threshold time; maintain a current sequence of a predetermined number of previous idle time representations (figure 5 and [0050]-[0052], threshold calculator 152 calculates the recommended idle time threshold and a confidence level based on the analyzed history of previous idle timeouts so that the idle time threshold for the next idle timeout prediction operation is set to the calculated recommended idle time threshold if the confidence level is sufficient enough, else the idle time threshold is set to 0). Benisty differs from the claimed invention in not specifically disclosing the controller configured to maintain a plurality of counter pairs, each counter pair corresponding to a different potential sequence of the predetermined number of previous idle time representations; increment a first counter of the counter pair corresponding to the current sequence in response to the current idle time having the first value and increment a second counter of the counter pair corresponding to the current sequence in response to the current idle time having the second value; and predict whether a subsequent idle time will be less than the threshold time, greater than the threshold time, or indeterminate based on the current sequence and the counter pair corresponding to the current sequence. However, Arora teaches a controller, using an idle duration history, predicts a duration of a next idle period for the entity in order to improve operation of computing device having idle period counters (figure 4, 402) to maintain a plurality of counter pairs, each counter pair corresponding to a different potential sequence of the predetermined number of previous idle time representations; increment a first counter of the counter pair corresponding to the current sequence in response to the current idle time having the first value and increment a second counter of the counter pair corresponding to the current sequence in response to the current idle time having the second value ([0049]-[0050], microcontroller 200 compares the duration of the idle period that has ended for the entity to a threshold to determine if the idle period was long, updates the prediction 402 by incrementing the counter for the prediction 402, otherwise, microcontroller 200 decrements the counter for the prediction 402 if the idle period was short), and predict whether a subsequent idle time will be less than the threshold time, greater than the threshold time, or indeterminate based on the current sequence and the counter pair corresponding to the current sequence ([0071]-[0072], microcontroller 200 causes core 102 to transition to the first idle state during the next idle period if the predicted duration of the idle period is longer than the threshold duration, and microcontroller 200 causes core 102 to transition to the second idle state during the next idle period if the predicted duration of the idle period is shorter than the threshold duration). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Benisty in having the controller configured to maintain a plurality of counter pairs, each counter pair corresponding to a different potential sequence of the predetermined number of previous idle time representations; increment a first counter of the counter pair corresponding to the current sequence in response to the current idle time having the first value and increment a second counter of the counter pair corresponding to the current sequence in response to the current idle time having the second value; and predict whether a subsequent idle time will be less than the threshold time, greater than the threshold time, or indeterminate based on the current sequence and the counter pair corresponding to the current sequence, as per teaching of Arora, in order to improve operation of computing device.
Regarding claim 2, Benisty discloses that the controller is further configured to generate the representation of the current idle time to have the first value in response to the current idle time being equal to the threshold time ([0046], the timer 150 begins counting towards the idle time threshold).
Regarding claim 3, Benisty differs from the claimed invention in not specifically teaching that the controller is further configured to predict the subsequent idle time will be less than the threshold time in response to a count of the first counter being greater than a count of the second counter by a threshold value for the counter pair corresponding to the current sequence, predict the subsequent idle time will be greater than the threshold time in response to the count of the second counter being greater than the count of the first counter by the threshold value for the counter pair corresponding to the current sequence, and predict the subsequent idle time will be indeterminate in response to the count of the first counter being within the threshold value of the count of the second counter for the counter pair corresponding to the current sequence. However, Arora teaches a controller configured to predict the subsequent idle time will be less than the threshold time in response to a count of the first counter being greater than a count of the second counter by a threshold value for the counter pair corresponding to the current sequence, predict the subsequent idle time will be greater than the threshold time in response to the count of the second counter being greater than the count of the first counter by the threshold value for the counter pair corresponding to the current sequence, and predict the subsequent idle time will be indeterminate in response to the count of the first counter being within the threshold value of the count of the second counter for the counter pair corresponding to the current sequence ([0070]-[0072], microcontroller 200 causes core 102 to transition to the first idle state during the next idle period if the predicted duration of the idle period is longer than the threshold duration, and microcontroller 200 causes core 102 to transition to the second idle state during the next idle period if the predicted duration of the idle period is shorter than the threshold duration). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Benisty in having that the controller is further configured to predict the subsequent idle time will be less than the threshold time in response to a count of the first counter being greater than a count of the second counter by a threshold value for the counter pair corresponding to the current sequence, predict the subsequent idle time will be greater than the threshold time in response to the count of the second counter being greater than the count of the first counter by the threshold value for the counter pair corresponding to the current sequence, and predict the subsequent idle time will be indeterminate in response to the count of the first counter being within the threshold value of the count of the second counter for the counter pair corresponding to the current sequence, as per teaching of Arora, in order to improve operation of computing device.
Allowable Subject Matter
Claims 8-14 and 16-22 are allowed.
Claims 4-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 2/11/2026 have been fully considered but they are not persuasive.
In response to applicant's argument that the references fail to show "increment a first counter of the counter pair corresponding to the current sequence in response to the current idle time having the first value and increment a second counter of the counter pair corresponding to the current sequence in response to the current idle time having the second value", Examiner respectfully disagreed. It is noted that Arora teaches record may store metadata with one or more idle period counters ([0029]) and microcontroller 200 maintains a history table that is used to predict idle period durations such that each prediction 402 is a 2-bit saturating counter, so that each prediction 402 has four possible states ([0045]-[0046]). Thus, Arora teaches the controller configured to maintain a plurality of counter pairs, each counter pair corresponding to a different potential sequence of the predetermined number of previous idle time representations. In addition, Arora teaches increment a first counter of the counter pair corresponding to the current sequence in response to the current idle time having the first value and increment a second counter of the counter pair corresponding to the current sequence in response to the current idle time having the second value ([0049]-[0050], microcontroller 200 compares the duration of the idle period that has ended for the entity to a threshold to determine if the idle period was long, updates the prediction 402 by incrementing the counter for the prediction 402, otherwise, microcontroller 200 decrements the counter for the prediction 402 if the idle period was short); and predict whether a subsequent idle time will be less than the threshold time, greater than the threshold time, or indeterminate based on the current sequence and the counter pair corresponding to the current sequence ([0071]-[0072], microcontroller 200 causes core 102 to transition to the first idle state during the next idle period if the predicted duration of the idle period is longer than the threshold duration, and microcontroller 200 causes core 102 to transition to the second idle state during the next idle period if the predicted duration of the idle period is shorter than the threshold duration). Therefore, the combination of Benisty and Arora teaches the broad claimed limitations of claim 1. For the same reasons as stated above, claims 2-3 are also rejected.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHUO H LI whose telephone number is (571)272-4183. The examiner can normally be reached Mon. Tue. and Thurs. 8:00-4:00 PM.
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/ZHUO H LI/Primary Examiner, Art Unit 2133
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