DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation “the first timing” in lines 8-9. There is insufficient antecedent basis for this limitation in the claim. There is no prior original recitation of “the first timing”. Claim 1 provides an original recitation of a “first timing signal”.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,154,659. Although the claims at issue are not identical, they are not patentably distinct from each other because the application claims are anticipated by, or obvious variants of, the patent claims.
Application claims 1-20 are each anticipated by patent claims 1-20, respectively. The claims are not identical because the application claims recite first and second timing signals at a first and second frequency, whereas the patent claims recite that the timing signals are synchronized with a respective first and second clock having different frequencies. However, this merely represents an obvious variant over the language in the patent claims. The application claims otherwise recite the same limitations as the patent claims.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 and 10 of U.S. Patent No. 11,830576 in view of Desai et al., U.S. Patent Application Publication No. 2017/0083461.
Application claims 1-20 are anticipated by the ‘576 patent claims 1-7 and 10 based on reasoning similar to the claims of the claims of the ‘659, i.e., variant language with respect to the timing signals. The ‘576 patent claims also exhibit variant language with respect to the application claims in that application claims 11-20 are directed to a method that performs the same functions as the system of the patent claims.
The ‘576 patent claim 1 recites a memory system comprising:
a memory chip; and
a memory controller configured to:
transfer, in a write operation,
a first timing signal synchronized with a first clock and
first data synchronized with the first timing signal to the memory chip; and
transfer, in a read operation,
a command synchronized with the first clock to the memory chip, an address synchronized with the first clock to the memory chip, and then a second timing signal synchronized with at least a second clock to the memory chip, the second clock having a frequency different from a frequency of the first clock,
wherein in the read operation, the memory chip is configured to generate a third timing signal synchronized with the second clock based on the second timing signal, and transfer the third timing signal and second data synchronized with the third timing signal to the memory controller.
The ‘576 patent claim 1 does not recite transferring a first command to the memory chip in a write operation.
Desai teaches transferring a first command to a memory chip in a write operation [para. 0002: “A memory controller for external dynamic random access memory (DRAM) must meet certain strict timing relationships as required, for example, under the Joint Electron Device Engineering Council (JEDEC) standards. For example, the memory controller must satisfy the write latency (WL) requirement between the write data (DQ) to be written to the DRAM and the corresponding command and address (CA) signals. In other words, a DRAM cannot receive the write data in the same memory clock cycle over which the DRAM receives a write command. Instead, the write data is presented the write latency number of clock cycles after the presentation of the write command.”].
It would have been obvious to one of ordinary skill in the art to combine the teachings of the ‘576 patent claims and Desai by modifying the ‘576 patent claims to include a step of transferring a first command to the memory chip during a write operation, as suggested by Desai. Desai discloses a write transaction as specified by the JEDEC standard includes a write commend followed by write data. The ’56 patent clams recite a write operation, including timing and data signals, without explicit recitation of a write command. However, it would have been obvious to include a write command based on Desai’s teaching that such a command would have adhered to an industry standard.
The claims of the ‘576 patent in combination with Desai correspond to the application claims in the following manner:
Application Claims
Patent Claims
1, 11
1
2, 12
2
3, 13
3
4 ,14
4
5, 15
5
6, 16
6
7, 17
1
8, 18
7
9, 19
7
10, 20
10
Conclusion
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/JI H BAE/Primary Examiner, Art Unit 2176 U.S. Patent and Trademark Office
Phone: 571-272-7181
Fax: 571-273-7181
ji.bae@uspto.gov