Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-8, 12-15, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kevin Cheng, Spoorti Doddamani, Tzi-Cker Chiueh, Yongheng Li, and Kartik Gopalan. 2020. Directvisor: Virtualization for Bare metal Cloud. In ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (VEE ’20), March 17, 2020, Lausanne, Switzerland. ACM, New York, NY, USA, 14 pages (hereafter Cheng) in view of Madukkarumukumana et al. Pub. No. US 2013/0232288 A1 (hereafter Madukkarumukumana) and Raisch et al. Pub. No. US 2020/0264912 A1 (hereafter Raisch).
Regarding claim 1, Cheng teaches “An interrupt information processing method, applied to a central processing unit (CPU), wherein the CPU comprises at least one physical central processing unit (PCPU), and the PCPU is configured to run a virtual central processing unit (VCPU) process on a virtual machine ([Pg. 47, section 3] teaches dedicated physical CPUs for each virtual cpu); the method comprises: determining a target VCPU process corresponding to a timer setting instruction in response to receiving the timer setting instruction ([Pg. 47-48, section 4.1] teaches DirectVM configuring a timer in the local APIC, wherein a timeout value is written to a register which then starts ticking; Pg. 47 section 3, under Dedicated Physical CPUs has taught that each vCPU has a dedicated physical CPU such that the timer interrupt would be meant for a vCPU process corresponding to the CPU), and obtaining, through a virtual machine corresponding to the target VCPU process, a timer interrupt … corresponding to the target VCPU process ([Pg. 47-48, section 4.1-4.2] teaches Directvisor configuring the local APIC to deliver a posted interrupt notification, wherein the Directvisor exports all physical APIC IDs of all physical CPUs assigned to a guest, identifying other guest vCPUs); modifying, through the virtual machine, indication information corresponding to the timer interrupt … to preset indication information, wherein the indication information is used to indicate whether the target VCPU process is capable of receiving timer interrupt information in a virtualization mode, and the preset indication information is used to indicate that the target VCPU process is capable of receiving the timer interrupt information in the virtualization mode ([Pg. 48 section 4.2] teaches setting a desired bit within a vCPU’s posted interrupt request bitmap, wherein the vCPU is to receive the interrupt, and since it does not require emulation by the hypervisor, so the virtual CPU remains in virtualization/guest mode such that it is able to receive an interrupt in virtualization mode); and injecting timer interrupt information into the target VCPU process in the virtualization mode in response to set time corresponding to the timer setting instruction is up ([Pg. 48, section 4.1] teaches DirectVM keeping track of expiration times of each timer interrupt, wherein the interrupt is triggered when the timer expires)”.
Cheng may not explicitly teach a timer interrupt identifier.
Madukkarumukumana teaches of bits used to indicate interrupt vector and desired destination for the interrupt request such that it teaches the limitation “obtaining, through a virtual machine corresponding to the target VCPU process, a timer interrupt identifier corresponding to the target VCPU process ([0034] teaches that an interrupt message may include a 32-bit address field and data field, wherein bits of the field may be used to indicate interrupt vector and desired destination)”.
It would have been obvious to a person of ordinary skill in the art before the effective
filing date to have applied the teachings of Madukkarumukumana to the invention of Cheng to
show that interrupts may contain an identifier corresponding to a vCPU. A person
having ordinary skill in the art would have been motivated to make this combination as associating an interrupt identifier with a corresponding vCPU allows the system to track and identify particular interrupts to be injected when an event timer expires or the like. Since the teachings were analogous art known at the filing time of the invention, one of ordinary skill could have applied said teachings to achieve expected results.
Regarding claim 8, it is similar to claim 1 and is rejected for the same reasons. Claim 8 is directed towards “An electronic device... (Madukkarumukumana [0024]).
Regarding claim 15, it is similar to claim 1 and is rejected for the same reasons. The combination may not explicitly teach a non-transitory computer-readable storage medium.
Raisch teaches a non-transitory medium for providing interrupts to a guest operating system such that it teaches the limitation “A non-transitory computer-readable storage medium, wherein the computer-readable storage medium stores computer-execution instructions, and when a processor executes the computer-execution instructions ([0093])”.
It would have been obvious to a person of ordinary skill in the art before the effective
filing date to have applied the teachings of Raisch to the combination of Cheng and Madukkarumukumana to show that the method of the combination may be carried out on a non-transitory storage medium. A person having ordinary skill in the art would have been motivated to make this modification as it is widely known in the art. Since the teachings were analogous art known at the filing time of the invention, one of ordinary skill could have applied said teachings to achieve expected results.
Regarding claim 5, the combination teaches “The method according to claim 1, wherein a virtual machine control mode is provided in the CPU (Cheng [Pg. 47, section 4] teaches of VM exits and VM entries);
correspondingly, before determining the target VCPU process corresponding to the timer setting instruction in response to receiving the timer setting instruction, and obtaining, through the virtual machine corresponding to the target VCPU process, the timer interrupt identifier corresponding to the target VCPU process, the method further comprises:
modifying the virtual machine control mode from a local timer mode to a virtual machine interrupt mode in response to the virtual machine switching from a host mode to the virtualization mode; wherein the virtual machine interrupt mode is used by the CPU to send the timer interrupt information to the virtual machine running in the virtualization mode (Cheng [Pg. 47-48, section 4.1] teaches Directvisor configuring the local APIC to deliver a posted interrupt notification instead of a regular timer interrupt when the timer expires, and then executes a VM entry such that when the VM switches from host to virtualization mode via a VM entry, the timer must be configured to be a posted interrupt notification vector, wherein it is a virtual machine interrupt mode)”.
Regarding claims 12 and 19, they are similar to claim 5 and are rejected for the same reasons.
Regarding claim 6, the combination teaches “The method according to claim 5, wherein the method further comprises: modifying the virtual machine control mode from the virtual machine interrupt mode to the local timer mode in response to the virtual machine switching from the virtualization mode to the host mode (Cheng [Pg. 49, section 5.2] teaches that Directvisor may disable direct timer and IPI accesses by re-enabling VM exits, wherein it configures local vectors to deliver physical timer interrupts and IPIs instead such that when a VM exit occurs (switching from virtualization to host mode), it would use local timer interrupts instead of the posted interrupts)”.
Regarding claims 13 and 20, they are similar to claim 6 and are rejected for the same reasons.
Regarding claim 7, the combination teaches “The method according to claim 1, wherein before determining the target VCPU process corresponding to the timer setting instruction in response to receiving the timer setting instruction, and obtaining, through the virtual machine corresponding to the target VCPU process, the timer interrupt identifier corresponding to the target VCPU process, the method further comprises:
obtaining a first quantity of timer interrupt information received by the virtual machine within a preset duration and a second quantity of other interrupt information, except the timer interrupt information, received by the virtual machine within the preset duration; and if the first quantity is greater than the second quantity, performing the step of determining the target VCPU process corresponding to the timer setting instruction in response to receiving the timer setting instruction, and obtaining, through the virtual machine corresponding to the target VCPU process, the timer interrupt identifier corresponding to the target VCPU process ([Cheng Pg. 48, section 4.1] teaches of spurious timer interrupts, wherein a DirectVM guest keeps track of both arrival times and the expected expiration times, and if the arrival time is earlier than an expected expiration time, then the time interrupt handling does not proceed. Otherwise, it would trigger the timer interrupt handling)”.
Regarding claim 14, it is similar to claim 7 and is rejected for the same reasons.
Claims 2, 9, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng, Madukkarumukumana, and Raisch as used above in claims 1, 8, and 15, and in further view of ZHAO et al. Pub. No. US 2023/0259380 A1 (hereafter Zhao).
Regarding claim 2, the combination teaches “The method according to claim 1, wherein the obtaining, through the virtual machine corresponding to the target VCPU process, the timer interrupt identifier corresponding to the target VCPU process comprises: obtaining, through the virtual machine corresponding to the target VCPU process, attribute information respectively corresponding to at least one VCPU process within the virtual machine (Madukkarumukumana [0043] teaches a interrupt request table, which may contain a Posted-interrupt descriptor address and a virtual vector assigned to an interrupt that is targeting a virtual processor),
wherein the attribute information comprises interrupt identifiers respectively corresponding to a plurality of interrupt types (Madukkarumukumana [0046] teaches a 256 bit posted interrupt request register);”
The combination may not explicitly teach of process identifiers to a vCPU process.
Zhao teaches of vCPU IDs correspondence to target interrupt requests such that it teaches the limitation “selecting, through the virtual machine, target attribute information to the target VCPU process from the attribute information respectively corresponding to the at least one VCPU process; selecting, through the virtual machine, target attribute information corresponding to the target VCPU process from the attribute information respectively corresponding to the at least one VCPU process according to a process identifier corresponding to the target VCPU process; and selecting, through the virtual machine, the timer interrupt identifier corresponding to the target VCPU process from the interrupt identifiers respectively corresponding to the plurality of interrupt types comprised in the target attribute information (Zhao [0019] teaches an interrupt number of each type, wherein a target interrupt number may be written to a register, and a interrupt affinity table is used to determine a corresponding vCPU, wherein the example given is interrupt number 10 corresponds to vCPU ID1. A target interrupt number may be the target attribute information to a corresponding vCPU, where the process identifier is the vCPU ID).”
It would have been obvious to a person of ordinary skill in the art before the effective
filing date to have applied the teachings of Zhao to the combination of Cheng, Madukkarumukumana, and Raisch to associate an interrupt identifier with a vCPU process. A person having ordinary skill in the art would have been motivated to make this combination as it would enable targeted and efficient virtual interrupt injections without VM exits, reducing switching overhead and improving performance of the system (Zhao [0019]). Since the teachings were analogous art known at the filing time of the invention, one of ordinary skill could have applied said teachings to achieve expected results.
Regarding claims 9 and 16, they are similar to claim 2 and are rejected for the same reasons.
Claims 3, 10, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng, Madukkarumukumana, and Raisch as used above in claims 1, 8, and 15, and in further view of PAPE Pub. No. US 2015/0121135 A1.
Regarding claim 3, the combination may not explicitly teach of a hook operation.
PAPE teaches a hook component for hooking interrupt numbers such that it teaches “The method according to claim 1, wherein before modifying, through the virtual machine, the indication information corresponding to the timer interrupt identifier to the preset indication information, the method further comprises: performing a hook operation on a preset program within the virtual machine, wherein the hook operation is used to modify the indication information corresponding to the timer interrupt identifier to the preset indication information when the timer setting instruction is received ([0092] teaches a hook operation intercepting a write attempt by the virtual machine and updates the event/MSR with a value with which the guest attempted to update it with. When combined with Cheng, it could be that that hooking and updating a value within a register may be a value within a bitmap representing the indication information for a target VM. Also see PAPE [0099])”.
It would have been obvious to a person of ordinary skill in the art before the effective
filing date to have applied the teachings of PAPE to the combination of Cheng, Madukkarumukumana, and Raisch to teach a hook operation for modifying a value. A person having ordinary skill in the art would have been motivated to make this combination as it would allow for monitoring and modifying of values from an outside, more privileged perspective, resulting in minimal performance impact to the VM and the system (PAPE [0001]). Since the teachings were analogous art known at the filing time of the invention, one of ordinary skill could have applied said teachings to achieve expected results.
Claims 4, 11, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng, Madukkarumukumana, and Raisch as used above in claims 1, 8, and 15, and PAPE as used in claims 3, 10, and 17 above, and in further view of Feng “[RFC: timer passthrough 1/9] KVM: vmx: hook set_next_event for getting the host tscd” (please see NPL titled RFC_hook_set_next_event.pdf).
Examiner notes that the cited NPL may be of the same inventor.
Regarding claim 4, the combination may not explicitly teach the preset program to be a set next event function.
Feng teaches a hook operation on a set_next_event function such that it teaches the limitation “The method according to claim 3, wherein the preset program is a set next event function (Feng stated that “in order to get the host tscd value, we need to hook set_next_event function”, wherein the functions defined will keep track of the tick time until next event)”.
It would have been obvious to a person of ordinary skill in the art before the effective
filing date to have applied the teachings of Feng to the combination of Cheng, Madukkarumukumana, Raisch, and PAPE to teach hooking a set_next_event function. A person having ordinary skill in the art would have been motivated to make this combination to show that hook operations can be used in a virtualization environment to intercept VM-related timer operation and modify values used in subsequent timer processing. Since the teachings were analogous art known at the filing time of the invention, one of ordinary skill could have applied said teachings to achieve expected results.
Regarding claims 11 and 18, they are similar to claim 4 and are rejected for the same reasons.
Regarding claim 5, the combination teaches “The method according to claim 1, wherein a virtual machine control mode is provided in the CPU (Cheng [Pg. 47, section 4] teaches of VM exits and VM entries);
correspondingly, before determining the target VCPU process corresponding to the timer setting instruction in response to receiving the timer setting instruction, and obtaining, through the virtual machine corresponding to the target VCPU process, the timer interrupt identifier corresponding to the target VCPU process, the method further comprises:
modifying the virtual machine control mode from a local timer mode to a virtual machine interrupt mode in response to the virtual machine switching from a host mode to the virtualization mode; wherein the virtual machine interrupt mode is used by the CPU to send the timer interrupt information to the virtual machine running in the virtualization mode (Cheng [Pg. 47-48, section 4.1] teaches Directvisor configuring the local APIC to deliver a posted interrupt notification instead of a regular timer interrupt when the timer expires, and then executes a VM entry such that when the VM switches from host to virtualization mode via a VM entry, the timer must be configured to be a posted interrupt notification vector, wherein it is a virtual machine interrupt mode)”.
Regarding claim 6, the combination teaches “The method according to claim 5, wherein the method further comprises: modifying the virtual machine control mode from the virtual machine interrupt mode to the local timer mode in response to the virtual machine switching from the virtualization mode to the host mode (Cheng [Pg. 49, section 5.2] teaches that Directvisor may disable direct timer and IPI accesses by re-enabling VM exits, wherein it configures local vectors to deliver physical timer interrupts and IPIs instead such that when a VM exit occurs (switching from virtualization to host mode), it would use local timer interrupts instead of the posted interrupts)”.
References not cited but are pertinent to the art are as follows:
WO 2015192381 A1
Teaches
INTERRUPTION HANDLING METHOD AND RELEVANT DEVICE OF VIRTUAL PLATFORM
WO 2016131247 A1
Teaches
METHOD FOR REALIZING HIGH-PERFORMANCE TIMER USING VIRTUAL MACHINE AND VIRTUAL MACHINE
US 20190121658 A1
Teaches
POSTED INTERRUPT PROCESSING IN VIRTUAL MACHINE MONITOR
US 20230125661 A1
Teaches
SYSTEMS AND METHODS FOR DETECTING AND PREDICTING VIRTUAL CPU RESOURCE STARVATION OF A VIRTUAL MACHINE
US 20170083363 A1
Teaches
Interrupt Information Processing Method, Virtual Machine Monitor, And Interrupt Controller
US 20100223611 A1
Teaches
REDUCING THE LATENCY OF VIRTUAL INTERRUPT DELIVERY IN VIRTUAL MACHINES
Conclusion
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/BRANDON NGUYEN/Examiner, Art Unit 2195
/Aimee Li/Supervisory Patent Examiner, Art Unit 2195
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