DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 10/04/2024 for application number 18/906,510. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Claims, and Oath/Declaration.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because:
In Fig. 1, reference character “100” has been used to designate both the overall system including the Microphone Array 130, Microphone 130A-130C, Display 114, Power Supply 118, and Speaker 120; and the System-on-Chip.
Also in Fig. 1, reference character “154” has been used to designate both the personal area network (PAN) adaptor and the audio circuitry.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Paragraph 25 recites “Fig. 2 shows a flowchart illustrating an example process 400” (emphasis added), however paragraph 56 and the Fig. 2 drawing shows the reference number to be 200.
Paragraph 26 recites “Fig. 3 is a block diagram of an example system-on-chip (SoC) apparatus 500” (emphasis added), however paragraph 67 and the Fig. 3 drawing shows the reference number to be 300.
Paragraph 27 recites “Fig. 4 shows a flowchart illustrating an example process 600” (emphasis added), however paragraph 76 and the Fig. 4 drawing shows the reference number to be 400.
Paragraph 28 recites “Fig. 5 is a block diagram of an example system-on-chip (SoC) apparatus 700” (emphasis added), however paragraph 82 and the Fig. 5 drawing show the reference number to be 500.
Paragraph 29 recites “Fig. 6 illustrates a block diagram of exemplary finite machine (FSM) logic 800” (emphasis added), however paragraph 91 and the Fig. 6 drawing show the reference number to be 600.
Reference number 154 as disclosed in paragraph 45 and 50 are labeled “PAN adaptor 154” and “Audio circuitry 154” respectively.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 17 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding Claim 17, lines 16-17 recite, “…and output a signal indicating an adjusted performance state for the at least one other clock domain.” (emphasis added) However, there does not appear to be support in the Specification as filed for the limitation of the desired configuration to adjust the performance state of the at least one other clock domain as required by the Claim. For purposes of examination, the examiner construes “an adjusted performance state for the at least one other clock domain” to be “the performance state for the at least one other clock domain” (emphasis added).
Claim Rejections - 35 USC § 103
Claims 1, 4, 6, 9, 12, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over GOLD et al., US 2009/0235108 A1, in view of BHANDARU et al., US 2013/0346774 A1, hereafter BHANDARU ‘774.
Regarding Claim 1, GOLD discloses
A method for managing performance in a system-on-chip (SoC) having multiple clock domains, the method comprising (Fig. 4, method 400, using computer system 100 (i.e. system-on-chip (SoC)) with a multi-core (i.e. having multiple clock domains) processor subsystem 110 in Fig. 1 and Fig. 2; [0024] discloses Clock Generation Unit 190 is capable of generating different frequencies for various cores (i.e. having multiple clock domains) of processing subsystem 110; [0036] discloses method 400 further implements steps 310 for checking entry criteria and 320 for performing overclocking entry procedure (i.e. managing performance) of method 300 shown in Fig. 3)
receiving an indication of a first clock domain associated with a first performance state ([0028] discloses the PCU 210 receives performance information 204 that indicates the state information relating to the operating condition (i.e. receiving an indication a first performance state associated with a first clock domain) of one or more cores (i.e. first clock domain));
determining if one or more conditions are satisfied for applying a shared rail boost (SRB) feature to the first clock domain, the one or more conditions comprising at least one of: a utilization level of the first clock domain exceeding a first threshold ([0026] discloses the performance control unit (PCU) 210 is configured to receive various input information and automatically determine whether to overclock (i.e. applying a shared rail boost (SRB) feature) one or more cores 230 (i.e. the first clock domain) based on one or more predetermined sets of (configurable) criteria (i.e. if one or more conditions are satisfied); [0038] discloses determining whether a particular processing unit (i.e. the first clock domain) has sufficient utilization to merit overclocking),
a number of active cores in the first clock domain exceeding a second threshold, or
at least one of a voltage difference between the first clock domain and at least one other clock domain, or a voltage difference between the first performance state and at least one other performance state, being in a specified range; and
outputting a signal indicating a second performance state for the first clock domain when at least one of the one or more conditions is satisfied ([0052] discloses control information sent (i.e. outputting a signal) to the power supply circuitry 180 and clock generation unit 190 where the voltage supplied to the core and clock frequencies are increased (i.e. second performance state for the first clock domain) once the entry criteria for overclocking a particular core is satisfied (i.e. when at least one of the one or more conditions is satisfied) and the core is now overclocked).
GOLD does not explicitly disclose receiving an indication of a target performance state of a first clock domain associated with a first performance state;
a utilization level of the first clock domain exceeding a first threshold,
wherein the second performance state is associated with the target performance state.
However, BHANDARU ‘774 teaches receiving an indication of a target performance state of a first clock domain associated with a first performance state ([0016] teaches the operating system (OS) can further request a higher performance state, namely a P0 state; the P0 state may be an opportunistic state to operate at a higher than guaranteed frequency, where the highest such frequency may correspond to a maximum turbo frequency (P01); [0049] teaches the power control unit may use turbo control logic that can determine an appropriate voltage and frequency for operating a core (i.e. a first clock domain) based on the request received (i.e. receiving an indication of a target performance state) from the OS);
a utilization level of the first clock domain exceeding a first threshold ([0018] teaches a core can be configured with one or more sensors, such as a core activity sensor to detect core active cycles; [0030] teaches the number of core active cycles over the last observation interval (i.e. a utilization level of the first clock domain) is greater than a minimum threshold (i.e. exceeding a first threshold)),
wherein the second performance state is associated with the target performance state ([0049] teaches the turbo control logic that the power control unit applies can determine an appropriate combination of voltage and frequency (i.e. the second performance state) for operating the cores in turbo mode (i.e. the target performance state associated with the second performance state)).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of GOLD and BHANDARU ‘774 before him before the effective filing date of the claimed invention, to incorporate cores entering into turbo mode through utilization as taught by BHANDARU ‘774 into the method disclosed by GOLD to efficiently enable one or more cores to independently operate at a selected turbo mode frequency (BHANDARU [0014]).
Regarding Claim 4¸ GOLD and BHANDARU ‘774 disclose the method of Claim 1. GOLD further discloses disabling the SRB feature if the first clock domain is at a first workload being lower than a threshold workload, or if a temperature of the first clock domain exceeds a temperature threshold ([0057] discloses PCU 210 (i.e. component of the processing system) initiates an exit procedure and reduces clock frequency (i.e. disabling the SRB feature) when the PCU 210 determines that an overclocked core’s temperature (i.e. a temperature of the first clock domain) exceeds a predetermined limit (i.e. exceeds a temperature threshold) (i.e. the core that was already overclocked will have its frequency reduced due to thermal constraints regardless of having met the criteria to enter overclocking)).
Regarding Claim 6, GOLD and BHANDARU ‘774 disclose the method of Claim 1. BHANDARU ‘774 further teaches wherein the second performance state is associated with at least one of an input from a Frequency Vote Aggregator (FVA), the recommended performance state, or a hardware constraint ([0040] teaches the updated performance state (i.e. the second performance state) can be based (i.e. is associated with) on the candidate power state along with various constraints on the processor (i.e. hardware constraints); these constraints may include a thermal constraint, an electrical design point constraint, and a stock keeping unit (SKU)-based constraint, among others).
Regarding Claim 9, GOLD discloses An apparatus for managing performance in a system-on-chip (SoC) having multiple clock domains, comprising (Fig. 1, computer system 100 (i.e. An apparatus, system-on-chip (SoC)) with a multi-core (i.e. having multiple clock domains) processor subsystem 110 shown further in Fig. 2; ; [0024] discloses Clock Generation Unit 190 is capable of generating different frequencies for various cores (i.e. having multiple clock domains) of processing subsystem 110; [0036] discloses method 400 further implements steps 310 for checking entry criteria and 320 for performing overclocking entry procedure (i.e. managing performance) of method 300 shown in Fig. 3).
a processing system that includes one or more processors and one or more memories coupled with the one or more processors (Fig 2., processor subsystem 110 (i.e. a processing system) includes cores 230A and 230B (i.e. includes one or more processors); [0017] discloses the processor subsystem 110 is coupled to a memory 140 via interconnect 150 (i.e. one or more memories coupled with the one or more processors)),
The remainder of Claim 9 recites limitations similar to those of Claim 1, and is rejected accordingly.
Regarding Claim 12, GOLD and BHANDARU ‘774 disclose the apparatus of Claim 9. The remainder of Claim 12 recites limitations similar to those of Claim 4, and is rejected accordingly.
Regarding Claim 14, GOLD and BHANDARU ‘774 disclose the apparatus of Claim 9. The remainder of Claim 14 recites limitations similar to those of Claim 6, and is rejected accordingly.
Claims 2, 8, 10 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over GOLD and BHANDARU ‘774, and further in view of PARK et al., US 2015/0355660 A1.
Regarding Claim 2, GOLD and BHANDARU ‘774 disclose the method of Claim 1. The combination of GOLD and BHANDARU ‘774 does not explicitly disclose comparing an open-loop voltage of the first clock domain with an open-loop voltage of the at least one other clock domain; and selecting a recommended performance state associated with the comparison,
wherein the recommended performance state comprises a higher performance state for the clock domain with the lower open-loop voltage.
However, PARK teaches comparing an open-loop voltage of the first clock domain with an open-loop voltage of the at least one other clock domain; and selecting a recommended performance state associated with the comparison [0038] teaches cores C1 and C2 share a common power domain P1, where the power domain may include a group of circuits or cores which share a power supply; [0043] teaches the threshold operating voltage VC1 for the core C1 (i.e. an open-loop voltage of the first clock domain) may be higher than (i.e. comparing open-loop voltages) the threshold operating voltage VC2 for the core C2 (i.e. an open-loop voltage of at least one other clock domain); the control circuit 370 may select the threshold operating voltage VC1 for the slower core C1 as the supply voltage for the power domain P1; [0044] teaches using the threshold operating voltage VC1, the operating frequency F1 for core C1 and frequency F2 for core C2 can be determined (i.e. selecting a recommended performance state associated with the comparison) (i.e. the comparison between the threshold operating voltages result in choosing the threshold operating voltage sufficient to ensure both cores C1 and C2 can meet the minimum requirements)),
wherein the recommended performance state comprises a higher performance state for the clock domain with the lower open-loop voltage ([0043] teaches that selecting the threshold operating voltage VC1 as the supply voltage for the power domain P1, the fast core C2 is operating in a higher threshold operating voltage VC1 than needed; [0044] teaches the operating frequency F2 for the core C2 may be the upper (e.g. highest) threshold frequency for the core C2 supported by the threshold operating voltage VC1 (i.e. wherein the recommended performance state comprises a higher performance state for the clock domain with the lower open-loop voltage), and may be higher than the operating frequency F1 of core C1 (i.e. the chosen threshold operating voltage VC1 provides C2 with more voltage than needed, and therefore can reach a higher frequency given the voltage margin from VC1)).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of GOLD, BHANDARU ‘774, and PARK before him before the effective filing date of the claimed invention, to incorporate comparing voltages between cores as taught by PARK into the method disclosed by GOLD and BHANDARU ‘774 to ensure lowest operating voltage is selected while still allowing all cores to meet the timing requirement (PARK [0043]).
Regarding Claim 8, GOLD and BHANDARU ‘774 disclose the method of Claim 1. The combination of GOLD and BHANDARU ‘774 does not disclose wherein determining if one or more conditions are satisfied for applying the SRB feature further comprises: determining that a performance state of the at least one other clock domain is above a threshold;
and applying the SRB feature if the performance state of the at least one other clock domain is above the threshold.
However, PARK teaches wherein determining if one or more conditions are satisfied for applying the SRB feature further comprises: determining that a performance state of the at least one other clock domain is above a threshold ([0043] teaches the control circuit determines a threshold operating voltage VC1 for core C1 (i.e. determining that a performance state of the at least one other clock domain), which may be at a higher threshold operating voltage (i.e. above a threshold) than the threshold operating voltage VC2 for core C2), and
applying the SRB feature if the performance state of the at least one other clock domain is above the threshold ([0044] teaches the operating frequency F2 for the core C2 may be set at a higher frequency (i.e. applying the SRB feature) with the support of the threshold operating voltage VC1 of core C1 (i.e. the at least one other clock domain) being higher than the threshold operating voltage VC2 of core C2 (i.e. is above the threshold)).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of GOLD, BHANDARU ‘774, and PARK before him before the effective filing date of the claimed invention, to incorporate comparing voltages between cores as taught by PARK into the method disclosed by GOLD and BHANDARU ‘774 to ensure lowest operating voltage is selected while still allowing all cores to meet the timing requirement (PARK [0043]).
Regarding Claim 10, GOLD and BHANDARU ‘774 disclose the apparatus of Claim 9. The remainder of Claim 10 recites limitations similar to those of Claim 2, and is rejected accordingly.
Regarding Claim 16, GOLD and BHANDARU ‘774 disclose the apparatus of Claim 9. The remainder of Claim 16 recites limitations similar to those of Claim 8, and is rejected accordingly.
Claims 3 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over GOLD, BHANDARU ‘774, and PARK, and further in view of BHANDARU et al., US 2014/0195829 A1, hereafter BHANDARU ’829.
Regarding Claim 3, GOLD, BHANDARU ‘774, and PARK disclose the method of Claim 2. The combination of GOLD, BHANDARU ‘774, and PARK does not disclose aggregating the target performance state and the recommended performance state to determine the second performance state,
wherein the second performance state is between the first performance state and the target performance state.
However, BHANDARU ‘829 teaches aggregating the target performance state and the recommended performance state to determine the second performance state ([0046] teaches determining whether the core is requesting a performance state (i.e. the target performance state) greater than the mid value EDP clip point (the mid value EDP clip point being the result of a performance state value between two values, i.e. aggregating the target performance state and the recommended state); if the requested performance state is greater, the core performance state is clipped to the EDP clip point mid performance state (i.e. determine the second performance state) (i.e. aggregating the target performance state and recommended performance state by considering both before deciding the performance state)),
wherein the second performance state is between the first performance state and the target performance state ([0016] teaches turbo mode frequencies are frequencies higher than the guaranteed performance state P1, meaning cores seeking turbo mode are requested for a higher performance state than the current performance state; [0021] teaches the EDP clip point is a maximum permitted turbo mode frequency; [0058] teaches the power control unit can dynamically clip a core to a maximum permitted turbo mode frequency (i.e. the second performance state) which may be lower than a requested turbo mode frequency, but higher than the pre-turbo mode performance state (i.e. between the first performance state and the target performance state) (i.e. the target and recommended performance state are aggregated by taking both into consideration and if the target performance state cannot be reached, the recommended performance state is chosen as the next performance state instead as the second performance state)).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of GOLD, BHANDARU ‘774, PARK, and BHANDARU ‘829 before him before the effective filing date of the claimed invention, to incorporate a maximum permitted turbo frequency as taught by BHANDARU ‘829 into the method disclosed by GOLD, BHANDARU ‘774, and PARK to have energy efficiency and conservation associated with integrated circuits (BHANDARU ‘829[0002]).
Regarding Claim 11, GOLD, BHANDARU ‘774 and PARK disclose the apparatus of Claim 10. The remainder of Claim 11 recites limitations similar to those of Claim 3, and is rejected accordingly.
Claims 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over GOLD and BHANDARU ‘774, and further in view of KUMAR et al., US 2012/0079290 A1.
Regarding Claim 5, GOLD and BHANDARU ‘774 disclose the method of Claim 1. The combination of GOLD and BHANDARU ‘774 does not explicitly disclose wherein the receiving and determining are agnostic to at least one of schedulers or kernels.
However, KUMAR teaches wherein the receiving and determining are agnostic to at least one of schedulers or kernels ([0026] teaches monitoring micro-architectural activities (i.e. the receiving) and determining if one or more core’s V/F can be dynamically changed (i.e. the determining) can be performed independently (i.e. agnostic) from the OS (i.e. at least one of the kernels) by the PCU).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of GOLD, BHANDARU ‘774, and KUMAR before him before the effective filing date of the claimed invention, to incorporate voltage and frequency changes to one or more cores independent from the OS as taught by KUMAR into the method disclosed by GOLD and BHANDARU ‘774 to reduce/increase power, depending on the required load demand (KUMAR [0026]).
Regarding Claim 13, GOLD and BHANDARU ‘774 disclose the apparatus of Claim 9. The remainder of Claim 13 recites limitations similar to those of Claim 5, and is rejected accordingly.
Claims 7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over GOLD and BHANDARU ‘774, and further in view of NUSSBAUM et al., US 2011/0022857 A1.
Regarding Claim 7, GOLD and BHANDARU ‘774 disclose the method of Claim 1. The combination of GOLD and BHANDARU ‘774 does not explicitly disclose wherein determining if one or more conditions are satisfied for applying the SRB feature further comprises: identifying the number of active cores in the first clock domain as greater than one, and not applying the SRB feature for the last active core.
However, NUSSBAUM teaches wherein determining if one or more conditions are satisfied for applying the SRB feature further comprises: identifying the number of active cores in the first clock domain as greater than one, and not applying the SRB feature for the last active core ([0017] teaches the power reallocation of CPU (i.e. the first clock domain) cores; [0018] teaches selectively distributing power among the active cores (i.e. identifying the number of active cores in the first clock domain as greater than one) or other computation units based on frequency sensitivity; [0040] teaches the cores in the P0 state are ordered e.g., in decreasing order of boost sensitivity (i.e. identifying the number of active cores). Thus, those at the bottom are least sensitive to a frequency increase; the power allocation controller removes a core with the lowest boost sensitivity from the list (i.e. not applying the SRB feature for the last active core) (i.e. the cores at the bottom that are removed will not have the boost).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of GOLD, BHANDARU ‘774, and NUSSBAUM before him before the effective filing date of the claimed invention, to incorporate frequency increase to prioritized active cores as taught by NUSSBAUM into the method disclosed by GOLD and BHANDARU ‘774 to allow for greater overall system throughput on heterogeneous workloads (NUSSBAUM [0018]).
Regarding Claim 15, GOLD and BHANDARU ‘774 disclose the apparatus of Claim 9. The remainder of Claim 15 recites limitations similar to those of Claim 7, and is rejected accordingly.
Claims 17, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over GOLD, in view of BURNS et al., US 2012/0331310 A1, and further in view of BHANDARU ’829.
Regarding Claim 17¸ GOLD discloses An apparatus for managing performance in a system-on-chip (SoC) having more than one clock domains, comprising (Fig .1, computer system 100 (i.e. system-on-chip (SoC)) with a multi-core (i.e. having multiple clock domains) processor subsystem 110 shown further in Fig. 2; [0024] discloses Clock Generation Unit 190 is capable of generating different frequencies for various cores (i.e. having multiple clock domains) of processing subsystem 110; [0036] discloses method 400 further implements steps 310 for checking entry criteria and 320 for performing overclocking entry procedure (i.e. managing performance) of method 300 shown in Fig. 3),
a processing system that includes one or more processors and one or more memories coupled with the one or more processors (Fig 2., processor subsystem 110 (i.e. a processing system) includes cores 230A and 230B (i.e. includes one or more processors); [0017] discloses the processor subsystem 110 is coupled to a memory 140 via interconnect 150 (i.e. one or more memories coupled with the one or more processors)),
wherein the first clock domain and the at least one other clock domain share a power supply ([0024] discloses computer system 100 includes power supply circuitry 180, which is adapted to supply power to the various components of processor subsystem 110; [0029] discloses power supply circuitry 180 (to control the voltage supplied 240 to cores 230) (i.e. wherein the first clock domain and the at least on other clock domain share a power supply));
determine if one or more conditions are satisfied for applying a shared rail boost (SRB) feature to the first clock domain, the one or more conditions comprising at least one of: a utilization level of the first clock domain exceeding a threshold ([0026] discloses the performance control unit (PCU) 210 is configured to receive various input information and automatically determine whether to overclock (i.e. applying a shared rail boost (SRB) feature) one or more cores 230 (i.e. the first clock domain) based on one or more predetermined sets of (configurable) criteria (i.e. if one or more conditions are satisfied); [0038] discloses determining whether a particular processing unit (i.e. the first clock domain) has sufficient utilization to merit overclocking),
a number of active cores in the first clock domain exceeding a first threshold, or
a voltage difference between the first clock domain and the at least one other clock domain being within a specified range; and
output a signal indicating an adjusted performance state for the first clock domain when at least one of the one or more conditions is satisfied ([0052] discloses control information sent (i.e. outputting a signal) to the power supply circuitry 180 and clock generation unit 190 where the voltage supplied to the core and clock frequencies are increased (i.e. indicating an adjusted performance state for the first clock domain) once the entry criteria for overclocking a particular core is satisfied (i.e. when at least one of the one or more conditions is satisfied) and the core is now overclocked).
GOLD does not explicitly disclose monitor a performance state of a first clock domain and a performance state of at least one other clock domain,
determine if one or more conditions are satisfied for applying a shared rail boost (SRB) feature to the first clock domain, the one or more conditions comprising at least one of: a utilization level of the first clock domain exceeding a second threshold
output a signal indicating an adjusted performance state for the at least one other clock domain.
However, BURNS teaches determine if one or more conditions are satisfied for applying a shared rail boost (SRB) feature to the first clock domain, the one or more conditions comprising at least one of: a utilization level of the first clock domain exceeding a second threshold ([0019] teaches turbo mode (i.e. applying a shared rail boost (SRB) feature) is enabled when the processor C0P0 residency crosses a predetermined utilization percentage (i.e. a utilization level of the first clock domain exceeding a second threshold))
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of GOLD and BURNS before him before the effective filing date of the claimed invention, to incorporate enabling turbo mode by exceeding a utilization percentage as taught by BURNS into the apparatus disclosed by GOLD to make intelligent decisions about when to enter turbo mode for performance and when to emphasize power savings (BURNS [0004]).
The combination of GOLD AND BURNS does not explicitly disclose monitor a performance state of a first clock domain and a performance state of at least one other clock domain,
output a signal indicating an adjusted performance state for the at least one other clock domain.
However, BHANDARU ‘829 teaches monitor a performance state of a first clock domain and a performance state of at least one other clock domain ([0041] teaches the cores (i.e. a first clock domain and at least one other clock domain) can be classified into different bins in a processor based on their respective performance state; these bins can include: an inactive bin when a given core is in a non-C0 state; a guaranteed bin corresponding to a guaranteed performance level (e.g., a P1 or lower performance level); and a turbo bin, which corresponds to cores that are in or are seeking to enter into a turbo mode (i.e. the cores being classified would mean that the performance states of the cores are being monitored)).
output a signal indicating the performance state for the at least one other clock domain ([0041] teaches the cores (i.e. a first clock domain and at least one other clock domain) can be classified into different bins in a processor based on their respective performance state; [0042] teaches the power consumption can be provided for a given performance level and type of circuitry active (i.e. outputting information (signal) on the power consumption for a given performance level for each of the cores (current and other clock domains))).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of GOLD, BURNS, and BHANDARU ‘829 before him before the effective filing date of the claimed invention, to incorporate classifying cores by their performance state as taught by BHANDARU ‘829 into the apparatus disclosed by GOLD and BURNS to have energy efficiency and conservation associated with integrated circuits (BHANDARU ‘829 [0002]).
Regarding Claim 19, GOLD, BURNS, and BHANDARU ‘829 disclose the apparatus of Claim 17. GOLD further discloses wherein the processing system is further configured to cause the apparatus to: disable the SRB feature when a temperature of the first clock domain exceeds a temperature threshold regardless of the conditions for applying the SRB feature ([0057] discloses PCU 210 (i.e. component of the processing system) initiates an exit procedure and reduces clock frequency (i.e. disabling the SRB feature) when the PCU 210 determines that an overclocked core’s temperature (i.e. a temperature of the first clock domain) exceeds a predetermined limit (i.e. exceeds a temperature threshold) (i.e. the core that was already overclocked will have its frequency reduced due to thermal constraints regardless of having met the criteria to enter overclocking)).
Regarding Claim 20, GOLD, BURNS, and BHANDARU ‘829 disclose the apparatus of Claim 17. BHANDARU ‘829 further discloses wherein outputting the signal indicating the adjusted performance state for the first clock domain comprises: selecting a target performance state associated with a target performance indication ([0016] teaches turbo mode frequencies are frequencies higher than the guaranteed performance state P1, meaning cores seeking turbo mode are requested (i.e. target performance state associated with a target performance indication) for a higher performance state than the current performance state; the highest such frequency may correspond to a maximum available turbo mode frequency (P01) (i.e. the request for turbo mode is the indication of a target performance; the target performance is the turbo mode));
selecting a recommended performance state associated with the performance state of the at least one other clock domain ([0040] teaches the cores can be classified into different bins which can include: an inactive bin when a given core is in a non-C0 state; a guaranteed bin, which corresponds to cores that are operating at a guaranteed performance level or lower (e.g., a P1 or lower performance level); and a turbo bin, which corresponds to cores that are in or are seeking to enter into a turbo mode, higher than the guaranteed P1 performance mode; [0042] teaches determining the available power budget by subtracting the power consumption of the inactive and guaranteed cores (i.e. the performance state of the at least one other clock domain); [0043] teaches the maximum permitted turbo mode for the cores/EDP clip point is determined (i.e. selecting a recommended performance state) is based on the available power budget after considering the guaranteed and inactive cores (i.e. is associated with the performance state of the at least one other clock domain));
aggregating the target performance state and the recommended performance state to determine the adjusted performance state for the first clock domain ([0046] teaches determining whether the core is requesting a performance state (i.e. the target performance state) greater than the mid value EDP clip point (the mid value EDP clip point being the result of a performance state value between two values, i.e. aggregating the target performance state and the recommended state); if the requested performance state is greater, the core performance state is clipped to the EDP clip point mid performance state (i.e. determine the second performance state for the first clock domain)) (i.e. the target and recommended performance state are aggregated by taking both into consideration and if the target performance state cannot be reached, the recommended performance state is chosen as the next performance state instead as the adjusted performance state)).
BURNS further teaches selecting a recommended performance state associated with the satisfied conditions for applying the SRB ([0019] teaches turbo mode (i.e. a recommended performance state for applying the SRB feature) is enabled when the C0P0 residency crosses a predetermined utilization percentage (i.e. associated with the satisfied conditions for applying the SRB feature)).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over GOLD, BURNS, and BHANDARU ‘829, and further in view of PARK.
Regarding Claim 18, the combination of GOLD, BURNS, and BHANDARU ‘829 disclose the apparatus of Claim 17, but does not explicitly disclose wherein the processing system is further configured to cause the apparatus to: compare an open-loop voltage of the first clock domain with an open-loop voltage of the at least one other clock domain; and
select a performance state above a performance state threshold for the clock domain with the lower open-loop voltage.
However, PARK teaches wherein the processing system is further configured to cause the apparatus to: compare an open-loop voltage of the first clock domain with an open-loop voltage of the at least one other clock domain ([0038] teaches cores C1 and C2 share a common power domain P1, where the power domain may include a group of circuits or cores which share a power supply; [0043] teaches the threshold operating voltage VC1 for the core C1 (i.e. an open-loop voltage of the first clock domain) may be higher than (i.e. comparing open-loop voltages) the threshold operating voltage VC2 for the core C2 (i.e. an open-loop voltage of at least one other clock domain); the control circuit 370 may select the threshold operating voltage VC1 for the slower core C1 as the supply voltage for the power domain P1; [0044] teaches using the threshold operating voltage VC1, the operating frequency F1 for core C1 and frequency F2 for core C2 can be determined (i.e. selecting a recommended performance state associated with the comparison)); and
select a performance state above a performance state threshold for the clock domain with the lower open-loop voltage ([0043] teaches that selecting the threshold operating voltage VC1 as the supply voltage for the power domain P1, the fast core C2, which had the lower threshold operating frequency (i.e. the clock domain with the lower open-loop voltage) is operating in a higher threshold operating voltage VC1 than needed; [0044] teaches the operating frequency F2 for the core C2 may be the upper (e.g. highest) threshold frequency for the core C2 supported by the threshold operating voltage VC1 (i.e. selecting a performance state above a performance state threshold for), and may be higher than the operating frequency F1 of core C1)).
Conclusion
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/L.A./Examiner, Art Unit 2175
/ANDREW J JUNG/Supervisory Patent Examiner, Art Unit 2175
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