DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 6, 12, 13 and 19 are objected to because of the following informalities: Acronyms CRB, BWP and PSCCH should be spelled out on their first use within a claim tree. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being clearly anticipated by Si et al. (US PG Pub. 2023/002800 A1) hereinafter Si.
Regarding claim 1, and similarly claim 14, Si discloses: A terminal device, comprising a processor configured to:
obtain first information, wherein the first information is used to determine one or more interlaces that are in a resource pool and correspond to a sub-channel. ([0087], [0094-0096], [0099], [0174] a sidelink sub-channel is defined based on interlaces, where one sub-channel includes a number L of interlaces, resource pool is pre-configured as a number of interlace-based sub-channels in the frequency domain. A UE receives a set of configurations and determines a resource pool including sub-channels, each comprising a set of interlaces of RBs.)
Regarding claim 2, and similarly claim 15, Si discloses: The terminal device according to claim 1, wherein the first information indicates the one or more interlaces corresponding to the sub-channel, by indicating a quantity of the one or more interlaces comprised in the sub-channel.([0095], [0087] L , the number of interlaces per sub-channel, can be pre-configured or configured by a higher layer parameter. L can be selected from a set of pre-defined values, {1, 2, 5, 10}. The parameter L directly conveys the quantity of interlaces constituting the sub-channel.)
Regarding claim 3, and similarly claim 16, Si discloses: The terminal device according to claim 1, wherein indices of sub-channels in the resource pool have correspondences with indices of interlaces in the resource pool. ([0093-0094], [0099] the frequency location of an interlace is determined by an interlace index m (where 0≤m<M), and that the interlace index can uniquely define the sub-channel. Each sub-channel in the resource pool has a relative sub-channel index starting from 0.)
Regarding claim 4, and similarly claim 17, Si discloses: The terminal device according to claim 1, wherein when the sub-channel comprises one interlace, indices of sub-channels in the resource pool have a one-to-one correspondence with indices of interlaces in the resource pool.( [0094] when L=1, one interlace per sub-channel, the interlace index can uniquely define the sub-channel, and the sub-channel index is the same as the interlace index.)
Regarding claim 5, and similarly claim 18, Si discloses: The terminal device according to claim 1, wherein when the sub-channel comprises a plurality of interlaces, indices of the plurality of interlaces are consecutive. ([0095] when one interlace-based sub-channel includes multiple interlaces (L≥1), the multiple interlaces have contiguous interlace indices, subject to or not subject to a wraparound operation with respect to M, sub-channel is determined based on a starting interlace index and the number of contiguous interlace indices L.)
Regarding claim 6, and similarly claim 19, Si discloses: The terminal device according to claim 1, wherein a first-indexed interlace in the resource pool is mapped by using a first frequency domain position as a frequency domain start position, wherein
the first frequency domain position is a first-indexed CRB comprised in a carrier corresponding to the resource pool; or the first frequency domain position is a first-indexed CRB comprised in a sidelink BWP corresponding to the resource pool. ([0087], [0090-0091], [0079], FIG. 8 the set of RBs with respect to the interlaces are all confined in the SL BWP. The number of RBs per interlace (N) is determined based on NRB_BWP (the number of RBs in the BWP). FIG. 8 illustrates interlaces defined within a BWP, where the interlace structure begins from the BWP’s starting frequency position.)
Regarding claim 7, Si discloses: The terminal device according to claim 1, wherein a quantity of interlaces comprised in an RB set in the resource pool is determined based on a size of a sidelink subcarrier spacing. ([0088], [0079] M (the interval between RBs in an interlace, and equivalently the total number of interlaces) is fixed and determined based on the subcarrier spacing of the BWP.)
Regarding claim 8, Si discloses: The terminal device according to claim 1, wherein a quantity of interlaces comprised in each RB set in the resource pool is an integer multiple of a quantity of the one or more interlaces comprised in the sub-channel. ([0094-0095], [0087] the total number of interlaces is M (e.g., M=10 for μ=0), and that L (interlaces per sub-channel) is selected from the set {1, 2, 5, 10}. These values are chosen such that M/L yields an integer, the total interlaces divide evenly among sub-channels.)
Regarding claim 9, Si discloses: The terminal device according to claim 1, wherein a total quantity of interlaces in the resource pool is an integer multiple of a quantity of the one or more interlaces comprised in the sub-channel. ([0095], [0101] L is from the set {1, 2, 5, 10} when M=10, ensuring M is always an integer multiple of L. The bitmap length for indicating sub-channels in the resource pool is ⌈M/L⌉, which implies an integer number of sub-channels fitting within the total interlace count.)
Regarding claim 10, Si discloses: The terminal device according to claim 1, wherein a quantity of interlaces comprised in each sub-channel in the resource pool is the same. ([0087], [0095] a sub-channel includes a number L of interlaces where L is a single configured value applied uniformly. L is pre-configured or configured by a higher layer parameter associated with the resource pool configuration, meaning all sub-channels within a given resource pool share the same number of interlaces.)
Regarding claim 11, Si discloses: The terminal device according to claim 1, wherein resource pool configuration information of the resource pool comprises the first information. ([0095], [0089], [0099-0100] both M and L are pre-configured or configured by the higher layer parameter, possibly associated with the (pre-)configuration of the resource pool. The frequency domain information of the resource pool (starting sub-channel index, number of sub-channels) is also provided by higher layer parameters associated with the resource pool configuration.)
Regarding claim 12, Si discloses: The terminal device according to claim 1, wherein the processor is further configured to: obtain second information, wherein the second information is used to indicate a quantity of interlaces comprised in a frequency domain resource of a PSCCH, and the quantity of the interlaces comprised in the frequency domain resource of the PSCCH is less than or equal to a quantity of the one or more interlaces comprised in the sub-channel. ([0136-0141], [0175] PSCCH resource allocation is based on interlace-based resource pools. The frequency domain resource for PSCCH can be an indication of a set of interlace indices, where the number of interlaces for PSCCH can be 1 fixed as the interlace with the lowest index within the sub-channel’s interlaces. Since L≥1 for a sub-channel, PSCCH always uses fewer or equal interlaces than the sub-channel.)
Regarding claim 13, Si discloses: The terminal device according to claim 12, wherein resource pool configuration information of the resource pool comprises the second information. ([0139], [0136] the indication of the set of interlace indices (or the single interlace index) can be provided by a pre-configuration or configured by a higher layer parameter, the configuration of the resource pool. The PSCCH frequency domain configuration is part of the resource pool configuration.)
Regarding claim 20, Si discloses: A sidelink communication method, comprising:
obtaining, by a terminal device, first information, wherein the first information is used to determine one or more interlaces that are in a resource pool and correspond to a sub-channel. ([0174], [0087], [0094-0096], [0099], FIG. 13 method 1300 where a UE receives a set of configurations step 1310 from a BS or another UE, then determines a resource pool including a set of sub-channels step 1320, where each sub-channel includes a set of interlaces of RBs with a uniform interval of M RBs. The configurations enable the UE to identify which interlaces correspond to which sub-channels.)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2022/0078760 A1 resource pool configuration information including PSCCH time-domain resources and determination of PSCCH frequency-domain resources based on config and control information format.
US 2022/0007210 A1 sidelink BWP configuration and resource pool configuration for PSCCH and PSSCH within the sidelinke BWP.
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NICHOLAS JENSEN
Supervisory Patent Examiner
Art Unit 2472
/NICHOLAS A JENSEN/Supervisory Patent Examiner, Art Unit 2472
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