DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on 12/4/2023. It is noted, however, that applicant has not filed a certified copy of the 10-2023-0172967 application as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-7 and 9-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon (US PGPUB 2014/0281188; hereinafter “Kwon ‘188”) in view of Weingarten et al. (US PGPUB 2010/0131806), Chen et al. (US PGPUB 2021/0365213) and Nemazie et al. (US PGPUB 2014/0281825).
With regard to Claim 1, Kwon ‘188 teaches a memory controller (Fig. 1: Memory Controller 110) comprising:
a cache manager configured to receive a logical block address (LBA) from a host and to separate the LBA into a plurality of logical page numbers (LPNs), the plurality of LPNs including at least a first LPN and a second LPN ([0068] “In FTL 103, logical addresses transmitted from file system 102 are translated to physical addresses for performing read/write operations in flash memory 104. In FTL 103, logical addresses are translated to physical addresses according to map table information. Logical addresses may be divided into logical pages.” [0069] “In FTL 103, logical block address (LBA) may be divided into LPNs page by page”).
With further regard to claim 1, Kwon ‘188 does not teach the assigning of logical pages to different page types as described in claim 1. Weingarten teaches
a physical striper configured to assign the first LPN to a first page type of a nonvolatile memory device and assign the second LPN to a second page type of the nonvolatile memory device ([0186] “The flash memory may decide to store LP1 in the MSB of the 1024 cells, LP2 in the next level and LP3 in the LSB.” [0188] “It is appreciated that each logical page may be assigned only one significance level, as in certain embodiments shown and described herein in which, say, LP1 is assigned to MSB, LP2 to ISB and LP3 to LSB,” wherein “LP1” is interpreted as the “first LPN” and “LP3” as the “second LPN”.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the memory controller as disclosed by Kwon ‘188 with the assigning of logical pages to different page types as taught by Weingarten as this enables “puncturing” to be utilized, wherein “puncturing is the process of removing some of the parity bits after encoding with an error-correction code… [and] puncturing considerably increases the flexibility of the system without significantly increasing its complexity” (Weingarten [0012]).
With further regard to claim 1, Kwon ‘188 in view of Weingarten does not teach the different page types having different read times as described in claim 1. Chen teaches
wherein the first page type has a first data read time and the second page type has a second data read time that is different from the first data read time ([0035] “the page read latencies of a high page and a low page of a multi-level cell (MLC) NAND are different, and the page read latencies of a least significant bit (LSB) page, a center significant bit (CSB) page, and a most significant bit (MSB) page of a triple-level cell (TLC) NAND are different.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the memory controller as disclosed by Kwon ‘188 in view of Weingarten with the different page types having different read times as taught by Chen in order to “arrange data to be stored according to the page read count and a latency factor corresponding to the pages of each type in each of the blocks” (Chen [0006]).
With further regard to claim 1, Kwon ‘188 in view of Weingarten and Chen does not teach generating of a mixed page-type program unit as described in claim 1. Nemazie teaches
a logical writer configured to receive assignments of the first LPN and the second LPN from the physical striper, generate a program unit by grouping at least the first LPN and the second LPN, and store data corresponding to the program unit in the nonvolatile memory device by performing a write operation based on the program unit ([0061] “FIG. 6 shows two paired blocks 300 and 302. Block 300 includes 128 pages and 64 lower page address 300-L0 to 300-L63 and 64 upper page address 300-U0 to 300-U63.” [0050] “The steps for writing a page to the block is initiated at step 252.” [0051] “Next, at step 260, the data and associated split ECC in the buffer (such as local buffer 106-2) and identified by the program page address is sent and programmed is into the memory, such as the flash subsystem 110 of FIG. 4.”),
wherein the first LPN and second LPN are grouped within the program unit such that a total read time of the program unit represents a combination of the first data read time and the second data read time ([0061] “FIG. 6 shows two paired blocks 300 and 302. Block 300 includes 128 pages and 64 lower page address 300-L0 to 300-L63 and 64 upper page address 300-U0 to 300-U63,” wherein the “total read time” being a combination of the first and second data read times is an inherent feature of the “program unit” composition, i.e. being composed of the different page types having different read times as taught above in Chen.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the memory controller as disclosed by Kwon ‘188 in view of Weingarten and Chen with the generating of a mixed page-type program unit as taught by Nemazie thereby “allowing substantially concurrent read of the split segment and split ECC” (Nemazie [0014]), wherein concurrent reading is well-known to improve the read speed.
With regard to Claim 2, Kwon ‘188 in view of Weingarten, Chen and Nemazie teaches all the limitations of Claim 1 as described above. Weingarten further teaches wherein the first page type is a most significant bit (MSB) page, and the second page type is a least significant bit (LSB) page ([0188] “It is appreciated that each logical page may be assigned only one significance level, as in certain embodiments shown and described herein in which, say, LP1 is assigned to MSB, LP2 to ISB and LP3 to LSB,” wherein “LP1” is interpreted as the “first LPN” and “LP3” as the “second LPN”.).
With regard to Claim 5, Kwon ‘188 in view of Weingarten, Chen and Nemazie teaches all the limitations of Claim 1 as described above. Kwon ‘188 further teaches wherein
the nonvolatile memory device includes one or more word lines ([0006] “The present disclosure provides a memory device comprising a plurality of memory cells arranged in series and organized into a plurality of blocks, a plurality of word lines respectively coupled to corresponding memory cells in the plurality of memory cells, and a controller coupled to the plurality of word lines for performing page read operations on the pages in respective blocks through the corresponding word lines.”),
wherein the memory controller is configured to write multiple data corresponding to the program unit to a memory cell that is connected to a corresponding one of the word lines of the nonvolatile memory device ([0037] “Based on the block read counts calculated above, the TLC NAND flash is able to arrange data to be stored in the blocks DataBlk #0 to DataBlk #2.” [0035] “a least significant bit (LSB) page, a center significant bit (CSB) page, and a most significant bit (MSB) page of a triple-level cell (TLC) NAND.”).
With regard to Claim 6, Kwon ‘188 in view of Weingarten, Chen and Nemazie teaches all the limitations of Claim 1 as described above. Kwon ‘188 further teaches wherein
the nonvolatile memory device includes a first word line and a second word line adjacent to the first word line, and the logical writer is configured to write a portion of the data corresponding to the program unit to a first memory cell connected to the first word line, and to write a portion of remaining data corresponding to the program unit to a second memory cell connected to the second word line ([0058] “In a NAND flash memory device having a structure as shown in FIG. 5, erase operations are performed block by block, and program operations are performed page PAG by page PAG corresponding to word lines WL0 through WL7. Although FIG. 5 shows an example in which 8 pages PAG are arranged in a single block in correspondence to 8 word lines WL0 through WL7, each of blocks BLK0 through BLKa-1 of memory cell array 21 could have different numbers of memory cells and pages from the numbers of memory cells MCEL and pages PAG of FIG. 5.”).
With further regard to Claim 6, Weingarten further teaches wherein
the plurality of LPNs further include a third LPN, the physical striper is configured to assign the third LPN to a third page type of the nonvolatile memory device ([0188] “It is appreciated that each logical page may be assigned only one significance level, as in certain embodiments shown and described herein in which, say, LP1 is assigned to MSB, LP2 to ISB and LP3 to LSB,” wherein “LP2” is interpreted as the “third LPN”.).
With further regard to Claim 6, Chen further teaches
wherein the third page type has a third data read time different from the first data read time and the second data read time ([0035] “the page read latencies of a high page and a low page of a multi-level cell (MLC) NAND are different, and the page read latencies of a least significant bit (LSB) page, a center significant bit (CSB) page, and a most significant bit (MSB) page of a triple-level cell (TLC) NAND are different.”).
With further regard to Claim 6, Nemazie further teaches wherein
the logical writer is configured to generate the program unit by grouping the first, the second, and the third LPNs ([0068] “In another example, in a 4-bit per Cell (having lower, first middle, second middle and upper page associated with a page of memory cells), lower pages are paired with upper page, a page of data in the buffer to be programmed in a block is assigned to a page of blocks (lower, middle or upper), lower and upper pages are paired together, first middle and second middle also paired together,” wherein the “upper,” “lower,” and “first middle” are the “the first, the second, and the third LPNs” respectively.)
With regard to Claim 7, Kwon ‘188 in view of Weingarten, Chen and Nemazie teaches all the limitations of Claim 6 as described above. Chen further teaches wherein
the third page type is a central significant bit (CSB) page and the third data read time is longer than the first data read time and the second data read time ([0019] “the types of the pages comprises a high page and a low page of a multi-level cell (MLC) NAND, or a least significant bit (LSB) page, a center significant bit (CSB) page, and a most significant bit (MSB) page of a triple-level cell (TLC) NAND.” [0035] “the page read latencies of a high page and a low page of a multi-level cell (MLC) NAND are different, and the page read latencies of a least significant bit (LSB) page, a center significant bit (CSB) page, and a most significant bit (MSB) page of a triple-level cell (TLC) NAND are different.”).
With regard to Claim 9, Kwon ‘188 teaches a storage device (Fig. 1: Memory System 100) comprising:
a nonvolatile memory device including a memory cell array ([0043] “FIG. 1 shows storage device 120 with flash memory devices”); and
a memory controller configured to receive a write request signal and data from a host and to control the nonvolatile memory device to write the received data to the memory cell array (Fig. 1: Memory Controller 110. [0041] “Memory controller 110 controls memory system 100 to perform read, write, and erase operations on storage device 120 in response to requests from a host.”),
wherein the nonvolatile memory device includes first through third pages ([0055] “Referring to FIG. 4, memory cell array 21 is a flash memory cell array comprising ‘a’ memory blocks BLK0 through BLKa-1. Each of blocks BLK0 through BLKa-1 comprises ‘b’ pages PAG0 through PAGb-1”),
the memory controller includes a cache manager configured to receive a logical block address (LBA) from the host and to separate the LBA into a plurality of logical page numbers (LPNs), the plurality of LPNs including at least first through sixth LPNs ([0068] “In FTL 103, logical addresses transmitted from file system 102 are translated to physical addresses for performing read/write operations in flash memory 104. In FTL 103, logical addresses are translated to physical addresses according to map table information. Logical addresses may be divided into logical pages.” [0069] “In FTL 103, logical block address (LBA) may be divided into LPNs page by page”).
With further regard to claim 9, Kwon ‘188 does not teach the assigning of logical pages to different page types as described in claim 9. Weingarten teaches
a physical striper configuring the first through third LPNs respectively corresponding to the first through third page types and the fourth through sixth LPNs respectively correspond to the first through third page types ([0186] “The flash memory may decide to store LP1 in the MSB of the 1024 cells, LP2 in the next level and LP3 in the LSB.” [0188] “It is appreciated that each logical page may be assigned only one significance level, as in certain embodiments shown and described herein in which, say, LP1 is assigned to MSB, LP2 to ISB and LP3 to LSB,” wherein “LP1,” “LP2” and “LP3” are interpreted as the “first through third LPNs respectively”.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the storage device as disclosed by Kwon ‘188 with the assigning of logical pages to different page types as taught by Weingarten as this enables “puncturing” to be utilized, wherein “puncturing is the process of removing some of the parity bits after encoding with an error-correction code… [and] puncturing considerably increases the flexibility of the system without significantly increasing its complexity” (Weingarten [0012]).
With further regard to claim 9, Kwon ‘188 in view of Weingarten does not teach the different page types having different read times as described in claim 9. Chen teaches
wherein each page type of the first through third page types has a different data read time ([0035] “the page read latencies of a high page and a low page of a multi-level cell (MLC) NAND are different, and the page read latencies of a least significant bit (LSB) page, a center significant bit (CSB) page, and a most significant bit (MSB) page of a triple-level cell (TLC) NAND are different.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the storage device as disclosed by Kwon ‘188 in view of Weingarten with the different page types having different read times as taught by Chen in order to “arrange data to be stored according to the page read count and a latency factor corresponding to the pages of each type in each of the blocks” (Chen [0006]).
With further regard to claim 9, Kwon ‘188 in view of Weingarten and Chen does not teach generating of a mixed page-type program unit as described in claim 9. Nemazie teaches
a physical striper configured to perform a grouping operation to generate a first group including the first through third LPNs and a second group including the fourth through sixth LPNs, and a logical writer configured to receive a signal indicating correspondence between the first through sixth LPNs and the first through third page types from the physical striper, and generate a program unit by aggregating the first and second groups, and store first through sixth data corresponding to the first through sixth LPNs in the nonvolatile memory device by performing a write operation based on the program unit ([0061] “FIG. 6 shows two paired blocks 300 and 302. Block 300 includes 128 pages and 64 lower page address 300-L0 to 300-L63 and 64 upper page address 300-U0 to 300-U63.” [0050] “The steps for writing a page to the block is initiated at step 252.” [0051] “Next, at step 260, the data and associated split ECC in the buffer (such as local buffer 106-2) and identified by the program page address is sent and programmed is into the memory, such as the flash subsystem 110 of FIG. 4.”),
wherein a total read time of the first group and a total read time of the second group are the same ([0061] “FIG. 6 shows two paired blocks 300 and 302. Block 300 includes 128 pages and 64 lower page address 300-L0 to 300-L63 and 64 upper page address 300-U0 to 300-U63,” wherein the “total read time” being a combination of the first and second data read times is an inherent feature of the “program unit” composition, i.e. being composed of the different page types having different read times as taught above in Chen.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the storage device as disclosed by Kwon ‘188 in view of Weingarten and Chen with the generating of a mixed page-type program unit as taught by Nemazie thereby “allowing substantially concurrent read of the split segment and split ECC” (Nemazie [0014]), wherein concurrent reading is well-known to improve the read speed.
With regard to Claim 10, Kwon ‘188 in view of Weingarten, Chen and Nemazie teaches all the limitations of Claim 9 as described above. Chen further teaches
wherein the first page type is a most significant bit (MSB) page, the second page type is a least significant bit (LSB) page, and the third page type is a central significant bit (CSB) page, and a third data read time for the third page type is longer than a first data read time for the first page type and a second data read time for the second page type ([0035] “the page read latencies of a high page and a low page of a multi-level cell (MLC) NAND are different, and the page read latencies of a least significant bit (LSB) page, a center significant bit (CSB) page, and a most significant bit (MSB) page of a triple-level cell (TLC) NAND are different.” [0038] “Referring to FIG. 5, a TLC NAND block DataBlk #n is given as an example, and page read operations are performed on pages of LSB, CSB and MSB (e.g. Page #0, Page #1, and Page #2) in the block DataBlk #n.”).
With regard to Claim 11, Kwon ‘188 in view of Weingarten, Chen and Nemazie teaches all the limitations of Claim 9 as described above. Kwon ‘188 further teaches wherein the memory controller and the nonvolatile memory device are configured to communicate with each other via a plurality of channels, and the memory controller is configured to transmit data corresponding to the first group to the nonvolatile memory device through a first channel, and transmit data corresponding to the second group to the nonvolatile memory device through a second channel different from the first channel (See Figs. 1-2 of Kwon ‘188 showing the plurality of channels (CH1..CHN), as further described by Kwon ‘188 in Paragraphs [0039]-[0047]).
With regard to Claim 12, Kwon ‘188 in view of Weingarten, Chen and Nemazie teaches all the limitations of Claim 9 as described above. Kwon ‘188 further teaches wherein the nonvolatile memory device includes at least an N-th word line and an (N+1)-th word line, and the first through sixth data are written to a memory cell connected to the N-th word line ([0058] “In a NAND flash memory device having a structure as shown in FIG. 5, erase operations are performed block by block, and program operations are performed page PAG by page PAG corresponding to word lines WL0 through WL7. Although FIG. 5 shows an example in which 8 pages PAG are arranged in a single block in correspondence to 8 word lines WL0 through WL7, each of blocks BLK0 through BLKa-1 of memory cell array 21 could have different numbers of memory cells and pages from the numbers of memory cells MCEL and pages PAG of FIG. 5.”).
With regard to Claim 13, Kwon ‘188 in view of Weingarten, Chen and Nemazie teaches all the limitations of Claim 9 as described above. Kwon ‘188 further teaches wherein the memory cell array includes at least an N-th word line and an (N+1)-th word line, the first, second, fourth, and fifth data are written to a first memory cell connected to the N-th word line, and the third and sixth data are written to a second memory cell connected to the (N+1)-th word line ([0058] “In a NAND flash memory device having a structure as shown in FIG. 5, erase operations are performed block by block, and program operations are performed page PAG by page PAG corresponding to word lines WL0 through WL7. Although FIG. 5 shows an example in which 8 pages PAG are arranged in a single block in correspondence to 8 word lines WL0 through WL7, each of blocks BLK0 through BLKa-1 of memory cell array 21 could have different numbers of memory cells and pages from the numbers of memory cells MCEL and pages PAG of FIG. 5.”).
With regard to Claim 14, Kwon ‘188 in view of Weingarten, Chen and Nemazie teaches all the limitations of Claim 9 as described above. Kwon ‘188 further teaches wherein the logical writer is configured to transmit a first signal to the physical striper in response to receipt of the plurality of LPNs from the cache manager, in response to receiving the first signal, the physical striper is configured to perform the grouping operation and to transmit a second signal to the logical writer, and the second signal includes the correspondence between the first through sixth LPNs and the first through third pages ([0070] “FIGS. 8A through 8C are diagrams illustrating methods of updating mapping information according to a sequence in which program operations are completed in response to write requests in a multi-bank memory system, according to an embodiment of the inventive concept.” [0071] “FIG. 8A shows a sequence in which write requests are issued by a host with respect to a same logical page. As illustrated in FIG. 8A, write requests are received from the host in the order of Write A, Write B, and so on with respect to the same logical page LPN 1000.”).
With regard to Claim 15, Kwon ‘188 in view of Weingarten, Chen and Nemazie teaches all the limitations of Claim 9 as described above. Kwon ‘188 further teaches wherein a data read time for the first data is the same as a data read time for the fourth data and is different from a data read time for the second data ([0086] “One or more I/O requests received from a host via host interface 114 are sequentially stored in request queue 115. I/O requests may include, for instance, write requests, erase requests, or read requests.” [0087] “I/O requests stored in request queue 115 may have a format that cannot be directly processed by storage device 120 including flash memory devices, for example. Therefore, CPU 111 reads I/O requests stored in request queue 115 and divides the I/O requests into sub-requests, such that storage device 120 may perform requested operations.”).
With regard to Claims 16-18, these claims recite a subset of the limitations recited in Claims 9, 11 and 2 rejected above, merely omitting or rearranging some elements, and as such Claims 16-18 are respectively rejected under the same grounds and for the same reasons as discussed above with regard to Claims 9, 11 and 2.
Claims 3 and 19 rejected under 35 U.S.C. 103 as being unpatentable over Kwon ‘188 in view of Weingarten, Chen and Nemazie as applied to Claims 1 and 16 above, and further in view of Kwon (US PGPUB 2009/0249030; hereinafter “Kwon ‘030”).
With regard to claim 3, Kwon ‘188 in view of Weingarten, Chen and Nemazie teaches all the limitations of claim 1 as described above. Kwon ‘188 in view of Weingarten, Chen and Nemazie does not teach the high speed programming as described in claim 3. Kwon ‘030 teaches
wherein the data corresponding to the program unit is written in a high-speed programming (HSP) scheme ([0107] “A NAND flash memory has a page program mode for a high speed programming or writing”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the memory controller as disclosed by Kwon ‘188 in view of Weingarten, Chen and Nemazie with the high speed programming as taught by Kwon ‘030 in order to improve memory performance.
With regard to Claim 19, this claim is equivalent in scope to Claim 3 rejected above, merely having a different independent claim type, and as such Claim 19 is rejected under the same grounds and for the same reasons as discussed above with regard to Claim 3.
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon ‘188 in view of Chiang et al. (US PGPUB 2010/0332732) and Byun.
With regard to Claim 16, Kwon’188 teaches a host-storage system comprising:
a host configured to transmit a write request signal, data, and a logical block address (LBA) ([0041] “Memory controller 110 controls memory system 100 to perform read, write, and erase operations on storage device 120 in response to requests from a host.”);
a nonvolatile memory device including a memory cell array and a plurality of word lines connected to the memory cell array (Fig. 3: Memory Cell Array 21. [0058] “In a NAND flash memory device having a structure as shown in FIG. 5, erase operations are performed block by block, and program operations are performed page PAG by page PAG corresponding to word lines WL0 through WL7. Although FIG. 5 shows an example in which 8 pages PAG are arranged in a single block in correspondence to 8 word lines WL0 through WL7, each of blocks BLK0 through BLKa-1 of memory cell array 21 could have different numbers of memory cells and pages from the numbers of memory cells MCEL and pages PAG of FIG. 5.”); and
a memory controller configured to receive the write request signal, the data, and the LBA and to control a write operation to write the data to a memory cell, of the nonvolatile memory device, corresponding to the LBA (Fig. 1: Memory Controller 110. [0041] “Memory controller 110 controls memory system 100 to perform read, write, and erase operations on storage device 120 in response to requests from a host. Some of these operations may require updates to address mapping information.” [0082] “The components of memory controller 110 may be electrically connected via bus 119. Host interface 114 implements a data exchange protocol corresponding to a host connected to memory system 100 and interfaces between memory system 100 and the host.” [0086] “One or more I/O requests received from a host via host interface 114 are sequentially stored in request queue 115. I/O requests may include, for instance, write requests... If write requests are received from a host, write command codes, a starting logical block address (LBA), and information regarding the number of LBAs for performing write operations may be stored in request queue 115.”).
wherein the memory controller includes
a cache manager configured to separate the LBA into logical page numbers (LPNs) (Fig. 10: Memory Controller 110 comprising CPU 111. [0101] “CPU 111 uses a FTL firmware to translate LPN 1000 of the first write request Write A to a PPN a.” [0068] “In FTL 103, logical addresses transmitted from file system 102 are translated to physical addresses for performing read/write operations in flash memory 104. In FTL 103, logical addresses are translated to physical addresses according to map table information. Logical addresses may be divided into logical pages.” [0069] “In FTL 103, logical block address (LBA) may be divided into LPNs page by page”).
With further regard to claim 16, Kwon ‘188 does not teach the logical writer as described in claim 16. Chiang teaches
a logical writer configured to receive the one or more LPNs and to generate a program unit by collecting the LPNs on a page-by-page basis ([0025] “FIG. 2... illustrating implementation of software in the memory system 100 of FIG. 1. Referring to FIG. 2, a memory system may implement software including... an FTL 330,” wherein the “FTL” comprises the “logical writer”. [0036] “the FTL 330 obtains the logical page number (LPN), the logical block number (LBN) and a logical offset page number (LOPN) in sequence according to a logic sector number in the input data from the host 210.” [0040] “data corresponding to a logical page numbers LP3 and LP0 in the logical block having the logical block number LB108 are written into physical page having the physical page numbers PPB2 and PPB3 respectively, and the mapping relationships between the physical pages having the physical page numbers PPB2 and PPB3. Thus, the logical page numbers LP3 and LP0 are recorded (updated) into the page mapping table 332,” wherein the “logical block” is the “program unit”.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the storage device as disclosed by Kwon ‘188 with the flash translation layer (FTL) as taught by Chiang “in order to make the programming characteristics inherent in flash memory recognizable to the host device” (Chiang [0006]).
With further regard to claim 16, Kwon ‘188 in view of Chiang does not teach the grouping of LPNs and write operation as described in claim 16. Byun teaches
a physical striper configured to group some of the LPNs into a first LPN group and some of a remainder of the LPNs into a second LPN group such that the first LPN group corresponds to a first page and the second LPN group corresponds to a second page different from the first page (Col. 8 ll. 8-14: “the controller 130 may... control the memory device 150 to perform a write operation on a logical page corresponding to an allocated physical address according to the determined scheme,” wherein the “controller 130” comprises the “physical striper”. See Byun Cl. 1: “a first and a second memory dies each including physical pages each including a first and a second logical pages, the operation method comprising: allocating a stripe including physical pages included in each of the first and second memory dies for programming data chunks in response to a write command... mapping the data chunks to first logical pages and second logical pages in the stripe according to the selected stripping scheme,” wherein the “physical pages” in Byun each include “first and a second logical pages”, i.e. “some of the LPNs” and “a remainder of the LPNs”. Col. 6 Ln. 23-31: “Each of the planes may perform a one-shot program operation. Specifically, the plane may buffer data acquired from the controller 130 in an internal page buffer (not illustrated), the data having a size of three logical pages. The plane may drive a word line and bit line (not illustrated) to control memory cells coupled to one word line, such that the memory cells have a target state of eight threshold voltage states. Thus, the plane may write three logical pages corresponding to one word line at once.” Col. 6 Ln. 34-36: “the minimum unit of a write operation of the memory device 150 may be set to three logical pages corresponding to one word line.” Col. 7 Ln. 1-5: “The scheme in which the processor 134 allocates physical addresses to interleave data to be written to the plurality of logical pages may be roughly divided into two types of schemes. FIG. 4 is a diagram illustrating a first scheme,” see Fig. 4 showing another example wherein Data1, Data3 and Data5 could constitute the “first group” and Data2, Data4 and Data6 could constitute the “second group”.), and
wherein, when performing the write operation to the nonvolatile memory device based on the program unit, the logical writer is configured to initiate a write operation for the first page and then initiate a write operation for the second page before completing the write operation for the first page (Col. 5 Ln. 57-64: “In order to perform write operations on a superblock in parallel, the processor 134 may pair write commands and provide the paired write commands to the respective dies Die1 to Die4 such that write data are interleaved. When the dies Die1 to Die4 divide the paired write commands and provide the divided write commands to the internal planes, the plurality of planes Plane1 to Plane8 may perform the write operations in parallel,” wherein the first and second page may be from different ‘die’ in order to enable parallel write operations.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the storage device as disclosed by Kwon ‘188 in view of Chiang with the grouping of LPNs and write operation as taught by Byun so that “the access performance of the memory system 110 may be optimized” (Byun Col. 14-15).
With regard to Claim 17, Kwon ‘188 in view of Chiang and Byun teaches all the limitations of Claim 16 as described above. Byun further teaches wherein
the first LPN group includes a first LPN corresponding to first data and a second LPN corresponding to second data (Fig. 5A: “LSB Superpage”, i.e. first LPN group, comprising Data1-Data8, wherein Data1 and Data3 are the “first data” and “second data” respectively.),
the second LPN group includes a third LPN corresponding to third data (Fig. 5A: “CSB Superpage”, i.e. second LPN group, comprising Data9-Data16, wherein Data11 is the “third data”.),
the memory controller and the nonvolatile memory device are configured to communicate with each other via at least a first channel and a second channel (Fig. 12: Controller 6320 communicates with Memory Device 6340 via Channels CH1-CHi.),
the memory controller is configured to transmit the first data to the nonvolatile memory device via the first channel and to transmit the second and third data to the nonvolatile memory device via the second channel (Col. 12 ll. 48-50: “the controller 6320 may be connected to the memory device 6340 through a plurality of channels CH1 to Chi,” wherein Figs. 5A and 12 shows that CH1, i.e. a “first channel”, is used to transmit the “first data” Data1 and that CH2, i.e. a “second channel”, is used to transmit the “second data” Data3 and “third data” Data11.), and
the logical writer is configured to perform a write operation for the third data after the initiating of the write operation for the first data and before completing the write operation for the second data (Col. 5 Ln. 57-64: “In order to perform write operations on a superblock in parallel, the processor 134 may pair write commands and provide the paired write commands to the respective dies Die1 to Die4 such that write data are interleaved. When the dies Die1 to Die4 divide the paired write commands and provide the divided write commands to the internal planes, the plurality of planes Plane1 to Plane8 may perform the write operations in parallel,” wherein Data1, i.e. “first data”, is written to Die1 whereas Data3 and Data11, i.e. the “second data” and “third data”, is written together as a block to Die2. The write operation for the “third data” is performed alongside the write operation for the “second data” and as such the write operation for the “third data” is performed before completing the write operation for the “second data”.).
With regard to Claim 18, Kwon ‘188 in view of Chiang and Byun teaches all the limitations of Claim 17 as described above. Byun further teaches wherein
a data read time for the first data is the same as a data read time for the second data and is different from a data read time for the third data, and the host is configured to perform a read operation for the third data after performing a read operation for the first data and before performing a read operation for the second data (Col. 5 ll. 56-51: “The plurality of planes Plane1 to Plane8 may operate in parallel to one another. In order to improve the parallel processing performance of the memory system 110, the controller 130 may configure one superblock by logically coupling memory blocks included in the respective planes Planet to Plane8.” Col. 7 ll. 29-33: “In order to maximize the parallel processing performance of the memory system 110, the processor 134 may allocate physical addresses according to the second scheme that interleaves data across the plurality of dies in order of superpage,” wherein the “first data” Data1 is read from Die1 at the same time as the “second data” Data3 from Die2 in accordance with the parallel data access described in Byun, wherein “third data” Data11 is accessed from Die2 as part of the same block read operation as the “second data” Data3, i.e. before the read operation has completed.).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon ‘188 in view of Chiang and Byun as applied to Claim 16 above, and further in view of Kwon ‘030.
With regard to Claim 19, Kwon ‘188 in view of Chiang and Byun teaches all the limitations of Claim 16 as described above. Kwon ‘188 further teaches wherein
the logical writer is configured to generate a program unit based on the correspondence between the LPNs generated by the physical striper and the first and second pages ([0058] “In a NAND flash memory device having a structure as shown in FIG. 5, erase operations are performed block by block, and program operations are performed page PAG by page PAG corresponding to word lines WL0 through WL7. Although FIG. 5 shows an example in which 8 pages PAG are arranged in a single block in correspondence to 8 word lines WL0 through WL7, each of blocks BLK0 through BLKa-1 of memory cell array 21 could have different numbers of memory cells and pages from the numbers of memory cells MCEL and pages PAG of FIG. 5.”).
With further regard to claim 19, Kwon ‘188 in view of Chiang and Byun does not teach the high speed programming as described in claim 19. Kwon ‘030 teaches
data included in the program unit are written to the first and second pages in a high-speed programming (HSP) scheme ([0107] “A NAND flash memory has a page program mode for a high speed programming or writing”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the storage system as disclosed by Kwon ‘188 in view of Chiang and Byun with the high speed programming as taught by Kwon ‘030 in order to improve memory performance.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon ‘188 in view of Weingarten, Chen, Nemazie and Kwon ‘030 as applied to Claim 19 above, and further in view of Seok.
With regard to claim 20, Kwon ‘188 in view of Weingarten, Chen, Nemazie and Kwon ‘030 teaches all the limitations of claim 19 as described above. Kwon ‘188 in view of Weingarten, Chen, Nemazie and Kwon ‘030 does not teach the MLC programming as described in claim 20. Seok teaches
wherein the memory cell array includes first and second word lines, which are connected to first and second memory cells, respectively, data of the first page included in the program unit is written to the first memory cell, and data of the second page is written to the second memory cell ([0037] “For example, the cell operation mode may include any one of a single-level cell (SLC) mode for storing 1-bit data, a multi-level cell (MLC) mode for storing 2-bit data, a triple-level cell (TLC) mode for storing 3-bit data, a quad-level cell (QLC) mode for storing 4-bit data, and/or a mode for storing 5 bits or more.” See also Cl. 20 of Seok: “writing the data to the memory cells connected to the spare word line in a multi-level cell (MLC) mode.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the storage system as disclosed by Kwon ‘188 in view of Weingarten, Chen, Nemazie and Kwon ‘030 with the MLC programming as taught by Seok in order to improve storage density.
Response to Arguments
Applicant's arguments, see Pages 9-11 of the Remarks filed 6/5/2026, with respect to the rejections under 35 U.S.C. 102/103 of Claims 1-3, 5-7 and 9-20 have been fully considered but they are not persuasive. With respect to the Applicant’s argument that the newly amended language of Claims 1-3, 5-7 and 9-20 is not taught by the previously cited prior art, this argument has been fully considered but is moot in view of the newly cited Weingarten et al. (US PGPUB 2010/0131806), Chen et al. (US PGPUB 2021/0365213) and Nemazie et al. (US PGPUB 2014/0281825) references as discussed above in the respective rejections.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is as follows:
Pu (US PGPUB 2022/0179588) discloses a data storage method and apparatus comprising a storage device having different types of memory pages with different access latencies, wherein incoming data is stored according to a specified latency level identifier.
Nie et al. (“DIR: Dynamic Request Interleaving for Improving the Read Performance of Aged SSDs,” 2019) discusses a strategy for improving the performance of TLC NAND flash-based SSDs called ‘DIR’, wherein the strategy comprises grouping consecutive logical pages that have high locality and interleaving their encoded data in LSB, CSB and MSB types of device pages.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NICHOLAS J SIMONETTI/Primary Examiner, Art Unit 2137 September 28, 2026
