DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on 12/4/2023. It is noted, however, that applicant has not filed a certified copy of the 10-2023-0172967 application as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4 and 6-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwon (US PGPUB 2014/0281188; hereinafter “Kwon ‘188”).
With regard to Claim 1, Kwon ‘188 teaches a memory controller (Fig. 1: Memory Controller 110) comprising:
a cache manager configured to receive a logical block address (LBA) from a host and to separate the LBA into a plurality of logical page numbers (LPNs), the plurality of LPNs including at least a first LPN and a second LPN ([0068] “In FTL 103, logical addresses transmitted from file system 102 are translated to physical addresses for performing read/write operations in flash memory 104. In FTL 103, logical addresses are translated to physical addresses according to map table information. Logical addresses may be divided into logical pages.” [0069] “In FTL 103, logical block address (LBA) may be divided into LPNs page by page”);
a physical striper configured to output a first signal that corresponds the first LPN to a first page of a nonvolatile memory device and corresponds the second LPN to a second page of the nonvolatile memory device, wherein the second page is different from the first page ([0068] “the LPN may be translated to physical page number according to map table information.” [0069] “the LPNs may be translated to PPN indicating physical storage locations of a flash memory device.”); and
a logical writer configured to receive the first and second LPNs from the cache manager, to receive the first signal from the physical striper, and to store data to the nonvolatile memory device by performing a write operation based on the first signal, wherein the write operation includes a first write operation for first data to a first address of the nonvolatile memory device corresponding to the first LPN and then performs a second write operation for second data to a second address of the nonvolatile memory device corresponding to the second LPN ([0070] “FIGS. 8A through 8C are diagrams illustrating methods of updating mapping information according to a sequence in which program operations are completed in response to write requests in a multi-bank memory system, according to an embodiment of the inventive concept.” [0071] “FIG. 8A shows a sequence in which write requests are issued by a host with respect to a same logical page. As illustrated in FIG. 8A, write requests are received from the host in the order of Write A, Write B, and so on with respect to the same logical page LPN 1000.”), and
wherein the data is stored such that a read operation by the host includes a first read operation for the first data stored at the first address and then a second read operation for the second data stored at the second address ([0068] “In FTL 103, logical addresses transmitted from file system 102 are translated to physical addresses for performing read/write operations in flash memory 104.” [0087] “An I/O request may be divided into sub-requests having a format based on which program operations and read operations may be performed in storage device 120. Size of a sub-request may be in the unit of pages that may be independently processed in a flash memory device. A sub-request may include command codes and LPN.”).
With regard to Claim 2, Kwon ‘188 teaches the memory controller of claim 1, wherein a first data read time for the first data and a second data read time for the second data are different from each other ([0086] “One or more I/O requests received from a host via host interface 114 are sequentially stored in request queue 115. I/O requests may include, for instance, write requests, erase requests, or read requests.” [0087] “I/O requests stored in request queue 115 may have a format that cannot be directly processed by storage device 120 including flash memory devices, for example. Therefore, CPU 111 reads I/O requests stored in request queue 115 and divides the I/O requests into sub-requests, such that storage device 120 may perform requested operations.”).
With regard to Claim 4, Kwon ‘188 teaches the memory controller of claim 1, wherein
the nonvolatile memory device includes one or more word lines, and the logical writer is configured to collect the LPNs to generate a program unit, for performing the write operation, based on the collected LPNS ([0058] “In a NAND flash memory device having a structure as shown in FIG. 5, erase operations are performed block by block, and program operations are performed page PAG by page PAG corresponding to word lines WL0 through WL7. Although FIG. 5 shows an example in which 8 pages PAG are arranged in a single block in correspondence to 8 word lines WL0 through WL7, each of blocks BLK0 through BLKa-1 of memory cell array 21 could have different numbers of memory cells and pages from the numbers of memory cells MCEL and pages PAG of FIG. 5.”).
With regard to Claim 6, Kwon ‘188 teaches the memory controller of claim 4, wherein
the nonvolatile memory device includes a first word line and a second word line adjacent to the first word line, the plurality of LPNs further include a third LPN, the physical striper is configured to correspond the third LPN to a third page of the nonvolatile memory device, and the logical writer is configured to generate the program unit by collecting the first, the second, and the third LPNs, to write some of the data corresponding to the program unit to a first memory cell connected to the first word line, and to write some of a remainder of the data corresponding to the program unit to a second memory cell connected to the second word line ([0058] “In a NAND flash memory device having a structure as shown in FIG. 5, erase operations are performed block by block, and program operations are performed page PAG by page PAG corresponding to word lines WL0 through WL7. Although FIG. 5 shows an example in which 8 pages PAG are arranged in a single block in correspondence to 8 word lines WL0 through WL7, each of blocks BLK0 through BLKa-1 of memory cell array 21 could have different numbers of memory cells and pages from the numbers of memory cells MCEL and pages PAG of FIG. 5.”).
With regard to Claim 7, Kwon ‘188 teaches the memory controller of claim 6, wherein
the logical writer is configured to performs a third write operation for a third address of the nonvolatile memory device that corresponds to the third LPN after the second write operation ([0058] “In a NAND flash memory device having a structure as shown in FIG. 5, erase operations are performed block by block, and program operations are performed page PAG by page PAG corresponding to word lines WL0 through WL7. Although FIG. 5 shows an example in which 8 pages PAG are arranged in a single block in correspondence to 8 word lines WL0 through WL7, each of blocks BLK0 through BLKa-1 of memory cell array 21 could have different numbers of memory cells and pages from the numbers of memory cells MCEL and pages PAG of FIG. 5.”), and
wherein the data is stored such that the read operation by the host includes a third read operation for third data stored at the third address after the second read operation ([0068] “In FTL 103, logical addresses transmitted from file system 102 are translated to physical addresses for performing read/write operations in flash memory 104.” [0087] “An I/O request may be divided into sub-requests having a format based on which program operations and read operations may be performed in storage device 120. Size of a sub-request may be in the unit of pages that may be independently processed in a flash memory device. A sub-request may include command codes and LPN.”).
With regard to Claim 8, Kwon ‘188 teaches the memory controller of claim 7, wherein a third data read time for the third data is different from a first data read time for the first data, and the third data read time is different from a second data read time for the second data ([0068] “In FTL 103, logical addresses transmitted from file system 102 are translated to physical addresses for performing read/write operations in flash memory 104.” [0087] “An I/O request may be divided into sub-requests having a format based on which program operations and read operations may be performed in storage device 120. Size of a sub-request may be in the unit of pages that may be independently processed in a flash memory device. A sub-request may include command codes and LPN.”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon ‘188 as applied to Claim 1 above, and further in view of Kwon (US PGPUB 2009/0249030; hereinafter “Kwon ‘030”).
With regard to claim 3, Kwon ‘188 teaches all the limitations of claim 1 as described above. Kwon ‘188 does not teach the high speed programming as described in claim 3. Kwon ‘030 teaches
wherein the first and second data are written in a high-speed programming (HSP) scheme ([0107] “A NAND flash memory has a page program mode for a high speed programming or writing”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the memory controller as disclosed by Kwon ‘188 with the high speed programming as taught by Kwon ‘030 in order to improve memory performance.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon ‘188 as applied to Claim 4 above, and further in view of Seok et al. (US PGPUB 2022/0208296).
With regard to claim 5, Kwon ‘188 teaches all the limitations of claim 4 as described above. Kwon ‘188 does not teach the MLC programming as described in claim 5. Seok teaches
wherein the memory controller is configured to write multiple data corresponding to the program unit to a memory cell that is connected to a corresponding one of the word lines of the nonvolatile memory device ([0037] “For example, the cell operation mode may include any one of a single-level cell (SLC) mode for storing 1-bit data, a multi-level cell (MLC) mode for storing 2-bit data, a triple-level cell (TLC) mode for storing 3-bit data, a quad-level cell (QLC) mode for storing 4-bit data, and/or a mode for storing 5 bits or more.” See also Cl. 20 of Seok: “writing the data to the memory cells connected to the spare word line in a multi-level cell (MLC) mode.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the memory controller as disclosed by Kwon ‘188 with the MLC programming as taught by Seok in order to improve storage density.
Claims 9-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon ‘188 in view of Byun (US Patent 11,144,449).
With regard to Claim 9, Kwon ‘188 teaches a storage device (Fig. 1: Memory System 100) comprising:
a nonvolatile memory device including a memory cell array (Fig. 3: Memory Cell Array 21); and
a memory controller configured to receive a write request signal and data from a host and to control the nonvolatile memory device to write the received data to the memory cell array (Fig. 1: Memory Controller 110. [0041] “Memory controller 110 controls memory system 100 to perform read, write, and erase operations on storage device 120 in response to requests from a host. Some of these operations may require updates to address mapping information.”),
wherein the nonvolatile memory device includes first through third pages ([0055] “Referring to FIG. 4, memory cell array 21 is a flash memory cell array comprising ‘a’ memory blocks BLK0 through BLKa-1. Each of blocks BLK0 through BLKa-1 comprises ‘b’ pages PAG0 through PAGb-1,” wherein Fig. 4 shows at least three pages.),
the memory controller includes
a cache manager configured to receive a logical block address (LBA) from the host and to separate the LBA into a plurality of logical page numbers (LPNs) (Fig. 10: Memory Controller 110 comprising CPU 111. [0101] “CPU 111 uses a FTL firmware to translate LPN 1000 of the first write request Write A to a PPN a.” [0068] “In FTL 103, logical addresses transmitted from file system 102 are translated to physical addresses for performing read/write operations in flash memory 104. In FTL 103, logical addresses are translated to physical addresses according to map table information. Logical addresses may be divided into logical pages.” [0069] “In FTL 103, logical block address (LBA) may be divided into LPNs page by page”),
a logical writer configured to receive the LPNs from the cache manager ([0071] “FIG. 8A shows a sequence in which write requests are issued by a host with respect to a same logical page. As illustrated in FIG. 8A, write requests are received from the host in the order of Write A, Write B, and so on with respect to the same logical page LPN 1000.”).
With further regard to claim 9, Kwon ‘188 does not teach the grouping of LPNs as described in claim 9. Byun teaches
the plurality of LPNs including at least first through sixth LPNs (See Figs. 3-4, wherein Data1-Data6 comprise the “first through sixth LPNs”. Col. 7 Ln. 14-15: “the first to sixth data Data1 to Data6 are written to the logical pages in the first die.”),
a physical striper is configured to perform a grouping operation such that a first group, including the first through third LPNs, and a second group including the fourth through sixth LPNs are generated, the first through third LPNs respectively correspond to the first through third pages and the fourth through sixth LPNs respectively correspond to the first through third pages (See Byun Cl. 1: “mapping the data chunks to first logical pages and second logical pages in the stripe according to the selected stripping scheme.” Col. 6 Ln. 23-31: “Each of the planes may perform a one-shot program operation. Specifically, the plane may buffer data acquired from the controller 130 in an internal page buffer (not illustrated), the data having a size of three logical pages. The plane may drive a word line and bit line (not illustrated) to control memory cells coupled to one word line, such that the memory cells have a target state of eight threshold voltage states. Thus, the plane may write three logical pages corresponding to one word line at once.” Col. 6 Ln. 34-36: “the minimum unit of a write operation of the memory device 150 may be set to three logical pages corresponding to one word line.” Col. 7 Ln. 1-5: “The scheme in which the processor 134 allocates physical addresses to interleave data to be written to the plurality of logical pages may be roughly divided into two types of schemes. FIG. 4 is a diagram illustrating a first scheme,” see Fig. 4 wherein Data1, Data3 and Data5 constitute the “first group” and Data2, Data4 and Data6 constitute the “second group”.), and
the logical writer configured to sequentially write first through sixth data, of the received data and respectively corresponding to the first through sixth LPNs, to the nonvolatile memory device by performing a write operation based on the grouping operation (Col. 6 Ln. 30-36: “Thus, the plane may write three logical pages corresponding to one word line at once. When each of the planes performs a one-shot program operation, the minimum unit of a write operation of the memory device 150 may be set to three logical pages corresponding to one word line,” thereby indicating, as shown in Fig. 4, that the three LPNs of Group 1, i.e. “Block11”, will be written first sequentially followed by the remaining three LPNs of Group 2, i.e. “Block21”.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the storage device as disclosed by Kwon ‘188 with the grouping of LPNs as taught by Byun “In order to improve the parallel processing performance of the memory system” (Byun Col. 5 Ln. 47-48).
With regard to Claim 10, Kwon ‘188 in view of Byun teaches all the limitations of Claim 9 as described above. Kwon ‘188 further teaches wherein the first through sixth data is written such that a read operation by the host sequentially reads the first through sixth data stored at the nonvolatile memory device ([0086] “One or more I/O requests received from a host via host interface 114 are sequentially stored in request queue 115. I/O requests may include, for instance, write requests, erase requests, or read requests.” [0087] “I/O requests stored in request queue 115 may have a format that cannot be directly processed by storage device 120 including flash memory devices, for example. Therefore, CPU 111 reads I/O requests stored in request queue 115 and divides the I/O requests into sub-requests, such that storage device 120 may perform requested operations.”).
With regard to Claim 11, Kwon ‘188 in view of Byun teaches all the limitations of Claim 9 as described above. Kwon ‘188 further teaches wherein the memory controller and the nonvolatile memory device are configured to communicate with each other via a plurality of channels, and the memory controller is configured to transmit the first data to the nonvolatile memory device through a first channel, transmit the second data to the nonvolatile memory device through a second channel different from the first channel, and transmit the third data to the nonvolatile memory device through a third channel different from both the first and second channels (See Figs. 1-2 of Kwon ‘188 showing the plurality of channels (CH1..CHN), as further described by Kwon ‘188 in Paragraphs [0039]-[0047]).
With regard to Claim 12, Kwon ‘188 in view of Byun teaches all the limitations of Claim 9 as described above. Kwon ‘188 further teaches wherein the nonvolatile memory device includes at least an N-th word line and an (N+1)-th word line, and the first through sixth data are written to a memory cell connected to the N-th word line ([0058] “In a NAND flash memory device having a structure as shown in FIG. 5, erase operations are performed block by block, and program operations are performed page PAG by page PAG corresponding to word lines WL0 through WL7. Although FIG. 5 shows an example in which 8 pages PAG are arranged in a single block in correspondence to 8 word lines WL0 through WL7, each of blocks BLK0 through BLKa-1 of memory cell array 21 could have different numbers of memory cells and pages from the numbers of memory cells MCEL and pages PAG of FIG. 5.”).
With regard to Claim 13, Kwon ‘188 in view of Byun teaches all the limitations of Claim 9 as described above. Kwon ‘188 further teaches wherein the memory cell array includes at least an N-th word line and an (N+1)-th word line, the first, second, fourth, and fifth data are written to a first memory cell connected to the N-th word line, and the third and sixth data are written to a second memory cell connected to the (N+1)-th word line ([0058] “In a NAND flash memory device having a structure as shown in FIG. 5, erase operations are performed block by block, and program operations are performed page PAG by page PAG corresponding to word lines WL0 through WL7. Although FIG. 5 shows an example in which 8 pages PAG are arranged in a single block in correspondence to 8 word lines WL0 through WL7, each of blocks BLK0 through BLKa-1 of memory cell array 21 could have different numbers of memory cells and pages from the numbers of memory cells MCEL and pages PAG of FIG. 5.”).
With regard to Claim 14, Kwon ‘188 in view of Byun teaches all the limitations of Claim 9 as described above. Kwon ‘188 further teaches wherein the logical writer is configured to transmit a first signal to the physical striper in response to receipt of the LPNs from the cache manager, in response to receiving the first signal, the physical striper is configured to perform the grouping operation and to transmit a second signal to the logical writer, and the second signal includes the correspondence between the first through sixth LPNs and the first through third pages ([0070] “FIGS. 8A through 8C are diagrams illustrating methods of updating mapping information according to a sequence in which program operations are completed in response to write requests in a multi-bank memory system, according to an embodiment of the inventive concept.” [0071] “FIG. 8A shows a sequence in which write requests are issued by a host with respect to a same logical page. As illustrated in FIG. 8A, write requests are received from the host in the order of Write A, Write B, and so on with respect to the same logical page LPN 1000.”).
With regard to Claim 15, Kwon ‘188 in view of Byun teaches all the limitations of Claim 9 as described above. Kwon ‘188 further teaches wherein a data read time for the first data is the same as a data read time for the fourth data and is different from a data read time for the second data ([0086] “One or more I/O requests received from a host via host interface 114 are sequentially stored in request queue 115. I/O requests may include, for instance, write requests, erase requests, or read requests.” [0087] “I/O requests stored in request queue 115 may have a format that cannot be directly processed by storage device 120 including flash memory devices, for example. Therefore, CPU 111 reads I/O requests stored in request queue 115 and divides the I/O requests into sub-requests, such that storage device 120 may perform requested operations.”).
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon ‘188 in view of Chiang et al. (US PGPUB 2010/0332732) and Byun.
With regard to Claim 16, Kwon’188 teaches a host-storage system comprising:
a host configured to transmit a write request signal, data, and a logical block address (LBA) ([0041] “Memory controller 110 controls memory system 100 to perform read, write, and erase operations on storage device 120 in response to requests from a host.”);
a nonvolatile memory device including a memory cell array and a plurality of word lines connected to the memory cell array (Fig. 3: Memory Cell Array 21. [0058] “In a NAND flash memory device having a structure as shown in FIG. 5, erase operations are performed block by block, and program operations are performed page PAG by page PAG corresponding to word lines WL0 through WL7. Although FIG. 5 shows an example in which 8 pages PAG are arranged in a single block in correspondence to 8 word lines WL0 through WL7, each of blocks BLK0 through BLKa-1 of memory cell array 21 could have different numbers of memory cells and pages from the numbers of memory cells MCEL and pages PAG of FIG. 5.”); and
a memory controller configured to receive the write request signal, the data, and the LBA and to control a write operation to write the data to a memory cell, of the nonvolatile memory device, corresponding to the LBA (Fig. 1: Memory Controller 110. [0041] “Memory controller 110 controls memory system 100 to perform read, write, and erase operations on storage device 120 in response to requests from a host. Some of these operations may require updates to address mapping information.” [0082] “The components of memory controller 110 may be electrically connected via bus 119. Host interface 114 implements a data exchange protocol corresponding to a host connected to memory system 100 and interfaces between memory system 100 and the host.” [0086] “One or more I/O requests received from a host via host interface 114 are sequentially stored in request queue 115. I/O requests may include, for instance, write requests... If write requests are received from a host, write command codes, a starting logical block address (LBA), and information regarding the number of LBAs for performing write operations may be stored in request queue 115.”).
wherein the memory controller includes
a cache manager configured to separate the LBA into logical page numbers (LPNs) (Fig. 10: Memory Controller 110 comprising CPU 111. [0101] “CPU 111 uses a FTL firmware to translate LPN 1000 of the first write request Write A to a PPN a.” [0068] “In FTL 103, logical addresses transmitted from file system 102 are translated to physical addresses for performing read/write operations in flash memory 104. In FTL 103, logical addresses are translated to physical addresses according to map table information. Logical addresses may be divided into logical pages.” [0069] “In FTL 103, logical block address (LBA) may be divided into LPNs page by page”).
With further regard to claim 16, Kwon ‘188 does not teach the logical writer as described in claim 16. Chiang teaches
a logical writer configured to receive the one or more LPNs and to generate a program unit by collecting the LPNs on a page-by-page basis ([0025] “FIG. 2... illustrating implementation of software in the memory system 100 of FIG. 1. Referring to FIG. 2, a memory system may implement software including... an FTL 330,” wherein the “FTL” comprises the “logical writer”. [0036] “the FTL 330 obtains the logical page number (LPN), the logical block number (LBN) and a logical offset page number (LOPN) in sequence according to a logic sector number in the input data from the host 210.” [0040] “data corresponding to a logical page numbers LP3 and LP0 in the logical block having the logical block number LB108 are written into physical page having the physical page numbers PPB2 and PPB3 respectively, and the mapping relationships between the physical pages having the physical page numbers PPB2 and PPB3. Thus, the logical page numbers LP3 and LP0 are recorded (updated) into the page mapping table 332,” wherein the “logical block” is the “program unit”.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the storage device as disclosed by Kwon ‘188 with the flash translation layer (FTL) as taught by Chiang “in order to make the programming characteristics inherent in flash memory recognizable to the host device” (Chiang [0006]).
With further regard to claim 16, Kwon ‘188 in view of Chiang does not teach the grouping of LPNs and write operation as described in claim 16. Byun teaches
a physical striper configured to group some of the LPNs into a first LPN group and some of a remainder of the LPNs into a second LPN group such that the first LPN group corresponds to a first page and the second LPN group corresponds to a second page different from the first page (Col. 8 ll. 8-14: “the controller 130 may... control the memory device 150 to perform a write operation on a logical page corresponding to an allocated physical address according to the determined scheme,” wherein the “controller 130” comprises the “physical striper”. See Byun Cl. 1: “a first and a second memory dies each including physical pages each including a first and a second logical pages, the operation method comprising: allocating a stripe including physical pages included in each of the first and second memory dies for programming data chunks in response to a write command... mapping the data chunks to first logical pages and second logical pages in the stripe according to the selected stripping scheme,” wherein the “physical pages” in Byun each include “first and a second logical pages”, i.e. “some of the LPNs” and “a remainder of the LPNs”. Col. 6 Ln. 23-31: “Each of the planes may perform a one-shot program operation. Specifically, the plane may buffer data acquired from the controller 130 in an internal page buffer (not illustrated), the data having a size of three logical pages. The plane may drive a word line and bit line (not illustrated) to control memory cells coupled to one word line, such that the memory cells have a target state of eight threshold voltage states. Thus, the plane may write three logical pages corresponding to one word line at once.” Col. 6 Ln. 34-36: “the minimum unit of a write operation of the memory device 150 may be set to three logical pages corresponding to one word line.” Col. 7 Ln. 1-5: “The scheme in which the processor 134 allocates physical addresses to interleave data to be written to the plurality of logical pages may be roughly divided into two types of schemes. FIG. 4 is a diagram illustrating a first scheme,” see Fig. 4 showing another example wherein Data1, Data3 and Data5 could constitute the “first group” and Data2, Data4 and Data6 could constitute the “second group”.), and
wherein, when performing the write operation to the nonvolatile memory device based on the program unit, the logical writer is configured to initiate a write operation for the first page and then initiate a write operation for the second page before completing the write operation for the first page (Col. 5 Ln. 57-64: “In order to perform write operations on a superblock in parallel, the processor 134 may pair write commands and provide the paired write commands to the respective dies Die1 to Die4 such that write data are interleaved. When the dies Die1 to Die4 divide the paired write commands and provide the divided write commands to the internal planes, the plurality of planes Plane1 to Plane8 may perform the write operations in parallel,” wherein the first and second page may be from different ‘die’ in order to enable parallel write operations.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the storage device as disclosed by Kwon ‘188 in view of Chiang with the grouping of LPNs and write operation as taught by Byun so that “the access performance of the memory system 110 may be optimized” (Byun Col. 14-15).
With regard to Claim 17, Kwon ‘188 in view of Chiang and Byun teaches all the limitations of Claim 16 as described above. Byun further teaches wherein
the first LPN group includes a first LPN corresponding to first data and a second LPN corresponding to second data (Fig. 5A: “LSB Superpage”, i.e. first LPN group, comprising Data1-Data8, wherein Data1 and Data3 are the “first data” and “second data” respectively.),
the second LPN group includes a third LPN corresponding to third data (Fig. 5A: “CSB Superpage”, i.e. second LPN group, comprising Data9-Data16, wherein Data11 is the “third data”.),
the memory controller and the nonvolatile memory device are configured to communicate with each other via at least a first channel and a second channel (Fig. 12: Controller 6320 communicates with Memory Device 6340 via Channels CH1-CHi.),
the memory controller is configured to transmit the first data to the nonvolatile memory device via the first channel and to transmit the second and third data to the nonvolatile memory device via the second channel (Col. 12 ll. 48-50: “the controller 6320 may be connected to the memory device 6340 through a plurality of channels CH1 to Chi,” wherein Figs. 5A and 12 shows that CH1, i.e. a “first channel”, is used to transmit the “first data” Data1 and that CH2, i.e. a “second channel”, is used to transmit the “second data” Data3 and “third data” Data11.), and
the logical writer is configured to perform a write operation for the third data after the initiating of the write operation for the first data and before completing the write operation for the second data (Col. 5 Ln. 57-64: “In order to perform write operations on a superblock in parallel, the processor 134 may pair write commands and provide the paired write commands to the respective dies Die1 to Die4 such that write data are interleaved. When the dies Die1 to Die4 divide the paired write commands and provide the divided write commands to the internal planes, the plurality of planes Plane1 to Plane8 may perform the write operations in parallel,” wherein Data1, i.e. “first data”, is written to Die1 whereas Data3 and Data11, i.e. the “second data” and “third data”, is written together as a block to Die2. The write operation for the “third data” is performed alongside the write operation for the “second data” and as such the write operation for the “third data” is performed before completing the write operation for the “second data”.).
With regard to Claim 18, Kwon ‘188 in view of Chiang and Byun teaches all the limitations of Claim 17 as described above. Byun further teaches wherein
a data read time for the first data is the same as a data read time for the second data and is different from a data read time for the third data, and the host is configured to perform a read operation for the third data after performing a read operation for the first data and before performing a read operation for the second data (Col. 5 ll. 56-51: “The plurality of planes Plane1 to Plane8 may operate in parallel to one another. In order to improve the parallel processing performance of the memory system 110, the controller 130 may configure one superblock by logically coupling memory blocks included in the respective planes Planet to Plane8.” Col. 7 ll. 29-33: “In order to maximize the parallel processing performance of the memory system 110, the processor 134 may allocate physical addresses according to the second scheme that interleaves data across the plurality of dies in order of superpage,” wherein the “first data” Data1 is read from Die1 at the same time as the “second data” Data3 from Die2 in accordance with the parallel data access described in Byun, wherein “third data” Data11 is accessed from Die2 as part of the same block read operation as the “second data” Data3, i.e. before the read operation has completed.).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon ‘188 in view of Chiang and Byun as applied to Claim 16 above, and further in view of Kwon ‘030.
With regard to Claim 19, Kwon ‘188 in view of Chiang and Byun teaches all the limitations of Claim 16 as described above. Kwon ‘188 further teaches wherein
the logical writer is configured to generate a program unit based on the correspondence between the LPNs generated by the physical striper and the first and second pages ([0058] “In a NAND flash memory device having a structure as shown in FIG. 5, erase operations are performed block by block, and program operations are performed page PAG by page PAG corresponding to word lines WL0 through WL7. Although FIG. 5 shows an example in which 8 pages PAG are arranged in a single block in correspondence to 8 word lines WL0 through WL7, each of blocks BLK0 through BLKa-1 of memory cell array 21 could have different numbers of memory cells and pages from the numbers of memory cells MCEL and pages PAG of FIG. 5.”).
With further regard to claim 19, Kwon ‘188 in view of Chiang and Byun does not teach the high speed programming as described in claim 19. Kwon ‘030 teaches
data included in the program unit are written to the first and second pages in a high-speed programming (HSP) scheme ([0107] “A NAND flash memory has a page program mode for a high speed programming or writing”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the storage system as disclosed by Kwon ‘188 in view of Chiang and Byun with the high speed programming as taught by Kwon ‘030 in order to improve memory performance.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon ‘188 in view of Chiang, Byun and Kwon ‘030 as applied to Claim 19 above, and further in view of Seok.
With regard to claim 20, Kwon ‘188 in view of Chiang, Byun and Kwon ‘030 teaches all the limitations of claim 19 as described above. Kwon ‘188 in view of Chiang, Byun and Kwon ‘030 does not teach the MLC programming as described in claim 20. Seok teaches
wherein the memory cell array includes first and second word lines, which are connected to first and second memory cells, respectively, data of the first page included in the program unit is written to the first memory cell, and data of the second page is written to the second memory cell ([0037] “For example, the cell operation mode may include any one of a single-level cell (SLC) mode for storing 1-bit data, a multi-level cell (MLC) mode for storing 2-bit data, a triple-level cell (TLC) mode for storing 3-bit data, a quad-level cell (QLC) mode for storing 4-bit data, and/or a mode for storing 5 bits or more.” See also Cl. 20 of Seok: “writing the data to the memory cells connected to the spare word line in a multi-level cell (MLC) mode.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the storage system as disclosed by Kwon ‘188 in view of Chiang, Byun and Kwon ‘030 with the MLC programming as taught by Seok in order to improve storage density.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is as follows:
Hu (US PGPUB 2020/0257465) discloses a disk array includes SSD of different page sizes and a virtual disk is constructed based on the SSDs of different page sizes.
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/NICHOLAS J SIMONETTI/Primary Examiner, Art Unit 2137 February 7, 2026, 20266