CTNF 18/906,790 CTNF 80339 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement 06-52 The information disclosure statements (IDS) submitted on November 24, 2025 were filed after the mailing date of the application on October 4, 2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-36 AIA Claim s 1-10 and 13-22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-20 of U.S. Patent No. 11,803,935 in view of Ouyang (US009912349B1) . As per Claim 1, the limitations of Claim 1 are covered by the limitations of patent Claim 1, as shown in the table below. However, the patent claims do not teach that the graphics processor is an accelerator device. However, Ouyang teaches that the graphics processor is an accelerator device ( deep learning accelerator terminal such as a Graphic Processing Unit, kernel calculation of the deep learning such as matrix multiplication, is completed in the interior of the deep learning accelerator , col. 13, lines 44-49). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the patent claims so that the graphics processor is an accelerator device as suggested by Ouyang. It is well-known in the art that graphics accelerators have the advantages of performing tasks much faster than CPUs, making graphics accelerators a valuable tool particularly in industries that require high computational power and efficiency. As per Claims 2-3, the limitations of Claims 2-3 are covered by the limitations of patent Claims 2-3 respectively. As per Claim 4, the limitations of Claim 4 are covered by the limitations of patent Claim 4. However, the patent claims do not teach that the graphics processor is an accelerator device. However, Ouyang teaches that the graphics processor is an accelerator device (col. 13, lines 44-49), as discussed in the rejection for Claim 1. As per Claims 5-8, the limitations of Claim 5-8 are covered by the limitations of patent Claims 5-8 respectively. As per Claim 9, the limitations of Claim 9 are covered by the limitations of patent Claim 10. However, the patent claims do not teach that the graphics processor is an accelerator device. However, Ouyang teaches that the graphics processor is an accelerator device (col. 13, lines 44-49), as discussed in the rejection for Claim 1. As per Claims 10, 13, and 14, the limitations of Claims 10, 13, and 14 are covered by the limitations of patent Claims 11-13 respectively. As per Claim 15, the limitations of Claim 15 are covered by the limitations of patent Claim 14. However, the patent claims do not teach that the graphics processor is an accelerator device. However, Ouyang teaches that the graphics processor is an accelerator device (col. 13, lines 44-49), as discussed in the rejection for Claim 1. As per Claim 16, the limitations of Claim 16 are covered by the limitations of patent Claim 15. As per Claim 17, the limitations of Claim 17 are covered by the limitations of patent Claim 16. However, the patent claims do not teach that the graphics processor is an accelerator device. However, Ouyang teaches that the graphics processor is an accelerator device (col. 13, lines 44-49), as discussed in the rejection for Claim 1. As per Claims 18-21, the limitations of Claims 18-21 are covered by the limitations of patent Claims 17-20 respectively. As per Claim 22, the limitations of Claim 22 are covered by the limitations of patent Claim 9 . 08-36 AIA Claim s 1-10 and 15-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1, 2, 7-10, and 12 of U.S. Patent No. 11,430,083 in view of Ouyang (US009912349B1) . As per Claim 1, the limitations of Claim 1 are covered by the limitations of patent Claims 7-8, as shown in the table below. However, the patent claims do not teach that the graphics processor is an accelerator device. However, Ouyang teaches that the graphics processor is an accelerator device (col. 13, lines 44-49). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the patent claims so that the graphics processor is an accelerator device as suggested by Ouyang. It is well-known in the art that graphics accelerators have the advantages of performing tasks much faster than CPUs, making graphics accelerators a valuable tool particularly in industries that require high computational power and efficiency. As per Claims 2-3, the limitations of Claims 2-3 are covered by the limitations of patent Claim 7. As per Claim 4, the limitations of Claim 4 are covered by the limitations of patent Claim 12. However, the patent claims do not teach that the graphics processor is an accelerator device. However, Ouyang teaches that the graphics processor is an accelerator device (col. 13, lines 44-49), as discussed in the rejection for Claim 1. As per Claims 5-6, the limitations of Claims 5-6 are covered by the limitations of patent Claim 7. As per Claim 7, the limitations of Claim 7 are covered by the limitations of patent Claim 10. As per Claim 8, the limitations of Claim 8 are covered by the limitations of patent Claim 9. As per Claim 9, the limitations of Claim 9 are covered by the limitations of patent Claim 1. However, the patent claims do not teach that the graphics processor is an accelerator device. However, Ouyang teaches that the graphics processor is an accelerator device (col. 13, lines 44-49), as discussed in the rejection for Claim 1. As per Claim 10, the limitations of Claim 10 are covered by the limitations of patent Claim 2. As per Claim 15, the limitations of Claim 15 are covered by the limitations of patent Claims 7-8. However, the patent claims do not teach that the graphics processor is an accelerator device. However, Ouyang teaches that the graphics processor is an accelerator device (col. 13, lines 44-49), as discussed in the rejection for Claim 1. As per Claim 16, the limitations of Claim 16 are covered by the limitations of patent Claim 7. As per Claim 17, the limitations of Claim 17 are covered by the limitations of patent Claim 12. However, the patent claims do not teach that the graphics processor is an accelerator device. However, Ouyang teaches that the graphics processor is an accelerator device (col. 13, lines 44-49), as discussed in the rejection for Claim 1. As per Claims 18-19, the limitations of Claims 18-19 are covered by the limitations of patent Claim 7. As per Claim 20, the limitations of Claim 20 are covered by the limitations of patent Claim 9 . 08-36 AIA Claim s 1-10 and 15-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1, 2, and 7-9 of U.S. Patent No. 10,943,325 in view of Ouyang (US009912349B1) . As per Claim 1, the limitations of Claim 1 are covered by the limitations of patent Claims 7-8, as shown in the table below. However, the patent claims do not teach that the graphics processor is an accelerator device. However, Ouyang teaches that the graphics processor is an accelerator device (col. 13, lines 44-49). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the patent claims so that the graphics processor is an accelerator device as suggested by Ouyang. It is well-known in the art that graphics accelerators have the advantages of performing tasks much faster than CPUs, making graphics accelerators a valuable tool particularly in industries that require high computational power and efficiency. As per Claims 2-3, the limitations of Claims 2-3 are covered by the limitations of patent Claim 7. As per Claim 4, the limitations of Claim 4 are covered by the limitations of patent Claim 7. However, the patent claims do not teach that the graphics processor is an accelerator device. However, Ouyang teaches that the graphics processor is an accelerator device (col. 13, lines 44-49), as discussed in the rejection for Claim 1. As per Claims 5-7, the limitations of Claims 5-7 are covered by the limitations of patent Claim 7. As per Claim 8, the limitations of Claim 8 are covered by the limitations of patent Claim 9. As per Claim 9, the limitations of Claim 9 are covered by the limitations of patent Claim 1. However, the patent claims do not teach that the graphics processor is an accelerator device. However, Ouyang teaches that the graphics processor is an accelerator device (col. 13, lines 44-49), as discussed in the rejection for Claim 1. As per Claim 10, the limitations of Claim 10 are covered by the limitations of patent Claim 2. As per Claim 15, the limitations of Claim 15 are covered by the limitations of patent Claims 7-8. However, the patent claims do not teach that the graphics processor is an accelerator device. However, Ouyang teaches that the graphics processor is an accelerator device (col. 13, lines 44-49), as discussed in the rejection for Claim 1. As per Claim 16, the limitations of Claim 16 are covered by the limitations of patent Claim 7. As per Claim 17, the limitations of Claim 17 are covered by the limitations of patent Claim 7. However, the patent claims do not teach that the graphics processor is an accelerator device. However, Ouyang teaches that the graphics processor is an accelerator device (col. 13, lines 44-49), as discussed in the rejection for Claim 1. As per Claims 18-19, the limitations of Claims 18-19 are covered by the limitations of patent Claim 7. As per Claim 20, the limitations of Claim 20 are covered by the limitations of patent Claim 9. 18/906,790 Claim 1 2 3 4 5 6 7 8 9 10 13 14 15 11,803,935 Claim 1 2 3 4 5 6 7 8 10 11 12 13 14 11,430,083 Claims 7-8 7 7 12 7 7 10 9 1 2 7, 8 10,943,325 Claims 7-8 7 7 7 7 7 7 9 1 2 7, 8 18/906,790 16 17 18 19 20 21 22 11,803,935 15 16 17 18 19 20 9 11,430,083 7 12 7 7 9 10,943,325 7 7 7 7 9 18/906,790 (Claim 1) 11,803,935 (Claim 1) An apparatus comprising: An apparatus comprising: a system interconnect; a system interconnect; an accelerator device coupled with the system interconnect, the accelerator device including: a graphics processor coupled with the system interconnect, the graphics processor including: Accelerator device taught by Ouyang first circuitry to load elements of matrices into a first memory of the accelerator device, wherein the first memory is a global memory; first circuitry to load elements of matrices into a first memory of the graphics processor, wherein the first memory is a global memory; Accelerator device taught by Ouyang second circuitry to transfer a subset of elements of the matrices from the first memory into a second memory, the second memory local to a set of processing resources of the accelerator device; second circuitry to transfer a subset of elements of the matrices form the first memory into a second memory, the second memory local to a set of processing resources of the graphics processor; Accelerator device taught by Ouyang third circuitry configurable to execute a compute kernel on the accelerator device, third circuitry configurable to execute a compute kernel on the graphics processor, Accelerator device taught by Ouyang the compute kernel to perform a matrix multiply operation on the subset of elements of the matrices, the compute kernel to specify one or more element-wise operations to perform on output of the matrix multiply operation before the output is transferred to the first memory, and the one or more element-wise operations include to apply an activation function to the output; and the compute kernel to perform a matrix multiply operation on the subset of elements of the matrices, the compute kernel to specify one or more element-wise operations to perform on output of the matrix multiply operation before the output is transferred to the first memory, and the one or more element-wise operations include to apply an activation function to the output; and fourth circuitry to perform the one or more element-wise operations on the output of the matrix multiply operation while the output is stored in the second memory. fourth circuitry to perform the one or more element-wise operations on the output of the matrix multiply operation while the output is stored in the second memory. 18/906,790 (Claim 1) 11,430,083 (Claims 7-8) An apparatus comprising: a system interconnect; an accelerator device coupled with the system interconnect, the accelerator device including: A data processing system comprising…one or more processors…wherein the one or more processors include a graphics processor (Claim 7) Accelerator device taught by Ouyang first circuitry to load elements of matrices into a first memory of the accelerator device, wherein the first memory is a global memory; the one or more processors to: load elements of matrices into a first memory of the graphics processor, wherein the first memory is a global memory (Claim 7) Accelerator device taught by Ouyang second circuitry to transfer a subset of elements of the matrices from the first memory into a second memory, the second memory local to a set of processing resources of the accelerator device; transfer a subset of elements of the matrices from the first memory into a second memory…the second memory local to a set of processing resources of the graphics processor; (Claim 7) Accelerator device taught by Ouyang third circuitry configurable to execute a compute kernel on the accelerator device, execution of a compute kernel on the graphics processor, (Claim 7) Accelerator device taught by Ouyang the compute kernel to perform a matrix multiply operation on the subset of elements of the matrices, the compute kernel to specify one or more element-wise operations to perform on output of the matrix multiply operation before the output is transferred to the first memory, and the one or more element-wise operations include to apply an activation function to the output; and the compute kernel is to cause the graphics processor to perform a sparse matrix multiply operation on the subset of elements of the matrices, and the matrix multiply framework is to provide a primitive to enable the compute kernel to specify one or more element-wise operations to perform on output of the sparse matrix multiply operation before the output is transferred to the first memory, the one or more element-wise operations including applying an activation function to the output (Claim 7) fourth circuitry to perform the one or more element-wise operations on the output of the matrix multiply operation while the output is stored in the second memory. the one or more element-wise operations to be performed after the matrix multiply is complete and while the output is stored in the second memory. (Claim 8) 18/906,790 (Claim 1) 10,943,325 (Claims 7-8) An apparatus comprising: a system interconnect; an accelerator device coupled with the system interconnect, the accelerator device including: A data processing system comprising…one or more processors…wherein the one or more processors include a graphics processor (Claim 7) Accelerator device taught by Ouyang first circuitry to load elements of matrices into a first memory of the accelerator device, wherein the first memory is a global memory; load elements of matrices into a first memory of the graphics processor, wherein the first memory is a global memory (Claim 7) Accelerator device taught by Ouyang second circuitry to transfer a subset of elements of the matrices from the first memory into a second memory, the second memory local to a set of processing resources of the accelerator device; transfer a subset of elements of the matrices from the first memory into a second memory…the second memory local to a set of processing resources of the graphics processor; (Claim 7) Accelerator device taught by Ouyang third circuitry configurable to execute a compute kernel on the accelerator device, execution of a compute kernel on the graphics processor, (Claim 7) Accelerator device taught by Ouyang the compute kernel to perform a matrix multiply operation on the subset of elements of the matrices, the compute kernel to specify one or more element-wise operations to perform on output of the matrix multiply operation before the output is transferred to the first memory, and the one or more element-wise operations include to apply an activation function to the output; and the compute kernel is to cause the graphics processor to perform a matrix multiply operation on the subset of elements of the matrices…the compute kernel to specify one or more element-wise operations to perform on output of the matrix multiply before the output is transferred to the first memory, the one or more element-wise operations including…applying an activation function to the output (Claim 7) fourth circuitry to perform the one or more element-wise operations on the output of the matrix multiply operation while the output is stored in the second memory. the one or more element-wise operations to be performed after the matrix multiply is complete and while the output is stored in the second memory (Claim 8) Allowable Subject Matter Claims 1-10 and 13-22 are rejected under double patenting, but would be allowable if terminal disclaimers are filed. 12-57 AIA Prior Art of Record 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. 1. Juffa (US007792895B1) teaches a system configured to perform a tiled matrix multiplication operation (col. 2, lines 53-55). Juffa teaches global memory configured to store a first source matrix, a second source matrix and a result matrix (col. 2, lines 55-57). GPU 200 includes streaming multiprocessors. Each instruction executed by a streaming multiprocessor may perform operations, including read and write operations to the GMEM 202 (col. 5, lines 7-10, 13-16). CTA copies a source tile 804 from tile row 802 of source matrix 800 from the global memory 202 to the local memory coupled to the streaming multiprocessor (col. 12, lines 62-65). CTA copies a source tile 824 from tile column 822 of source matrix 820 from the global memory 202 to the local memory coupled to the serial multiprocessor (col. 13, lines 9-11). To compute and accumulate the partial dot products of an element 844 of result tile 842, the thread assigned to element 844 would compute the partial dot products or a row 814 of source tile 804 and a column 834 of source tile 824. The thread would access the elements of row 814 and column 834 from the local memory for these computations and then write the resulting partial dot products to the local registers assigned to the thread where the partial dot products would accumulate (col. 13, lines 34-43). 2. Maaninen (US 20150199963A1) teaches machine learning [0028]. MAC unit 10 to carry out matrix multiply and add operations. An activation function unit 12 to apply an activation function to the output of MAC unit 10 [0043]. 3. Jin (US 20180181306A1) teaches storing the HS data generated using the HS wave as HS output 218 in LDS 210 [0041]. Block diagram 200 includes a local data store memory 210 (also referred to as LDS 210) and an off chip memory 212 [0034]. Block diagram 200 of components processing a thread group in a shader engine [0033]. Once CU 202 completes processing an HS wave of a thread group, HS 206 copies the HS output 218 from LDS 210 to global memory 212 [0045]. 4. Bebee (US010409560B1) teaches compute kernel (col. 7, lines 53-57). Primtives may include an SpMV primitive (for sparse matrix vector multiplication), SpMM (for sparse matrix-matrix multiplication), and/or a primitive implementing a convolution operation (col. 5, lines 2-8). Machine learning (col. 1, lines 24-27) . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONI HSU whose telephone number is (571)272-7785. The examiner can normally be reached M-F 10am-6:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kee Tung can be reached at (571)272-7794. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. JH /JONI HSU/Primary Examiner, Art Unit 2611 Application/Control Number: 18/906,790 Page 2 Art Unit: 2611 Application/Control Number: 18/906,790 Page 3 Art Unit: 2611 Application/Control Number: 18/906,790 Page 4 Art Unit: 2611 Application/Control Number: 18/906,790 Page 5 Art Unit: 2611 Application/Control Number: 18/906,790 Page 6 Art Unit: 2611 Application/Control Number: 18/906,790 Page 7 Art Unit: 2611 Application/Control Number: 18/906,790 Page 8 Art Unit: 2611 Application/Control Number: 18/906,790 Page 9 Art Unit: 2611 Application/Control Number: 18/906,790 Page 10 Art Unit: 2611 Application/Control Number: 18/906,790 Page 11 Art Unit: 2611 Application/Control Number: 18/906,790 Page 12 Art Unit: 2611 Application/Control Number: 18/906,790 Page 13 Art Unit: 2611 Application/Control Number: 18/906,790 Page 14 Art Unit: 2611 Application/Control Number: 18/906,790 Page 15 Art Unit: 2611 Application/Control Number: 18/906,790 Page 16 Art Unit: 2611 Application/Control Number: 18/906,790 Page 17 Art Unit: 2611 Application/Control Number: 18/906,790 Page 18 Art Unit: 2611 Application/Control Number: 18/906,790 Page 19 Art Unit: 2611 Application/Control Number: 18/906,790 Page 20 Art Unit: 2611
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