DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-7 are pending for examination.
Response to Argument
Applicant’s arguments with respect to claim 1 have been considered but are moot in view of the new ground(s) of rejection below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ideno et al., US Patent 10,108,209; hereinafter Ideno.
Regarding claim 1, DUONG discloses a power supply circuit (Fig. 1) comprising:
a first regulator (102) that includes a first input terminal (N1) to which a first voltage is input (N1 is an input), a first output terminal from which a second voltage is output (Tout), and a first adjustment terminal (101c), and adjusts the second voltage based on a voltage of the first adjustment terminal (Tout is based on the output Ng of the differential amp);
a second regulator (107 is a constant current regulator) that includes a second input terminal (input of 107) to which the first voltage is input (N1 is an input) and a second output terminal (Vrf) from which a third voltage is output (Vrf); and
a differential amplifier circuit (101e) that outputs, to the first adjustment terminal (101c), a signal corresponding to a difference between the third voltage (Vrf) and a fourth voltage (divided voltage at N3) at a first node (N3) between a plurality of first resistors (R2 and R3) connected in series between the first output terminal (Tout) and a reference potential (GND) lower than the second voltage (GND potential is lower than Vrf).
Allowable Subject Matter
Claim 7 is allowed.
Claims 2-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAI H TRAN whose telephone number is (571)270-0668. The examiner can normally be reached M - F 8:30 - 5:00.
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/THAI H TRAN/Examiner, Art Unit 2836
/REXFORD N BARNIE/Supervisory Patent Examiner, Art Unit 2836
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