Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a sidewall” of independent Claim 1 must be shown and labeled or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 10 positively recite at the end of the claim the phrase “such as Si02 layers”, this is indefinitely as it is only giving an example and it is not clear whether that is part of the scope or not.
For purposes of compact prosecution, these claims will be interpreted as if the phrase “such as Si02 layers” is not present as it appears to be only giving an example and not something that must be present.
Claim 14 positively recites “performing a treatment process adapted to passivate exposed surface portions of the sacrificial layers”. Therefore, it is unknown whether the method of Claim 14 actively passivates exposed surface portions of the sacrificial layer because of the phrase “adapted to”.
For purposes of compact prosecution, that Claim 14 limitation will be interpreted to instead recite “performing a treatment process [[adapted to passivate]] that passivates exposed surface portions of the sacrificial layers”.
Appropriate correction is required.
Claim 17 positively recites “performing a treatment process adapted to passivate exposed surface portions of the sacrificial layers”. Therefore, it is unknown whether the method of Claim 17 passivates exposed surface portions of the sacrificial layer.
For purposes of compact prosecution, that Claim 17 limitation will be interpreted to instead recite “performing a treatment process [[adapted to passivate]] that passivates exposed surface portions of the sacrificial layers”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-5, 7, 16, and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (“Kim”), US 2019/0198520.
Regarding Claim 1, Kim discloses a method (Figs. 6-18; ¶ 0020) for forming a memory structure (10. Figs. 6-18; ¶ 0024) for a 3D NAND flash memory (¶ 0004), the method comprising:
forming a layer stack (12; Fig. 6; ¶ 0024 “stack 12”) over a substrate (22; Fig. 6; ¶ 0027 “22 may correspond to a semiconductor substrate”), the layer stack comprising an alternating sequence (Fig. 6; ¶ 0024 “alternating first and second levels”) of gate layers (20, 16; Fig. 6; ¶ 0026 “20 of the second levels 16 is ultimately replaced with conductive material of memory cell gates”) and inter-gate spacer layers (18, 14; Fig. 6; ¶ ¶ 0024 “18 may comprise, consist essentially of, or consist of silicon nitride”);
forming first recessed areas (26; Fig. 7; ¶ 0030 “form gaps (i.e., cavities) 26”) in a sidewall (Fig. 7) surrounding a memory hole (Fig. 7; ¶ 0030 “opening 24”) in the layer stack by laterally etching back the inter-gate spacer layers from the memory hole (Fig. 7; ¶ 0030 “material 18 of the first levels 14 is recessed along the opening 24 to form gaps (i.e., cavities) 26”);
forming sacrificial layers (30, 32; Fig. 8; ¶ 0034 “structures 30 comprise material 32”) in the first recessed areas (Fig. 8; ¶ 0035 “material 32 may be deposited through the opening 24 and into the gaps 26”; ¶ 0034 “structures 30 are formed within the first gaps 26”);
forming second recessed areas (34; Fig. 9; ¶ 0036 “gaps 34”) in the sidewall by laterally etching back the gate layers from the memory hole (Fig. 9; ¶ 0036 “material 20 of the second levels 16 is recessed along the opening 24 to form second gaps 34”);
forming a lateral memory stack (12; Fig. 14) in each second recessed area (34; Figs. 9-14 noting that second recessed areas 34 of Fig. 9 initially has material 40, 42 as shown in Fig. 11; ¶ 0046 “material 40 (FIG. 12) of the segments 42 (FIG. 12) comprises, consists essentially of, or consist of silicon nitride; and the material 32 (FIG. 12) of the spacing structures 30 (FIG. 12)”) by selectively depositing (Figs 9-13), in the second recessed areas (Figs. 9-13), a blocking oxide (48, 54; Fig. 13; ¶ 0045 “surfaces within opening 24 are exposed to oxidizing conditions which oxidize the segments 42 (FIG. 12) to form charge-blocking regions 48”; ¶ 0046 “charge-blocking regions 48 may comprise the silicon oxynitride 54”) and, subsequently (Figs. 14, 15), a charge trap material (62, 64, 66, 68, 70; Figs. 14-15; ¶ 0052 “charge-storage material 62 is formed”; ¶ 0054 “charge-storage material 62…may be referred to as silicon nitride segments 64”; ¶ 0055 “66 and the silicon dioxide 68 may be considered to correspond to charge-storage regions (e.g., charge-trapping regions)” and “charge-storage regions (e.g., charge-trapping regions) 70”), wherein the sacrificial layers (30, 32, 50, 52; Figs. 12-14 noting that sacrificial layers 30, 32 are oxidized in Fig. 13 to form 50, 52; ¶ 0045 “oxidize edges of the spacing structures 30 (FIG. 11) to form the ledges 50”; ¶ 0046 “oxidize the polycrystalline silicon 32 to form additional silicon dioxide 52”) define deposition-inhibiting areas (Figs. 12-14; ¶ 0046 “the boundary between the materials 52 and 54 may be an abrupt interface”; ¶ 0047 “shapes analogous to the shapes of the charge-blocking regions 48 and ledges 50 shown in FIG. 13)”; ¶ 0053 “leave only the material 62 which is confined within the gaps 56”) for the selective deposition of the blocking oxide and the charge trap material (Figs. 12-14);
removing the sacrificial layers (30, 32 of Fig. 12 that changed to 50, 52 in Fig. 13; ¶ 0046 “material 32 (FIG. 12) of the spacing structures 30 (FIG. 12)” and “oxidize the polycrystalline silicon 32 to form additional silicon dioxide 52”; ¶ 0045 “oxidize edges of the spacing structures 30 (FIG. 11) to form the ledges 50”) by etching from the memory hole (Fig. 16; ¶ 0058 “ledges 50 (FIG. 15) are removed to form fourth gaps 72” and “material 52 (FIG. 15) of the ledges 50…is removed selectively…by…etch”);
after removing the sacrificial layers (Fig. 17), re-growing the inter-gate spacer layers (74, 76; Fig. 17; ¶ 0059 “material 74 is formed within the gaps 72”, “material 74 may comprise, consist essentially of, or consist of silicon nitride; and may be considered to be configured as silicon nitride segments 76” and “material 18 of the first levels 14 may be referred to as first silicon nitride, and the material 74 may be referred to as second silicon nitride which replaces some of the first silicon nitride”; ¶ 0061 “silicon nitride segments 76 are along the first levels 14, and are adjacent the first material 18 (which in some embodiments may be silicon nitride)”) such that the lateral memory stacks (12) are vertically separated by the re-grown inter-gate spacer layers (Fig. 17; ¶ 0061 “silicon nitride segments 76 are along the first levels 14, and are adjacent the first material 18”);
after re-growing the inter-gate spacer layers (Fig. 18), forming a tunneling oxide layer (66, 78, 82: Fig. 18; ¶ 0062 “tunneling materials 78, 80 and 82 are formed”; ¶ 0063 “66 may correspond to an additional tunneling material”; ¶ 0065) in the memory hole (Fig. 18; ¶ 0062 “tunneling materials 78, 80 and 82 are formed along an outer periphery of the opening 24”); and
forming a channel layer (84; Fig. 18; ¶ 0066 “channel material 84 is formed”) along the tunneling oxide layer (Fig. 18 ¶ 0066 “Channel material 84 is formed within the opening 24 and along the tunneling materials 78, 80 and 82. In the illustrated embodiment, the channel material 84 is directly against the tunneling material 82.”).
Regarding Claim 2, Kim discloses wherein forming the sacrificial layers (30, 32, Fig. 8; ¶ 0034) comprises conformally depositing sacrificial material to fill the first recessed areas (¶ 0035 “The material 32 may be formed within the gaps 26 with any suitable processing. For instance, in some embodiments material 32 may be deposited through the opening 24 and into the gaps 26; resulting in the gaps 26 being filled with the material 32”) and cover the sidewall of the memory hole (¶ 0035 “the opening 24 being at least partially filled with the material 32” in this instance the memory hole 24 is completely filled with sacrificial layer 30, 32), and etching back the sacrificial material (¶ 0035 “Subsequently, an etch may be utilized to remove excess material 32 from within the opening 24”) to expose end surfaces of the gate layers at the sidewall (¶ 0034 “structures 30 comprise outer edges 29 along the opening 24”; ¶ 0035 “material 32 within the gaps 26”).
Regarding Claim 4, Kim discloses wherein forming the sacrificial layers (30, 32, Fig. 8; ¶ 0034) comprises selectively depositing (Fig. 8; ¶ 0035 “material 32 may be formed within the gaps 26”), in the first recessed areas (Fig. 8; ¶ 0035 “material 32 may be formed within the gaps 26”), a sacrificial material (30, 32 of Fig. 12 is changed to 50, 52 in Fig. 13; ¶ 0046 “material 32 (FIG. 12) of the spacing structures 30 (FIG. 12)” and “oxidize the polycrystalline silicon 32 to form additional silicon dioxide 52”; ¶ 0045 “oxidize edges of the spacing structures 30 (FIG. 11) to form the ledges 50”. Then 50, 52 is removed in Fig. 16 ¶ 0058 “ledges 50 (FIG. 15) are removed to form fourth gaps 72”. Therefore sacrificial layers 30, 32 are a sacrificial material) to fill the first recessed areas (Fig. 8; ¶ 0035 “material 32 may be formed within the gaps 26”).
Regarding Claim 5, Kim discloses wherein the blocking oxide is grown laterally in the second recessed areas to a thickness in a range of 4-12 nm (¶ 0048 “The charge-blocking regions 48 extend vertically, and have horizontal thicknesses T1. Such horizontal thicknesses may be of any suitable dimension, and in some embodiments may be within a range of from about 50 Å to about 150 Å.” noting that this is a thickness in a range of 5 nm to 15 nm).
Regarding Claim 7, Kim discloses wherein the blocking oxide is grown laterally in the second recessed areas to a thickness in a range of 4-12 nm (¶ 0048 “The charge-blocking regions 48 extend vertically, and have horizontal thicknesses T1. Such horizontal thicknesses may be of any suitable dimension, and in some embodiments may be within a range of from about 50 Å to about 150 Å.” noting that this is a thickness in a range of 5 nm to 15 nm).
Regarding Claim 16, Kim discloses further comprising selectively depositing (Figs. 10-12; ¶ 0040 “a layer of dielectric barrier material 38 is formed to extend conformally along the peripheral surfaces 31, 33 and 35 within the gaps 34; and to extend along the outer edges 29 of the spacing structures 30”), in the second recessed areas (34), a dielectric liner (38, 46; Figs. 10-12; ¶ 0044 “dielectric material 38 remaining at the processing stage of FIG. 12 may be considered to be configured as liners 46”) on the gate layers (Figs. 10-12; ¶ 0044 “dielectric material 38 remaining at the processing stage of FIG. 12 may be considered to be configured as liners 46 extending within the cavities 34, and along the peripheral surfaces 31, 33 and 35 of such cavities”), and subsequently selectively depositing (Fig. 13) the blocking oxide (¶ 0045 “surfaces within opening 24 are exposed to oxidizing conditions…to form charge-blocking regions 48”) on the dielectric liner (Fig. 13).
Regarding Claim 18, Kim discloses wherein the gate layers are sacrificial gate layers (Fig. 20; ¶ 0071 “material 20 (FIG. 19) of the second levels 16 is removed”) and the method further comprises, subsequent to depositing the blocking oxide and the charge trap material (Fig. 20), replacing the sacrificial gate layers (Figs. 18-20; ¶ 0071 “material 20 (FIG. 19) of the second levels 16 is removed”) by a replacement metal gate stack (92, 94, 96; Figs. 21-22; ¶ 0072 “conductive materials 92 and 94 are provided within…the cavities 90”; ¶ 0074 “conductive materials 92 and 94 remaining within the cavities 90 together form conductive regions 96”; ¶ 0075 “Portions of the conductive regions 96 proximate the charge-blocking regions 48 may correspond to conductive gates 98, and portions of the conductive regions 96 more distal from the charge-blocking regions 48 may correspond to wordlines 160.”).
Regarding Claim 19, Kim discloses further comprising:
selectively depositing (Figs. 10-12; ¶ 0040 “a layer of dielectric barrier material 38 is formed to extend conformally along the peripheral surfaces 31, 33 and 35 within the gaps 34; and to extend along the outer edges 29 of the spacing structures 30”), in the second recessed areas (34), a dielectric liner (38, 46; Figs. 10-12; ¶ 0044 “dielectric material 38 remaining at the processing stage of FIG. 12 may be considered to be configured as liners 46”) on the gate layers (Figs. 10-12; ¶ 0044 “dielectric material 38 remaining at the processing stage of FIG. 12 may be considered to be configured as liners 46 extending within the cavities 34, and along the peripheral surfaces 31, 33 and 35 of such cavities”), and subsequently selectively depositing (Fig. 13) the blocking oxide (¶ 0045 “surfaces within opening 24 are exposed to oxidizing conditions…to form charge-blocking regions 48”) on the dielectric liner (Fig. 13);
wherein the gate layers are sacrificial gate layers (Fig. 20; ¶ 0071 “material 20 (FIG. 19) of the second levels 16 is removed”) and the method further comprises, subsequent to depositing the blocking oxide and the charge trap material (Fig. 20), replacing the sacrificial gate layers (Figs. 18-20; ¶ 0071 “material 20 (FIG. 19) of the second levels 16 is removed”) by a replacement metal gate stack (92, 94, 96; Figs. 21-22; ¶ 0072 “conductive materials 92 and 94 are provided within…the cavities 90”; ¶ 0074 “conductive materials 92 and 94 remaining within the cavities 90 together form conductive regions 96”; ¶ 0075 “Portions of the conductive regions 96 proximate the charge-blocking regions 48 may correspond to conductive gates 98, and portions of the conductive regions 96 more distal from the charge-blocking regions 48 may correspond to wordlines 160.”); and
utilizing the dielectric liner as an etch stop layer when removing the sacrificial gate layers to be replaced by the replacement metal gate stack (Fig. 20 the dielectric liner 38 is the etch stop when removing the sacrificial gate layers to be replaced by the replacement metal gate stack in Fig. 22).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (“Kim”), US 2019/0198520, in view of Kang et al., (“Kang”), US 2021/0399011 (listed in the IDS).
Regarding Claim 3, Kim does not disclose wherein the inter-gate spacer layers are oxide-comprising layers, such as SiO2 layers.
Kang discloses wherein the inter-gate spacer layers (106; Fig. 2; ¶ 0057 “layers 106”) are oxide-comprising layers (¶ 0057 “layers 106 comprise silicon oxide”), such as SiO2 layers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kim to have wherein the inter-gate spacer layers are oxide-comprising layers, such as SiO2 layers, as taught by Kang, because “layers 110 comprise a material that is etch selective relative to the first layers 106 so that the second layers 110 can be removed without substantially affecting the first layers 106” (Kang ¶ 0057), thereby improving the performance and reliability of the memory structure.
Regarding Claim 9, Kim does not disclose wherein the gate layers are nitride-comprising layers, such as SiN layers, or polysilicon-comprising layers.
Kand discloses wherein the gate layers (110; Fig. 2; ¶ ¶ 0057 “layers 110”) are nitride-comprising layers (¶ 0057 “layers 110 comprise nitride layers”), such as SiN layers (¶ 0057 “In one or more embodiments, the second layers 110 comprise silicon nitride (SiN”), or polysilicon-comprising layers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kim to have wherein the gate layers are nitride-comprising layers, such as SiN layers, or polysilicon-comprising layers, as taught by Kang, because “layers 110 comprise a material that is etch selective relative to the first layers 106 so that the second layers 110 can be removed without substantially affecting the first layers 106” (Kang ¶ 0057), thereby improving the performance and reliability of the memory structure.
Regarding Claim 10, Kim does not disclose wherein the inter-gate spacer layers are oxide-comprising layers, such as SiO2 layers.
Kang discloses wherein the inter-gate spacer layers (106; Fig. 2; ¶ 0057 “layers 106”) are oxide-comprising layers (¶ 0057 “layers 106 comprise silicon oxide”), such as SiO2 layers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kim to have wherein the inter-gate spacer layers are oxide-comprising layers, such as SiO2 layers, as taught by Kang, because “layers 110 comprise a material that is etch selective relative to the first layers 106 so that the second layers 110 can be removed without substantially affecting the first layers 106” (Kang ¶ 0057), thereby improving the performance and reliability of the memory structure.
Claims 6, 8, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (“Kim”), US 2019/0198520, in view of Zhou et al. (“Zhou”), US 10,283,513 (listed in the IDS).
Regarding Claim 6, Kim does not disclose wherein the charge trap material is grown laterally in the second recessed areas to a thickness in a range of 4-8 nm.
Zhou discloses wherein the charge trap material (54; Fig. 5H; col. 16 line 10 “charge storage layer 54 can be formed”) is grown laterally (Fig. 5H) in the second recessed areas (49; Fig. 5H; col. 15 line 25 “openings 49”) to a thickness in a range of 4-8 nm (col. 16 lines 62-63 “thickness of the charge storage layer 54 can be in a range from 2 nm to 20 nm”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kim to have wherein the charge trap material is grown laterally in the second recessed areas to a thickness in a range of 4-8 nm, as taught by Zhou, because “Each adjoining set of a blocking dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56 collectively constitute a memory film 50, which can store electrical charges with a macroscopic retention time.” (Zhou col. 29 lines 15-19), thereby improving the performance and reliability of the memory structure.
Regarding Claim 8, Kim does not disclose wherein the charge trap material is grown laterally in the second recessed areas to a thickness in a range of 4-8 nm.
Zhou discloses wherein the charge trap material (54; Fig. 5H; col. 16 line 10 “charge storage layer 54 can be formed”) is grown laterally (Fig. 5H) in the second recessed areas (49; Fig. 5H; col. 15 line 25 “openings 49”) to a thickness in a range of 4-8 nm (col. 16 lines 62-63 “thickness of the charge storage layer 54 can be in a range from 2 nm to 20 nm”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kim to have wherein the charge trap material is grown laterally in the second recessed areas to a thickness in a range of 4-8 nm, as taught by Zhou, because “Each adjoining set of a blocking dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56 collectively constitute a memory film 50, which can store electrical charges with a macroscopic retention time.” (Zhou col. 29 lines 15-19), thereby improving the performance and reliability of the memory structure.
Regarding Claim 11, Kim does not disclose wherein the sacrificial layers are metal oxide-layers, such as Al2O3 or TiO2 layers, metal-nitride layers, such as AlN or TiN layers, metal layers, such as Co, Ru, Cu, W or Mo layers, or carbon-comprising layers, such as amorphous carbon or organic spin-on layers.
Zhou discloses wherein the sacrificial layers (42; Fig. 2; col. 7 line 21 “sacrificial material layers 42”) are metal oxide-layers, such as Al2O3 or TiO2 layers, metal-nitride layers, such as AlN or TiN layers, metal layers (col. 7 lines 21-23 “sacrificial material layers 42 may comprise…a conductive material”), such as Co, Ru, Cu, W or Mo layers, or carbon-comprising layers, such as amorphous carbon or organic spin-on layers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kim to have wherein the sacrificial layers are metal oxide-layers, such as Al2O3 or TiO2 layers, metal-nitride layers, such as AlN or TiN layers, metal layers, such as Co, Ru, Cu, W or Mo layers, or carbon-comprising layers, such as amorphous carbon or organic spin-on layers, as taught by Zhou, because “sacrificial material layers 42 is a sacrificial material that can be removed selective to the first material of the insulating layers 32” (Zhou col. 7 lines 10-13), thereby improving the performance and reliability of the memory structure.
Allowable Subject Matter
Claims 12-15 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 12, the prior art does not teach or render obvious further comprising, prior to depositing the blocking oxide, functionalizing surface portions of the etched back gate layers in the second recessed areas and thereafter depositing the blocking oxide on the functionalized surface portions. Therefore, the combination of the features of Claims 1 and 12 is considered allowable.
Claims 13 and 15 incorporate all of the limitations of allowable Claim 12. Therefore, they are also allowable.
Regarding Claim 14, the prior art does not teach or render obvious further comprising, prior to depositing the blocking oxide, performing a treatment process adapted to passivate exposed surface portions of the sacrificial layers with respect to the selective deposition of the blocking oxide and the charge trap material. If the rejection of Claim 14 under §112(b), as explained supra, is overcome, then the combination of the features of Claims 1, 12, 13, and 14 is considered allowable.
Regarding Claim 17, the prior art does not teach or render obvious further comprising, prior to depositing the blocking oxide, performing a treatment process adapted to passivate exposed surface portions of the sacrificial layers with respect to the selective deposition of the blocking oxide and the charge trap material. If the rejection of Claim 17 under §112(b), as explained supra, is overcome, then the combination of the features of Claims 1 and 17 is considered allowable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim, US 10,438,962, discloses a method for forming a memory structure for a 3D NAND flash memory that includes forming a layer stack over a substrate, the layer stack comprising an alternating sequence of gate layers and inter-gate spacer layers, forming first recessed areas, forming sacrificial layers in the first recessed areas, forming second recessed areas, and forming in the second recess areas a blocking oxide and a charge trap material. Lai et al., US 2019/0096907, discloses a method for forming a memory structure for a 3D NAND flash memory that includes forming a layer stack over a substrate, the layer stack comprising an alternating sequence of gate layers and inter-gate spacer layers, forming second recessed areas, forming in the second recessed areas a charge trap material. Wang et al., US 2023/0134694, discloses a method for forming a memory structure for a 3D NAND memory that includes forming a layer stack over a substrate, the layer stack comprising an alternating sequence of gate layers and inter-gate spacer layers, forming a blocking oxide, and forming a charge trap material. Tseng, US 2023/0240071, discloses a method for forming a memory structure for a 3D NAND flash memory that includes forming a layer stack over a substrate, the layer stack comprising an alternating sequence of gate layers and inter-gate spacer layers, and forming a charge trap material.
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/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
