DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 16 is objected to because of the following informalities: Claim 16, line 5 recites “the control terminal of the fifth transistor”, which should be --a control terminal of the fifth transistor -- because this term was not previously presented in the claim.
Appropriate correction is required.
Claim 17 is objected to because of the following informalities: Claim 17, line 2 recites “a control terminal of the fifth transistor”, which should be --the control terminal of the fifth transistor -- because this term was previously presented in the claim.
Appropriate correction is required.
Claim 19 is objected to because of the following informalities: Claim 19, line 7 recites “an output current”, which should be --the output current -- because this term was previously presented in the claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7, 8, 10-13 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yao et al. (US 2015/0340890), hereinafter Yao, in view of Couleur et al. (US 2018/0097513), hereinafter Couleur.
Regarding claim 1, Yao discloses (see figures 1-5) a method (figure 2) comprising: providing (figure 2, part through 205) a voltage setpoint (figure 2, part V_OUT SETTING) to a voltage converter (figure 2, part voltage converter between Vin to Cout) wherein the voltage setpoint (figure 2, part V_OUT SETTING) is indicative of a target output voltage (figure 2, part V_OUT SETTING) of the voltage converter (figure 2, part voltage converter between Vin to Cout); generating an output voltage (figure 2, part Vout) at a voltage rail (figure 2, part voltage rail at Vout) with the voltage converter (figure 2, part voltage converter between Vin to Cout) based on the voltage setpoint (figure 2, part V_OUT SETTING) (paragraph [0026]; Controller 207 receives a V_OUT SETTING signal from the output voltage controller 205 and turns on and off transistor T1 accordingly. In some embodiments, the V_OUT SETTING signal is an error value between the output voltage level of the USB charger 200 and the voltage level requested by the client device 201. In other embodiments, the V_OUT SETTING signal may be a signal indicating which output voltage level to generate. For instance, the V_OUT SETTING may be a digital signal indicating that the client device requested a first voltage level (e.g. 5V) or a second voltage level (e.g. 12V)); when the voltage setpoint (figure 2, part V_OUT SETTING) is transitioning from a first voltage setpoint (figures 2 and 4, part V_OUT SETTING at first voltage setpoint Vdd1) to a second voltage setpoint (figures 2 and 4, part V_OUT SETTING at second voltage setpoint Vdd2) that has a lower magnitude than the first voltage setpoint (figures 2 and 4, part V_OUT SETTING at first voltage setpoint Vdd1), providing a signal to a first node (figure 3A, part first node at output of 205) coupled to a control terminal of an output switch (figure 3A, part S1; control terminal) to turn on the output switch (figure 3A, part S1; turn-on), wherein the output switch comprises a terminal (figure 3A, part S1; upper terminal) coupled to a first terminal of a first resistor (figure 3A, part R1; lower terminal), and a terminal (figure 3A, part S1; lower terminal) coupled to a first terminal of a load (figures 1 and 3A, part lower terminal of 201), wherein a second terminal of the first resistor (figure 3A, part R1; upper terminal) is coupled to a second terminal of the load (figures 1 and 3A, part upper terminal of 201), wherein the output switch (figure 3A, part S1) conducts an output current to or from (figure 3A, part S1; through turn-on conduction) the voltage rail (figures 2 and 3A, part voltage rail at Vout) (paragraph [0027]; When switch S1 is closed, a discharging path for Cout is created through R1), and wherein a change in the output current (figure 3A, part change of output current through S1 when is turn-on) is induced by a change in a voltage of the first node (figure 3A, part voltage of the first node at output of 205); and turning off the output switch (figure 3A, part S1; turn-off) after the output voltage (figure 2, part Vout) reaches the target output voltage (figure 2, part V_OUT SETTING) corresponding to the second voltage setpoint (figures 2 and 4, part V_OUT SETTING at second voltage setpoint Vdd2)(paragraphs [0018]-[0028]; Bleeder 203 creates a discharging path for output capacitor (Cout) to discharge. When the client device 201 requests for an output voltage level, lower than the current voltage level being outputted by the USB charger 200, the bleeder 203 is turned on by the output voltage controller 205 and the charge stored in the output capacitor Cout is discharged, thus lowering the voltage of the output of the USB charger 200… At t0, when switch S1 is closed, the output voltage starts lowering from a first voltage level Vdd1 to a second voltage level Vdd2. In one embodiment, the output voltage 401 reduces according to equation (1). Once the output voltage 401 reaches the second voltage level Vdd2, switch S1 is opened and the output voltage 401 is held constant at Vdd2).
Yao does not expressly disclose providing a first constant current to a first node coupled to a control terminal of an output transistor to turn on the output transistor, wherein the output transistor comprises a source terminal coupled to a first terminal of a first resistor, and a drain terminal coupled to a first terminal, wherein the output transistor conducts an output current to or from the voltage rail, and wherein the change in the output current is substantially linear; and turning off the output transistor.
Couleur teaches (see figures 1-4) providing a first constant current (figure 1, part I1 from current mirror 140) to a first node (figure 1, part 138) coupled to a control terminal of an output transistor (figure 1, part M1) to turn on the output transistor (figure 1, part M1; turn-on), wherein the output transistor (figure 1, part M1) comprises a source terminal (figure 1, part M1; source terminal) coupled to a first terminal of a first resistor (figure 1, part RL; upper terminal), and a drain terminal (figure 1, part M1; drain terminal), wherein a second terminal of the first resistor (figure 1, part RL; lower terminal), wherein the output transistor conducts (figure 1, part M1; turn-on) an current (figure 1, part ISF), and wherein a change in the current (figure 1, part change of ISF) is induced by a change in a voltage of the first node (figure 1, part VCTRL at 138), and wherein the change in the current is substantially linear (figure 1, part change of ISF; through charge/discharge current at C1) (figure 4, part IB); and turning off the output transistor (figure 1, part M1; turn-off) (paragraph [0013]; The transistor M1 generates an output current signal ISF that is proportional to the control voltage output signal VCTRL).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the discharge circuit of Yao with the arrangement and control features as taught by Couleur (more specific configure arrangement S1/R1 and the control circuit 205 of Yao with the arrangement M1/RL and the control VCTRL features as taught by Couleur) and obtain a method comprising: providing a voltage setpoint to a voltage converter, wherein the voltage setpoint is indicative of a target output voltage of the voltage converter; generating an output voltage at a voltage rail with the voltage converter based on the voltage setpoint; when the voltage setpoint is transitioning from a first voltage setpoint to a second voltage setpoint that has a lower magnitude than the first voltage setpoint, providing a first constant current to a first node coupled to a control terminal of an output transistor to turn on the output transistor, wherein the output transistor comprises a source terminal coupled to a first terminal of a first resistor, and a drain terminal coupled to a first terminal of a load, wherein a second terminal of the first resistor is coupled to a second terminal of the load, wherein the output transistor conducts an output current to or from the voltage rail, and wherein a change in the output current is induced by a change in a voltage of the first node, and wherein the change in the output current is substantially linear; and turning off the output transistor after the output voltage reaches the target output voltage corresponding to the second voltage setpoint, because it provides more efficient and stable control that reduce power losses in order enhanced energy efficiency (paragraph [0008]).
Regarding claim 2, Yao and Couleur teach everything claimed as applied above (see claim 1). Further, Yao discloses (see figures 1-5) turning off the output switch (figure 3A, part S1; turn-off). However, Yao does not expressly disclose providing a second constant current to the first node, wherein the second constant current has opposite direction than the first constant current.
Couleur teaches (see figures 1-4) turning off the output transistor (figure 1, part M1; turn-off) comprises providing a second constant current (figure 1, part second constant current through 136) to the first node (figure 1, part 138), wherein the second constant current (figure 1, part second constant current through 136) has opposite direction than the first constant current (figure 1, part I1 from current mirror 140).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the discharge circuit of Yao with the arrangement and control features as taught by Couleur (more specific configure arrangement S1/R1 and the control circuit 205 of Yao with the arrangement M1/RL and the control VCTRL features as taught by Couleur), because it provides more efficient and stable control that reduce power losses in order enhanced energy efficiency (paragraph [0008]).
Regarding claim 3, Yao and Couleur teach everything claimed as applied above (see claim 2). However, Yao does not expressly disclose providing the first constant current to the first node comprises injecting the first constant current to a capacitor coupled to the first node, and wherein providing the second constant current to the first node comprises sinking the second constant current from the capacitor.
Couleur teaches (see figures 1-4) providing the first constant current (figure 1, part I1 from current mirror 140) to the first node (figure 1, part 138) comprises injecting the first constant current (figure 1, part I1 from current mirror 140) to a capacitor (figure 1, part C1) coupled to the first node (figure 1, part 138), and wherein providing the second constant current (figure 1, part second constant current through 136) to the first node (figure 1, part 138) comprises sinking the second constant current (figure 1, part second constant current through 136) from the capacitor (figure 1, part C1).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the discharge circuit of Yao with the arrangement and control features as taught by Couleur (more specific configure arrangement S1/R1 and the control circuit 205 of Yao with the arrangement M1/RL and the control VCTRL features as taught by Couleur), because it provides more efficient and stable control that reduce power losses in order enhanced energy efficiency (paragraph [0008]).
Regarding claim 7, Yao and Couleur teach everything claimed as applied above (see claim 1). Further, Yao discloses (see figures 1-5) the output switch (figure 3A, part S1; turn-on). However, Yao does not expressly disclose providing the first constant current to the first node causes a first voltage ramp at the first node and a second voltage ramp at the source terminal of the output transistor.
Couleur teaches (see figures 1-4) providing the first constant current (figure 1, part I1 from current mirror 140) to the first node (figure 1, part 138) causes a first voltage ramp (figure 1, part voltage ramp at VCTRL) at the first node (figure 1, part 138) and a second voltage ramp at the source terminal of the output transistor (figure 1, part voltage ramp at source terminal of M1).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the discharge circuit of Yao with the arrangement and control features as taught by Couleur (more specific configure arrangement S1/R1 and the control circuit 205 of Yao with the arrangement M1/RL and the control VCTRL features as taught by Couleur), because it provides more efficient and stable control that reduce power losses in order enhanced energy efficiency (paragraph [0008]).
Regarding claim 8, Yao and Couleur teach everything claimed as applied above (see claim 1). Further, Yao discloses (see figures 1-5) the voltage setpoint (figure 2, part V_OUT SETTING) transitions from the first voltage setpoint (figures 2 and 4, part V_OUT SETTING at first voltage setpoint Vdd1) to the second voltage setpoint (figures 2 and 4, part V_OUT SETTING at second voltage setpoint Vdd2). However, Yao does not expressly disclose in discrete voltage steps
Couleur teaches (see figures 1-4) in discrete voltage steps (figure 1, part discrete voltage steps based on the charging and discharging steps of C1; reflected at 412 in figure 4).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the discharge circuit of Yao with the arrangement and control features as taught by Couleur (more specific configure arrangement S1/R1 and the control circuit 205 of Yao with the arrangement M1/RL and the control VCTRL features as taught by Couleur) and obtain the voltage setpoint transitions from the first voltage setpoint to the second voltage setpoint in discrete voltage steps, because it provides more efficient and stable control that reduce power losses in order enhanced energy efficiency (paragraph [0008]).
Regarding claim 10, Yao and Couleur teach everything claimed as applied above (see claim 1). Further, Yao discloses (see figures 1-5) the second terminal of the first resistor (figure 3A, part R1; upper terminal) is coupled to the voltage rail (figure 2, part voltage rail at Vout).
Regarding claim 11, Yao and Couleur teach everything claimed as applied above (see claim 1). Further, Yao discloses (see figures 1-5) generating the output voltage (figure 2, part Vout) comprises generating a positive output voltage (figure 2, part Vout), and wherein the first voltage setpoint corresponds to 12 V (figures 2 and 4, part V_OUT SETTING at first voltage setpoint Vdd1) and the second voltage setpoint corresponds to 5 V (figures 2 and 4, part V_OUT SETTING at second voltage setpoint Vdd2)(paragraph [0026]; the V_OUT SETTING may be a digital signal indicating that the client device requested a first voltage level (e.g. 5V) or a second voltage level (e.g. 12V)). However, Yao does not expressly disclose the first voltage setpoint corresponds to 20 V.
It would have been obvious matter of design choice to one having ordinary skill in the art before the effective filling date of the claimed invention to configure converter of the combination of Yao and Couleur and obtain generating the output voltage comprises generating a positive output voltage, and wherein the first voltage setpoint corresponds to 20 V and the second voltage setpoint corresponds to 5 V in order to obtain more accurate output voltage based on the design demand. Furthermore, the invention would perform equally well with the combination of Yao and Couleur.
Regarding claim 12, Yao and Couleur teach everything claimed as applied above (see claim 1). Further, Yao discloses (see figures 1-5) the terminal of the output switch (figure 3A, part S1) and the voltage rail (figure 2, part voltage rail at Vout). However, Yao does not expressly disclose the drain terminal of the output transistor is coupled to the voltage rail.
Couleur teaches (see figures 1-4) the drain terminal of the output transistor is coupled to the voltage rail (figure 1, part drain terminal of M1).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the discharge circuit of Yao with the arrangement and control features as taught by Couleur (more specific configure arrangement S1/R1 and the control circuit 205 of Yao with the arrangement M1/RL and the control VCTRL features as taught by Couleur), because it provides more efficient and stable control that reduce power losses in order enhanced energy efficiency (paragraph [0008]).
Regarding claim 13, Yao discloses (see figures 1-5) a circuit (figure 2, part 200) comprising: a voltage converter (figure 2, part voltage converter between Vin to Cout) having an output (figure 2, part voltage converter between Vin to Cout; output at upper terminal of Cout) coupled to a voltage rail (figure 2, part voltage rail at Vout) and configured to generate, at the output of the voltage converter (figure 2, part voltage converter between Vin to Cout; output at upper terminal of Cout), an output voltage (figure 2, part Vout) based on a voltage setpoint (figure 2, part V_OUT SETTING), wherein the voltage setpoint is indicative of a target output voltage (figure 2, part V_OUT SETTING) of the voltage converter (figure 2, part voltage converter between Vin to Cout)(paragraph [0026]; Controller 207 receives a V_OUT SETTING signal from the output voltage controller 205 and turns on and off transistor T1 accordingly. In some embodiments, the V_OUT SETTING signal is an error value between the output voltage level of the USB charger 200 and the voltage level requested by the client device 201. In other embodiments, the V_OUT SETTING signal may be a signal indicating which output voltage level to generate. For instance, the V_OUT SETTING may be a digital signal indicating that the client device requested a first voltage level (e.g. 5V) or a second voltage level (e.g. 12V)); an output switch (figure 2, part inside 203) (figure 3A, part S1) having a current path (figure 3A, part S1) coupled to the voltage rail (figures 2 and 3A, part voltage rail at Vout); a first resistor (figure 3A, part R1) having a first terminal (figure 3A, part R1; lower terminal) coupled to a terminal of the output switch (figure 3A, part S1; upper terminal); and a control circuit (figure 2, part 205) configured to: provide the voltage setpoint (figure 2, part V_OUT SETTING) to the voltage converter (figure 2, part voltage converter between Vin to Cout; through 207); cause the output switch (figure 3A, part S1) to conduct an output current to or from (figure 3A, part S1; through turn-on conduction) the voltage rail (figures 2 and 3A, part voltage rail at Vout) (paragraph [0027]; When switch S1 is closed, a discharging path for Cout is created through R1), wherein a change in the output current (figure 3A, part change of output current through S1 when is turn-on) is induced by a change in a voltage (figure 3A, part voltage output of 205 to S1) of a control terminal of the output switch (figure 3A, part S1); and cause the output switch to turn off (figure 3A, part S1; turn-off)after the output voltage (figure 2, part Vout) reaches the target output voltage (figures 2 and 4, part V_OUT SETTING at second voltage setpoint Vdd2)(paragraphs [0018]-[0028]; Bleeder 203 creates a discharging path for output capacitor (Cout) to discharge. When the client device 201 requests for an output voltage level, lower than the current voltage level being outputted by the USB charger 200, the bleeder 203 is turned on by the output voltage controller 205 and the charge stored in the output capacitor Cout is discharged, thus lowering the voltage of the output of the USB charger 200… At t0, when switch S1 is closed, the output voltage starts lowering from a first voltage level Vdd1 to a second voltage level Vdd2. In one embodiment, the output voltage 401 reduces according to equation (1). Once the output voltage 401 reaches the second voltage level Vdd2, switch S1 is opened and the output voltage 401 is held constant at Vdd2).
Yao does not expressly disclose an output transistor; a first resistor having a first terminal coupled to a source terminal of the output transistor; cause the output transistor to conduct an output current to or from the voltage rail, wherein a change in the output current is induced by a change in a voltage of a control terminal of the output transistor, and wherein the change in the output current is linear with the change in the voltage of the control terminal; and cause the output transistor to turn off.
Couleur teaches (see figures 1-4) an output transistor (figure 1, part M1) having a current path (figure 1, part ISF); a first resistor (figure 1, part RL) having a first terminal (figure 1, part RL; upper terminal) coupled to a source terminal of the output transistor (figure 1, part source terminal of M1); cause the output transistor to conduct (figure 1, part M1; turn-on) an current (figure 1, part ISF), wherein a change in the current (figure 1, part change of ISF) is induced by a change in a voltage (figure 1, part VCTRL at 138) of a control terminal of the output transistor (figure 1, part control terminal of M1), and wherein the change in the current is linear (figure 1, part change of ISF; through charge/discharge current at C1) (figure 4, part IB) with the change in the voltage of the control terminal (figure 1, part VCTRL at 138); and cause the output transistor to turn off (figure 1, part M1; turn-off) (paragraph [0013]; The transistor M1 generates an output current signal ISF that is proportional to the control voltage output signal VCTRL).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the discharge circuit of Yao with the arrangement and control features as taught by Couleur (more specific configure arrangement S1/R1 and the control circuit 205 of Yao with the arrangement M1/RL and the control VCTRL features as taught by Couleur) and obtain a circuit comprising: a voltage converter having an output coupled to a voltage rail and configured to generate, at the output of the voltage converter, an output voltage based on a voltage setpoint, wherein the voltage setpoint is indicative of a target output voltage of the voltage converter; an output transistor having a current path coupled to the voltage rail; a first resistor having a first terminal coupled to a source terminal of the output transistor; and a control circuit configured to: provide the voltage setpoint to the voltage converter; cause the output transistor to conduct an output current to or from the voltage rail, wherein a change in the output current is induced by a change in a voltage of a control terminal of the output transistor, and wherein the change in the output current is linear with the change in the voltage of the control terminal; and cause the output transistor to turn off after the output voltage reaches the target output voltage, because it provides more efficient and stable control that reduce power losses in order enhanced energy efficiency (paragraph [0008]).
Regarding claim 18, Yao and Couleur teach everything claimed as applied above (see claim 13). Further, Yao discloses (see figures 1-5) the change in the output current (figure 3A, part change of output current through S1 when is turn-on) to the change in the voltage of the control terminal (figure 3A, part voltage output of 205 to control terminal of S1). However, Yao does not expressly disclose a slope of the change in the output current to the change in the voltage of the control terminal changes while maintaining linear behavior.
Couleur teaches (see figures 1-4) a slope of the change in the output current (figure 1, part slope of change of ISF; through charge/discharge current at C1) to the change in the voltage of the control terminal (figure 1, part VCTRL at 138) changes while maintaining linear behavior (figure 1, part change of ISF) (figure 4, part IB).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the discharge circuit of Yao with the arrangement and control features as taught by Couleur (more specific configure arrangement S1/R1 and the control circuit 205 of Yao with the arrangement M1/RL and the control VCTRL features as taught by Couleur) and obtain a slope of the change in the output current to the change in the voltage of the control terminal changes while maintaining linear behavior, because it provides more efficient and stable control that reduce power losses in order enhanced energy efficiency (paragraph [0008]).
Regarding claim 19, claim 13 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 20, Yao and Couleur teach everything claimed as applied above (see claim 19). Further, Yao discloses (see figures 1-5) a first resistor (figure 3A, part R1) having a first terminal (figure 3A, part R1; lower terminal) coupled to a terminal of the output switch (figure 3A, part S1; upper terminal). However, Yao does not expressly disclose a first resistor having a first terminal coupled to a source terminal of the output transistor.
Couleur teaches (see figures 1-4) a first resistor having a first terminal (figure 1, part RL; upper terminal) coupled to a source terminal of the output transistor (figure 1, part M1; source terminal).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the discharge circuit of Yao with the arrangement and control features as taught by Couleur (more specific configure arrangement S1/R1 and the control circuit 205 of Yao with the arrangement M1/RL and the control VCTRL features as taught by Couleur), because it provides more efficient and stable control that reduce power losses in order enhanced energy efficiency (paragraph [0008]).
Claims 4, 5, 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yao et al. (US 2015/0340890), hereinafter Yao, in view of Couleur et al. (US 2018/0097513), hereinafter Couleur, and further in view of Abe (US 2004/0051581).
Regarding claim 4, Yao and Couleur teach everything claimed as applied above (see claim 3). Further, Yao discloses (see figures 1-5) the second terminal of the first resistor (figure 3A, part R1; upper terminal). However, Yao does not expressly disclose providing the first constant current comprises providing the first constant current using a first transistor having a current path coupled between a first supply voltage terminal and the first node, and wherein providing the second constant current comprises using a second transistor having a current path coupled between the first node and the second terminal of the first resistor.
Abe teaches (see figures 1-11) providing the first constant current (figure 1, part current through P7) comprises providing the first constant current (figure 1, part current through P7) using a first transistor (figure 1, part P7) having a current path coupled between a first supply voltage terminal (figure 1, part VDD; through P14) and the first node (figure 1, part first node at gate of N3), and wherein providing the second constant current (figure 1, part current through N5) comprises using a second transistor (figure 1, part N5) having a current path coupled between the first node (figure 1, part first node at gate of N3) and the second terminal of the first resistor (figure 1, part lower terminal of R2; through ground).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the combination of Yao and Couleur with the features as taught by Abe and obtain providing the first constant current comprises providing the first constant current using a first transistor having a current path coupled between a first supply voltage terminal and the first node, and wherein providing the second constant current comprises using a second transistor having a current path coupled between the first node and the second terminal of the first resistor, because it provides more efficient switching control in order to obtain more stable output (paragraph [0017]).
Regarding claim 5, Yao, Couleur and Abe teach everything claimed as applied above (see claim 4). Further, Yao discloses (see figures 1-5) turning off the output switch (figure 3A, part S1; turn-off). However, Yao does not expressly disclose turning off the first transistor and turning on a third transistor having a current path coupled between the first supply voltage terminal and a current path of a fourth transistor, the fourth transistor and the second transistor forming a first current mirror.
Abe teaches (see figures 1-11) turning off the output transistor (figure 1, part N3; turn-off) comprises turning off the first transistor (figure 1, part P7; turn-off) and turning on a third transistor (figure 1, part P6; turn-on) having a current path coupled between the first supply voltage terminal (figure 1, part VDD; through P14) and a current path of a fourth transistor (figure 1, part N4), the fourth transistor (figure 1, part N4) and the second transistor forming a first current mirror (figure 1, part N5).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the combination of Yao and Couleur with the features as taught by Abe, because it provides more efficient switching control in order to obtain more stable output (paragraph [0017]).
Regarding claim 14, Yao and Couleur teach everything claimed as applied above (see claim 13). Further, Yao discloses (see figures 1-5) the control circuit (figure 2, part 205) is configured to cause the output switch to turn off (figure 3A, part S1; turn-on). However, Yao does not expressly disclose a capacitor coupled to the control terminal of the output transistor; a first transistor having a current path coupled between a first supply voltage terminal and the control terminal of the output transistor; and a second transistor having a current path coupled between the control terminal of the output transistor and a second terminal of the first resistor, wherein the control circuit is configured to cause the first constant current to be provided to the control terminal of the output transistor by turning on the first transistor and turning off the second transistor, and wherein the control circuit is configured to cause the output transistor to turn off by turning off the first transistor and turning on the second transistor.
Couleur teaches (see figures 1-4) a capacitor (figure 1, part C1) coupled to the control terminal of the output transistor (figure 1, part control terminal of M1); a first switch (figure 1, part 134) having a current path coupled between a first supply voltage terminal (figure 1, part VDDA through 140) and the control terminal of the output transistor (figure 1, part control terminal of M1); and a second switch (figure 1, part 136) having a current path coupled between the control terminal of the output transistor (figure 1, part control terminal of M1) and a second terminal of the first resistor (figure 1, part RL; through 150), wherein the control circuit (figure 1, part control circuit generated by 120) is configured to cause the first constant current (figure 1, part I1) to be provided to the control terminal of the output transistor (figure 1, part control terminal of M1) by turning on the first switch (figure 1, part 134; turn-on) and turning off the second switch (figure 1, part 136; turn-off), and wherein the control circuit (figure 1, part control circuit generated by 120) is configured to cause the output transistor to turn off (figure 1, part M1; turn-off) by turning off the first switch (figure 1, part 134; turn-off) and turning on the second switch (figure 1, part 136; turn-on).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the discharge circuit of Yao with the features as taught by Couleur, because it provides more efficient and stable control that reduce power losses in order enhanced energy efficiency (paragraph [0008]).
Abe teaches (see figures 1-11) a first transistor (figure 1, part P7) having a current path coupled between a first supply voltage terminal (figure 1, part VDD; through P14) and the control terminal of the output transistor (figure 1, part first node at gate of N3); and a second transistor (figure 1, part N5) having a current path coupled between the control terminal of the output transistor (figure 1, part first node at gate of N3) and a second terminal of the first resistor (figure 1, part lower terminal of R2; through ground), wherein the control circuit (figure 1, part control circuit generated by R2/R1 and R2/D2) is configured to cause the first constant current (figure 1, part current through P7) to be provided to the control terminal of the output transistor (figure 1, part first node at gate of N3) by turning on the first transistor (figure 1, part P7; turn-on) and turning off the second transistor (figure 1, part N5; turn-off), and wherein the control circuit (figure 1, part control circuit generated by R2/R1 and R2/D2) is configured to cause the output transistor to turn off (figure 1, part N3; turn-off) by turning off the first transistor (figure 1, part P7; turn-off) and turning on the second transistor (figure 1, part N5; turn-on).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the combination of Yao and Couleur with the features as taught by Abe and obtain a capacitor coupled to the control terminal of the output transistor; a first transistor having a current path coupled between a first supply voltage terminal and the control terminal of the output transistor; and a second transistor having a current path coupled between the control terminal of the output transistor and a second terminal of the first resistor, wherein the control circuit is configured to cause a first constant current to be provided to the control terminal of the output transistor by turning on the first transistor and turning off the second transistor, and wherein the control circuit is configured to cause the output transistor to turn off by turning off the first transistor and turning on the second transistor, because it provides more efficient switching control in order to obtain more stable output (paragraph [0017]).
Regarding claim 15, Yao, Couleur and Abe teach everything claimed as applied above (see claim 14). Further, Yao discloses (see figures 1-5) the control circuit (figure 2, part 205). However, Yao does not expressly disclose a first current mirror comprising the second transistor and a third transistor; and a fourth transistor having a current path coupled between the first supply voltage terminal and a current path of the third transistor, wherein the control circuit is configured to turn on the second transistor by turning on the fourth transistor.
Abe teaches (see figures 1-11) a first current mirror (figure 1, part N4/N5) comprising the second transistor (figure 1, part N5) and a third transistor (figure 1, part N4); and a fourth transistor (figure 1, part P6) having a current path coupled between the first supply voltage terminal (figure 1, part VDD; through P14) and a current path of the third transistor (figure 1, part N4), wherein the control circuit (figure 1, part control circuit generated by R2/R1 and R2/D2) is configured to turn on the second transistor (figure 1, part N5; turn-on) by turning on the fourth transistor (figure 1, part P6; turn-on).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the combination of Yao and Couleur with the features as taught by Abe, because it provides more efficient switching control in order to obtain more stable output (paragraph [0017]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Yao et al. (US 2015/0340890), hereinafter Yao, in view of Couleur et al. (US 2018/0097513), hereinafter Couleur, and further in view of Duong et al. (US 2017/0199537), hereinafter Duong.
Regarding claim 16, Yao and Couleur teach everything claimed as applied above (see claim 13). Further, Yao discloses (see figures 1-5) the control circuit (figure 2, part 205). However, Yao does not expressly disclose a fifth transistor having a current path coupled between the control terminal of the output transistor and a second terminal of the first resistor, a second current mirror comprising a sixth transistor and a seventh transistor, the seventh transistor having a current path coupled the control terminal of the fifth transistor; and an eighth transistor having a current path coupled to a current path of the sixth transistor, wherein the control circuit is configured to turn off the fifth transistor by turning on the eighth transistor.
Duong teaches (see figures 1-13) a fifth transistor (figure 8, part M2) having a current path coupled between the control terminal of the output transistor (figure 8, part 121) and a second terminal of the first resistor (figure 8, part lower terminal of ESR; through ground), a second current mirror (figure 8, part N8/N9) comprising a sixth transistor (figure 8, part N8) and a seventh transistor (figure 8, part N9), the seventh transistor (figure 8, part N9) having a current path coupled a control terminal of the fifth transistor (figure 8, part M2); and an eighth transistor (figure 8, part P5) having a current path coupled to a current path of the sixth transistor (figure 8, part N8), wherein the control circuit (figure 8, part control circuit generated by 120 and 125) is configured to turn off the fifth transistor (figure 8, part M2; turn-off) by turning on the eighth transistor (figure 8, part P5; turn-on).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the combination of Yao and Couleur with the features as taught by Duong and obtain a fifth transistor having a current path coupled between the control terminal of the output transistor and a second terminal of the first resistor; a second current mirror comprising a sixth transistor and a seventh transistor, the seventh transistor having a current path coupled the control terminal of the fifth transistor; and an eighth transistor having a current path coupled to a current path of the sixth transistor, wherein the control circuit is configured to turn off the fifth transistor by turning on the eighth transistor, because it provides more efficient control with suppression of overshoot and undershoot at the output (paragraph [0013]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yao et al. (US 2015/0340890), hereinafter Yao, in view of Couleur et al. (US 2018/0097513), hereinafter Couleur, and further in view of applicant' s admitted prior art, hereinafter AAPA.
Regarding claim 9, Yao and Couleur teach everything claimed as applied above (see claim 1). Further, Yao discloses (see figures 1-5) generating the output voltage (figure 2, part Vout). However, Yao does not expressly disclose generating a negative output voltage, and wherein the first voltage setpoint corresponds to -9 V and the second voltage setpoint corresponds to -1 V.
AAPA teaches (see figure 2) generating the output voltage (figure 2, part Voutn) comprises generating a negative output voltage (figure 2, part Voutn), and wherein the first voltage setpoint corresponds to -5 V (figure 2, part Voutn) and the second voltage setpoint corresponds to -1 V (figure 2, part Voutn)(paragraphs [0005]-[0006]; DC-DC converter 202 with discharge circuit 104. When the voltage setpoint of DC-DC converter 102 is increased (e.g., from −5 V to −1 V), voltage Vg.sub.108 transitions from low to high to fully turn on transistor 108 and discharge output voltage V.sub.outn to facilitate the increase of the output voltage V.sub.outn. Once the output voltage V.sub.outn reaches the new target (e.g., −1 V), voltage Vg.sub.108 transitions from high to low to fully turn off transistor 108 and stop discharging the output voltage V.sub.outn).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the voltage converter of Yao with the inverting DC-DC converter feature as taught by AAPA , because it provides efficient power conversion for inverting demand.
It would have been obvious matter of design choice to one having ordinary skill in the art before the effective filling date of the claimed invention to configure converter of the combination of Yao and Couleur and obtain generating a negative output voltage, and wherein the first voltage setpoint corresponds to -9 V and the second voltage setpoint corresponds to -1 V in order to obtain more accurate output voltage based on the design demand. Furthermore, the invention would perform equally well with the combination of Yao and Couleur.
Allowable Subject Matter
Claims 6 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims (additional of fix any objection presented above).
The following is a statement of reasons for the indication of allowable subject matter: The closest prior art (which has been made of record) fail to disclose (by themselves or in combination):
Regarding claim 6, when the voltage setpoint is transitioning from the first voltage setpoint to the second voltage setpoint: turning off a fifth transistor having a current path coupled between the first node and the second terminal of the first resistor, wherein turning off the fifth transistor comprises turning on a sixth transistor having a current path coupled to a second current mirror that is coupled to the control terminal of the fifth transistor; and turning on a seventh transistor comprising a control terminal coupled to the first node, wherein a current path of the seventh transistor is coupled between a control terminal of the fifth transistor and the voltage rail, wherein the seventh transistor is coupled between the control terminal of the fifth transistor and a second resistor;
Regarding claim 17, a ninth transistor having a current path coupled between a control terminal of the fifth transistor and the second terminal of the first resistor; and a second resistor coupled between the current path of the ninth transistor and the second terminal of the first resistor;
In combination with the additionally claimed features, as are claimed by the Applicant. Thus, the Applicant’s claims are determined to be novel and non-obvious.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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