DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 8-9, 11-12, 18-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2020/0007362).
Claim 1, Kim discloses a driver circuit (Fig. 4A, 5A, 7) comprising:
a plurality of transistors that includes pullup transistors (two pullup transistors, Figs. 5A) that are coupled between an output (OUTtx, Fig. 5A) of the driver circuit and a first power rail (VDD) and pulldown transistors (two pulldown transistors, Fig. 5A) that are coupled between the output (OUTtx) of the driver circuit and a second power rail (ground); and
a logic circuit (Encoder 20_2 and MUX 30, Fig. 4A) configured to: turn on a predefined number of transistors during each data transmission interval configured for a data communication channel (OUTtx), the transistors that are turned on being selected during the each data transmission interval from the plurality of transistors based on a value of multibit data to be encoded in signaling state of the data communication channel (see Fig. 7), and turn off transistors in the plurality of transistors that are not selected from the plurality of transistors based on the value of multibit data to be encoded in signaling state of the data communication channel (see Fig. 7), wherein each transistor in the plurality of transistors is configured to contribute a same nominal impedance to the output of the driver circuit when turned on (all four transistors, each has the same impedance or resistance, see Fig. 5A), and wherein the driver circuit is configured to present a same nominal output impedance to the data communication channel for each value of the multibit data to be encoded (see Figs. 7, 9 and P[0123]-[0127] …the output driver 20 maintains impedance matching characteristics under all input conditions of the signal input from the first to fourth driver signal lines…).
Claim 2, Kim discloses the driver circuit of claim 1, wherein the multibit data is to be encoded using pulse-amplitude modulation (see Fig. 4A and P[0087]… the PAM-3 signaling…).
Claim 8, Kim discloses the driver circuit of claim 1, wherein the pullup transistors and the pulldown transistors comprise N-type metal-oxide-semiconductor transistors (all the transistors are NMOS transistors, Fig. 5A).
Claim 9, Kim discloses the driver circuit of claim 1, wherein the multibit data to be encoded comprises a two-bit number (see P[0088]… receive data of three bits of A, B, and C…).
Claims 11-12, 18-19 are rejected as above claims since the elements and limitations are similar.
Claim(s) 1-7, 9-17, 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wilson (US 10,404,505) and evidence by Lee et al. (US 2019/0303339).
Claim 1, Wilson discloses a driver circuit (transmitter 902 and 904, Figs. 9-12) comprising:
a plurality of transistors that includes pullup transistors (PMOS transistors in Figs. 9-12) that are coupled between an output (TR-∑) of the driver circuit and a first power rail (VDDQ) and pulldown transistors (NMOS transistors in Figs. 9-12) that are coupled between the output of the driver circuit and a second power rail (ground); and
a logic circuit (Controller 910) configured to: turn on a predefined number of transistors during each data transmission interval (see Figs. 9-12, transistors that are indicated as CLOSED) configured for a data communication channel (Line 908), the transistors (transistors that are indicated as CLOSED in Figs. 9-12) that are turned on being selected during the each data transmission interval from the plurality of transistors based on a value of multibit data (LSB and MSB) to be encoded in signaling state of the data communication channel, and turn off transistors (transistors that are indicated as OPEN in Figs. 9-12) in the plurality of transistors that are not selected from the plurality of transistors based on the value of multibit data to be encoded in signaling state of the data communication channel,
wherein each transistor in the plurality of transistors is configured to contribute a same nominal impedance to the output of the driver circuit when turned on (see col. 5, lines 1-15,… Each section is designed to have a pull-up and pull-down resistance of 120Ω…), and wherein the driver circuit is configured to present a same nominal output impedance (see col. 5, lines 1-15,… as there are three sections and each section is always activated, either in a pull-up or pull-down state, the overall equivalent resistance is 40Ω…) to the data communication channel for each value of the multibit data to be encoded.
Claim 2, Wilson discloses the driver circuit of claim 1, wherein the multibit data is to be encoded using pulse-amplitude modulation (see col. 5, lines 1-15,… PAM-4 POD driver would be constructed…).
Claim 3, Wilson discloses the driver circuit of claim 2, wherein the logic circuit is configured to turn on three transistors during each data transmission interval, the three transistors including: three pullup transistors (see Fig. 9, three PMOS transistors are CLOSED) when the multibit data to be encoded has a first value; two pullup transistors and one pulldown transistors (see Fig. 10, two PMOS transistors and one NMOS transistor are CLOSED) when the multibit data to be encoded has a second value; one pullup transistors and two pulldown transistors (see Fig. 11, one PMOS transistor and two NMOS transistors are CLOSED) when the multibit data to be encoded has a third value; and three pulldown transistors (see Fig. 12, three NMOS transistors are CLOSED) when the multibit data to be encoded has a fourth value.
Claim 4, Wilson discloses the driver circuit of claim 1, wherein four different signaling states are defined for the data communication channel (see Figs. 9-12 and col. 4, lines 47-67).
Claim 5, Wilson discloses the driver circuit of claim 4, wherein a combination of pullup transistors and pulldown transistors turned on during each data transmission interval produce voltage levels in the data communication channel that correspond to one of the four different signaling states (see Figs. 9-12 and col. 4, lines 47-67).
Claim 6, Wilson discloses the driver circuit of claim 1, wherein the plurality of transistors includes differentially controlled transistor pairs (PMOS transistor and NMOS transistor are differentially controlled transistor pairs) and a pulldown transistor that is enabled when no pullup transistor in the plurality of transistors is enabled (see Figs. 9-12, NMOS transistor are CLOSED when PMOS transistor OPEN and vice versa).
Claim 7, Wilson discloses the driver circuit of claim 1, wherein the plurality of transistors includes differentially controlled transistor pairs (see Figs. 9-12, three PMOS transistors and three NMOS transistors).
Claim 9, Wilson discloses the driver circuit of claim 1, wherein the multibit data to be encoded comprises a two-bit number (LSB and MSB, see Figs. 9-12 and col. 4, lines 47-67).
Claim 10, Wilson discloses the driver circuit of claim 9, wherein the two-bit number is received in a serial datastream (evidence by Lee, see Fig. 2 and P[0033]…serial data..).
Claims 11-17, 19-20 are rejected as above since the elements and limitations are similar.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH Q TRAN whose telephone number is (571)272-1813. The examiner can normally be reached M-F: 9AM - 5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander H Taningco can be reached at 571-272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANH Q TRAN/Primary Examiner, Art Unit 2845 6/24/26
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