Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 12,120,865 B2 to Huang et al.
Although the claims at issue are not identical, they are not patentably distinct from each other because the parent patent renders obvious the instant application.
Regarding independent claim 1: Huang teaches (Claims 1-11) an integrated circuit (IC) structure, comprising:
a first memory cell comprising:
a first access transistor comprising a gate electrode, source, and drain; a first capacitor on a first side of the first access transistor;
a first metallization feature between the first capacitor and the first transistor, the first metallization feature interconnecting a terminal of the first capacitor to a first of the source or drain of the first access transistor; and
a second memory cell comprising: a second access transistor comprising a gate electrode, source and drain, and in a vertical stack with the first access transistor; and
a second capacitor on a second side of second access transistor, opposite the first capacitor; a second metallization feature between the second capacitor and the second transistor,
the second metallization feature interconnecting a terminal of the second capacitor to a first of the source or drain of the second access transistor (Claim 1).
Regarding claim 2: Huang teaches the claim limitation of the IC structure of claim 1, from which this claim depends,
further comprising: a first interconnect on the first side of the first access transistor and coupled to the gate electrode of the first access transistor; and a second interconnect on the first side of the first access transistor and coupled to a second of the source or drain of the first access transistor (Claim 1).
Regarding claim 3: Huang teaches the claim limitation of the IC structure of claim 2, from which this claim depends,
wherein the first of the source or drain of the first access transistor is spaced apart from the first of the source and drain of the second access transistor by an intervening dielectric material (Claim 2).
Regarding claim 4: Huang teaches the claim limitation of the IC structure of claim 2, from which this claim depends,
wherein the first interconnect extends in a first horizontal direction, and the second interconnect extends in a second horizontal direction, orthogonal to the first horizontal direction (Claim 3).
Regarding claim 5: Huang teaches the claim limitation of the IC structure of claim 3, from which this claim depends,
wherein the second interconnect is also coupled to a second of the source or drain of the second access transistor (Claim 4).
Regarding claim 6: Huang teaches the claim limitation of the IC structure of claim 2, from which this claim depends,
wherein the gate electrode of the first access transistor electrically couples the first interconnect to the gate electrode of the second access transistor (Claim 4).
Regarding claim 7: Huang teaches the claim limitation of the IC structure of claim 2, from which this claim depends,
further comprising: a third interconnect on the second side of the second access transistor and coupled to the gate electrode of the second access transistor (Claim 4).
Regarding claim 8: Huang teaches the claim limitation of the IC structure of claim 2, from which this claim depends,
wherein the second interconnect is shared between two adjacent cells of a memory array, and the second interconnect is coupled to the source or drain of a third access transistor adjacent to the first access transistor (Claim 5).
Regarding claim 9: Huang teaches the claim limitation of the IC structure of claim 8, from which this claim depends,
further comprising a third capacitor on the first side of the third access transistor, and wherein: each of the first and second capacitors comprises a metal-insulator-metal (MIM) structure; and the insulator of the MIM structure comprises a ferroelectric or a dielectric material (Claim 10).
Regarding claim 10: Huang teaches the claim limitation of the IC structure of claim 1, from which this claim depends,
wherein the first and second access transistors each comprise monocrystalline semiconductor material including silicon or germanium (Claim 10).
Regarding independent claim 11: Huang teaches (e.g., Claims 12-14) an integrated circuit (IC) structure, comprising:
a first plurality of metal-insulator-metal (MIM) capacitors within a first plane of the IC structure; a second plurality of MIM capacitors within a second plane of the IC structure; a first plurality of access transistors within a third plane of the IC structure, between the first and second planes,
wherein: individual ones of the first plurality of access transistors comprise a gate electrode, source, and drain; and first metallization features interconnect a terminal of an individual ones of the first MIM capacitors to a first of the source or drain of individual ones of the first access transistors; and a second plurality of access transistors within a fourth plane of the IC structure, between the third and second planes,
wherein: individual ones of the second plurality of access transistors comprise a gate electrode, source, and drain; and second metallization features interconnecting a terminal of an individual ones of the second MIM capacitors to a first of the source or drain of individual ones of the second access transistors (Claim 12).
Regarding claim 12: Huang teaches the claim limitation of the IC structure of claim 11, from which this claim depends,
wherein: a pair of the first and second access transistors comprise a stack of channel regions and one or more gate electrodes around the stack of channel regions; the first access transistor of the pair of transistors comprises a first source and drain coplanar with a first of the channel regions; and the second access transistor of the pair of transistors comprises a second source and drain coplanar with a second of the channel regions (Claim 13).
Regarding claim 13: Huang teaches the claim limitation of the IC structure of claim 11, from which this claim depends,
further comprising a wordline interconnect extending in a first direction on a first side of a row of the first access transistors, wherein the wordline interconnect is electrically coupled to gate electrodes of the first access transistors within the row; a bitline interconnect extending in a second direction, orthogonal to the first direction, on the first side of a column of the first access transistors, wherein the bitline interconnect is coupled to a second of the source or drain of the first access transistors within the column (Claim 13).
Regarding claim 14: Huang teaches the claim limitation of the IC structure of claim 13, from which this claim depends,
further comprising an interconnect on a second side of the second access transistors, opposite the first side, and coupled to one of: a source or drain of a row or column of the second access transistors; a gate electrode of a row or column of the second access transistors; or a second terminal of a row or column of the second MIM capacitors (Claim 13).
Regarding claim 15: Huang teaches the claim limitation of the IC structure of claim 11, from which this claim depends,
further comprising logic circuitry comprising a plurality of p-type and n-type field effect transistor structures within the third plane or fourth plane of the IC structure (Claim 13).
Regarding independent claim 11: Huang teaches (e.g., Claims 1-11) an integrated circuit (IC) structure, comprising:
a first plurality of metal-insulator-metal (MIM) capacitors within a first plane of the IC structure; a second plurality of MIM capacitors within a second plane of the IC structure; a first plurality of access transistors within a third plane of the IC structure, between the first and second planes,
wherein: individual ones of the first plurality of access transistors comprise a gate electrode, source, and drain; and first metallization features interconnect a terminal of an individual ones of the first MIM capacitors to a first of the source or drain of individual ones of the first access transistors; and a second plurality of access transistors within a fourth plane of the IC structure, between the third and second planes,
wherein: individual ones of the second plurality of access transistors comprise a gate electrode, source, and drain; and second metallization features interconnecting a terminal of an individual ones of the second MIM capacitors to a first of the source or drain of individual ones of the second access transistors (Claim 1).
Regarding claim 16: Huang teaches the claim limitation of the IC structure of claim 11, from which this claim depends,
wherein: individual ones of the first and second pluralities of MIM capacitors comprise a ferroelectric or a dielectric insulator material; and the first and second access transistors each comprise monocrystalline semiconductor material including silicon or germanium (Claim 10).
Regarding independent claim 17: Huang teaches (e.g., Claims 15-20) a method comprising:
forming a stack of channel regions; forming one or more gate electrodes around the stack of channel regions;
forming a stack of source and drain regions comprising a first pair of source and drain regions electrically coupled to a first of the channel regions, and over a second pair of source and drain regions electrically coupled to a second of the channel regions;
forming a plurality of first metal-insulator metal (MIM) capacitors on a first side of the stack of channel regions, wherein individual ones of the first MIM capacitors are electrically coupled to a first of the first pair of source and drain regions;
forming a plurality of second MIM capacitors on a second side of the stack of channel regions, wherein individual ones of the second MIM capacitors are electrically coupled to a first of the second pair of source and drain regions; forming on the first side of the stack of channel regions a wordline interconnect to the one or more gate electrodes; and forming on the first side of the stack of channel regions a bitline interconnect to a second of the first pair of source and drain regions (Claim 15).
Regarding claim 18: Huang teaches the claim limitation of the method of claim 17, on which this depends,
further comprising forming on the second side of the stack of channel regions an interconnect to either a second of the second pair of source and drain regions, or to a second one of the gate electrodes (Claim 15).
Regarding claim 19: Huang teaches the claim limitation of the method of claim 17, on which this depends, further comprising:
bonding the first side to a host substrate after forming at least the wordline interconnect; and removing a donor substrate exposing the second side prior to forming the second MIM capacitors (Claim 20).
Claim 20 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. U.S. Patent No. US 12,120,865 B2 to Huang et al. in view of Chanemougame et al. (US 10,090,193 B1).
Regarding claim 20: Huang teaches the claim limitation of the method of claim 17, on which this depends,
Huang does not expressly teach that forming the stack of channel regions comprises growing a stack of semiconductor material layers comprising silicon or germanium.
Chanemougame teaches (e.g., Figs. 1-5) a method comprising
forming a stack of channel regions (Col. 6, Lines 59-67 and Col. 7, Lines 1-45) comprises growing a stack of semiconductor material layers comprising silicon or germanium (Col. 12, Lines 61-67 and Col. 13, Lines 1-28).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Huang, the method of forming the stack of channel regions comprising growing a stack of semiconductor material layers comprising silicon or germanium, as taught by Chanemougame, because silicon is the most abundant semiconductor material in the industry of semiconductor manufacturing device and the technology associated with growing silicon material is well established.
Allowable Subject Matter
Claims 1-20 would be allowable if all the rejections included above are overcome.
Regarding claim 1: allowable subject matter:
“a second memory cell comprising: a second access transistor comprising a gate electrode, source and drain, and in a vertical stack with the first access transistor; and a second capacitor on a second side of second access transistor, opposite the first capacitor; a second metallization feature between the second capacitor and the second transistor, the second metallization feature interconnecting a terminal of the second capacitor to a first of the source or drain of the second access transistor”.
Regarding claim 11: allowable subject matter:
“a second plurality of access transistors within a fourth plane of the IC structure, between the third and second planes, wherein: individual ones of the second plurality of access transistors comprise a gate electrode, source, and drain; and second metallization features interconnecting a terminal of an individual ones of the second MIM capacitors to a first of the source or drain of individual ones of the second access transistors”.
Regarding claim 17: allowable subject matter:
“electrically coupled to a first of the first pair of source and drain regions; forming a plurality of second MIM capacitors on a second side of the stack of channel regions, wherein individual ones of the second MIM capacitors are electrically coupled to a first of the second pair of source and drain regions; forming on the first side of the stack of channel regions a wordline interconnect to the one or more gate electrodes; and forming on the first side of the stack of channel regions a bitline interconnect to a second of the first pair of source and drain regions”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812
