DETAILED ACTION
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: image sensor and model generation unit in claim 1.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof:
Referring to the specifications as filed, the image sensor corresponds to pg. 11 “image sensor 100 may be a charge-coupled device (CCD) camera”, and the model generation unit corresponds to pg. 13 “the model generation unit 400 may be implemented in the form of a separate processor, device, or module that learns corresponding pair information of the crop data to generate clean data.”.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al (US Patent 11551348 B2).
Regarding claim 1, Zhang discloses a learning-based die-to-die mask inspection apparatus (col 11 lines 54-55 the DML described herein may be used for die-to-die type inspection or cell-to-cell type inspection) comprising:
an image sensor (col 7 lines 29-32 The one or more detectors may include photo-multiplier tubes (PMTs), charge coupled devices (CCDs), time delay integration (TDI) cameras, and any other suitable detectors known in the art) that acquires images of dies of a mask (col 15 lines 1-17 the test images may include N BBP images 202 and 204 from N adjacent dies and one design image 200. These images may be selected from the same die coordinates with identical fields of view (FOV) (i.e., the same die coordinates in multiple dies centered on the same within die location));
a processor (col 8 lines 16-25 the term “computer system” may be broadly defined to encompass any device having one or more processors, which executes instructions from a memory medium. The computer subsystem(s) or system(s) may also include any suitable processor known in the art such as a parallel processor) that generates crop data of corresponding pairs for the same region of the dies from the images acquired by the image sensor (col 15 lines 1-17 the test images may include N BBP images 202 and 204 from N adjacent dies and one design image 200. These images may be selected from the same die coordinates with identical fields of view (FOV) (i.e., the same die coordinates in multiple dies centered on the same within die location; e.g. FOV regions correspond to crop data), inputs the crop data to the model generation unit (col 15 lines 1-25 as shown in FIG. 2, design image 200 is input to first CNN 206 in Block A 208, optical image 202 is input to CNN 210 in Block A, and optical image 204 is input to CNN 212 in Block A. CNNs 206, 210, and 212 generate reference features for each of the input images, respectively. These CNNs may have any suitable configuration known in the art), receives the clean mask from the model generation unit, and then detects a defect in each of the dies through the crop data and the clean mask (col 15 lines 1-17 First, the test images go through Block A to calculate the reference features, which is the average of N outputs from Block A. Second, both test and reference features go through Block B to measure the distance between them based on the outputs from Block B. Third, Block C is applied to generate the final labels (defective vs. non-defective) for each image pixel location.).
Zhang teaches in another embodiment a model generation unit that generates a clean mask using a pre-trained model (col 18 lines 13-35 the corresponding reference image includes a non-defective test image for the specimen, projecting the corresponding reference image includes learning a reference region in the latent space, and the one or more portions of the corresponding reference image used for determining the distance include the reference region; The “non-defective” test image may be generated using the specimen, e.g., by imaging a known defect free portion of the specimen. The “non-defective” test image may also or alternatively be generated from a test image having an unknown defectivity (with a network or model configured to generate a reference image from a test image having unknown defectivity; e.g. the “non-defective” test image corresponds to the clean mask);
receives the clean mask from the model generation unit (col 18 lines 13-35 the corresponding reference image includes a non-defective test image for the specimen, projecting the corresponding reference image includes learning a reference region in the latent space, and the one or more portions of the corresponding reference image used for determining the distance include the reference region); and then detects a defect in each of the dies through the crop data and the clean mask (col 18 lines 13-35 the DML defect detection model can project both “defective” and “non-defective” test images into the latent space, learn the reference region in the latent space, and use it to determine if the one or more portions of the test image are a defect or not with respect to the reference region).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the corresponding die inspection process of Zhang to utilize the learned non-defective reference image generation technique also disclosed by Zhang. Both embodiments are directed to improving semiconductor defect inspection by generating a reliable reference representation and comparing inspection information against the reference representation to identify defects. One of ordinary skill in the art would have been motivated to use the generated non-defective reference image as the reference representation for corresponding die image regions because doing so would provide an improved defect-free baseline and reduce false defect detections caused by image variation, alignment differences, and inspection noise.
The combination would have resulted in an inspection apparatus wherein corresponding image regions from multiple dies are provided to a learned model to generate a non-defective reference image, and defects are detected by evaluating the die image regions using the generated reference image.
Regarding claim(s) 8 (drawn to a method):
The rejection/proposed combination of Zhang, explained in the rejection of apparatus claim(s) 1, anticipates/renders obvious the steps of the method of claim(s) 8 because these steps occur in the operation of the proposed combination as discussed above. Thus, the arguments similar to that presented above for claim(s) 1 is/are equally applicable to claim(s) 8.
Claim(s) 4 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang as applied to claim 1 and 8 above, and further in view of Gao et al (US Patent 10127652 B2).
Regarding claim 4, Zhang discloses apparatus of claim 1, but fails to teach where Gao teaches wherein, when ground truth (GT) is not present, the model generation unit generates the clean mask by adding the corresponding pairs so that defect information disappears (col 9 lines 45-52 the standard reference image may be generated from multiple images acquired by the wafer inspection system corresponding to different dies on the wafer. In one such example, one can construct an “average” image or a “median” image by taking the pixel-wise average (or median) over a collection of images corresponding to different dies).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to have implemented the teaching of wherein, when ground truth (GT) is not present, the model generation unit generates the clean mask by adding the corresponding pairs so that defect information disappears from Gao into the mask inspection apparatus as disclosed by Zhang. The motivation for doing this is to improve inspecting and classifying defects detected on a wafer.
Regarding claim(s) 11 (drawn to a method):
The rejection/proposed combination of Zhang and Gao, explained in the rejection of apparatus claim(s) 11, anticipates/renders obvious the steps of the method of claim(s) 4 because these steps occur in the operation of the proposed combination as discussed above. Thus, the arguments similar to that presented above for claim(s) 11 is/are equally applicable to claim(s) 4.
Claim(s) 5 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang as applied to claim 1 and 8 above, and further in view of Sakai et al (US 20120141011).
Regarding claim 5, Zhang discloses the apparatus of claim 1, wherein the processor generates the crop data of the corresponding pairs for the same region of the dies from the images acquired by the image sensor (col 15 lines 1-17 the test images may include N BBP images 202 and 204 from N adjacent dies and one design image 200. These images may be selected from the same die coordinates with identical fields of view (FOV) (i.e., the same die coordinates in multiple dies centered on the same within die location; e.g. FOV regions correspond to crop data), transmits the crop data of the corresponding pair to the model generation unit (col 15 lines 1-25 as shown in FIG. 2, design image 200 is input to first CNN 206 in Block A 208, optical image 202 is input to CNN 210 in Block A, and optical image 204 is input to CNN 212 in Block A. CNNs 206, 210, and 212 generate reference features for each of the input images, respectively. These CNNs may have any suitable configuration known in the art), but fails to teach where Sakai teaches extracts a difference image by comparing the crop data with the clean mask (¶73 acquiring a difference between the defect image 80 and the reference image 81), and detects a defect by removing mask information from the extracted difference image (¶73 Next, the matching processing unit 47 prepares a defect mask image 83 that is generated by removing the defect portion extraction image 82 from the defect image 80, that is, an image that masks the defect portion extraction image 82 of the defect image 80; the matching processing unit 47 extracts a contour from the defect mask image 83 and acquires a contour extraction result 84).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to have implemented the teaching of extracts a difference image by comparing the crop data with the clean mask, and detects a defect by removing mask information from the extracted difference image from Sakai into the mask inspection apparatus as disclosed by Zhang. The motivation for doing this is to improve semiconductor defect classifying technology using the image processing technology for a defect image.
Regarding claim(s) 12 (drawn to a method):
The rejection/proposed combination of Zhang and Sakai, explained in the rejection of apparatus claim(s) 12, anticipates/renders obvious the steps of the method of claim(s) 5 because these steps occur in the operation of the proposed combination as discussed above. Thus, the arguments similar to that presented above for claim(s) 12 is/are equally applicable to claim(s) 5.
Claim(s) 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Zhang and Sakai as applied to claim 5 above, and further in view of Hwang et al (US 20130244403).
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Zhang as applied to claim 8 above, and further in view of Hwang et al (US 20130244403).
Regarding claim 6, the combination of Zhang and Sakai discloses the apparatus of claim 5, but fail to teach where Hwang teaches wherein the processor detects a start position of each of the dies and extracts the crop data by cropping a local region of the die according to a size of a region to be cropped based on the start position (¶38 Then, the trimming part 300 moves laterally in a pre-programmed circular path. Specifically, the trimming part 300 first moves away from its starting position towards the corner 121 of the semiconductor chip 111. At the same time, before the trimming part 300 reaches corner 121 of the semiconductor chip 111, the trimming part 300 begins to rotate along its longitudinal axis at a predetermined RPM. When the trimming part 300 reaches the corner 121 of the semiconductor chip 111, the side wall of the cylindrical trimming part 300, which is covered with a plurality of grinding grit, being in physical contact with the semiconductor chips' corners. As a result, the cylindrical trimming part 300 removes portions of semiconductor material from the corner 121 of the semiconductor chip 111 (i.e., trimming corner 121 of the semiconductor chip 111); ¶39 the trimming part 300 has removed the pre-determined amount of material from the corner 121 of the semiconductor chip 111).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to have implemented the teaching of wherein the processor detects a start position of each of the dies and extracts the crop data by cropping a local region of the die according to a size of a region to be cropped based on the start position from Hwang into the mask inspection apparatus as disclosed by the combination of Zhang and Sakai. The motivation for doing this is to improve semiconductor chip shape modification and the apparatus for making such modification.
Regarding claim 7, the combination of Zhang, Sakai, and Hwang discloses the apparatus of claim 6, wherein the crop data is formed to have the same preset size and shape (Hwang ¶33 the amount of semiconductor material to be trimmed is also determined by the duration of the trimming operation and the width of the trimming part diameter, both of which can be controlled and preset; ¶34 the corners of the semiconductor chips 101, 102, 103, and 104 have been trimmed and achieved an intended rounded shape, a cutting device will then be used to dice the semiconductor wafer 100 into semiconductor chips; ¶35 FIG. 5 provides a more detailed illustration with respect to how the trimming part 300 operates to alter the geometric shape of the semiconductor chip corners; wherein they are cropped to have the same size and shape). The motivation to combine the references is discussed above in the rejection for claim 6.
Regarding claim(s) 13-14 (drawn to a method):
The rejection/proposed combination of Zhang and Hwang, explained in the rejection of apparatus claim(s) 13-14, anticipates/renders obvious the steps of the method of claim(s) 6-7 because these steps occur in the operation of the proposed combination as discussed above. Thus, the arguments similar to that presented above for claim(s) 13-14 is/are equally applicable to claim(s) 6-7.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang as applied to claim 8 above, and further in view of Yoshitake (US 20200394778).
Regarding claim 10, Zhang discloses the method of claim 8, but fails to teach where Yoshitake teaches wherein the clean mask is a gray image and an image that has intensity only in a defective portion (¶81 it is determined whether a difference between both the intensity values is larger than a determination threshold value, and if larger, it is determined that there is a defect; ¶133 the comparison unit 58 compares the mask die image (secondary electron image to be inspected) of the die 1 with the mask die image (secondary electron image to be inspected; if a gray scale level difference in each pixel is larger than the determination threshold Th, it is determined that there is a defect).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to have implemented the teaching of wherein the clean mask is a gray image and an image that has intensity only in a defective portion from Yoshitake into the mask inspection apparatus as disclosed by the combination of Zhang. The motivation for doing this is to improve techniques for mask inspecting defects.
Allowable Subject Matter
Claims 2-3 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, and similarly regarding claim 9, the prior art of record, alone or in combination, fails to teach at least “wherein, when ground truth (GT) is present, the model generation unit extracts a difference between the corresponding pairs using corresponding pair information, and learns so that there is no difference between a value remaining in a difference image and a value in the ground truth by applying a loss to the difference to generate the clean mask and generate the difference image”. Claim 3 depends on claim 2, and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN KY whose telephone number is (571)272-7648. The examiner can normally be reached Monday-Friday 9-5PM.
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/KEVIN KY/ Primary Examiner, Art Unit 2671