DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 1-3 and 23 are rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, because the claim purports to invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, but fails to recite a combination of elements as required by that statutory provision and thus cannot rely on the specification to provide the structure, material or acts to support the claimed function. As such, the claim recites a function that has no limits and covers every conceivable means for achieving the stated function, while the specification discloses at most only those means known to the inventor. Accordingly, the disclosure is not commensurate with the scope of the claim.
Claim 1 recites a circuit having circuitry for aligning a phase of an output signal with a phase of an input signal having circuitry operable in one of a plurality of phase alignment modes. Other that the recitation of what the circuit does (i.e. operable in multiple modes), the claim does not provide any specific structure or steps required to perform that function. The claim appears to claim all possible ways of achieving a result without limiting the invention to what is considered as invented by the applicant. As such, the claim recites a function that has no limits and covers every conceivable means for achieving the stated function, while the specification discloses at most only those means known to the inventor. Accordingly, the disclosure is not commensurate with the scope of the claim.
Claims 2-3 provide additional description of the different circuitry having regaling to the clocks and phase detector/adjustment. However, none of the claim provide any meaningful structure or steps to perform the functions recited in claim 1 and thus are rejected accordingly.
Similarly, claim 23 recites clock generator IC for maintaining a phase alignment without any meaningful structure or steps to perform the recited function.
Correction required.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9, 13-14 and 24-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 9-10 and 25:
Claim 9 depends on claim 4; wherein claim 4 recites the limitation of “determine a phase difference … and apply one or more correction steps to correct the determined phase difference. Claim 9 further states“ wherein in the multiple step alignment mode the is operable to: extend a period of each of one or more subsequent cycles of the output signal by applying a correction step having duration that does not correspond to the determined phase difference” (emphasis added ).
Thus, it is unclear how the correction of the phase difference is achieved when the correction step to extend a period where the duration does not correspond to the determined phase difference. The claim appears to be missing the essential step to achieve the correction of the determined phase difference. As such the claim is vague and indefinite.
Claim 25 recites essentially recite the same limitation as discussed in claim 9, applying a duration NOT corresponding to the predetermined phase difference; and further state selecting the cycle to apply the correction at random. These two feature DO NOT serve to correct the phase alignment sand thus it is unclear what the metes and bounds applicant intent to cover by the claim.
Regarding claim 14 and 24:
Claim 14 depends on claim 4 and further recites “wherein in the random or pseudo-random step alignment mode the phase alignment circuitry is operative to: extend a period of each of one or more subsequent cycles of the output signal by applying a correction step having a randomly or pseudo-randomly selected duration. The claim essentially states that to correct the phase difference, a duration is randomly or pseudo-randomly selected to extend a period of the cycles. A duration to extent a period is random or pseudo-random select will NOT necessarily correct the phase difference; it is essential for the duration of the extended period to correspond to the phase difference (not just some random duration) in order to correct the alignment. The claim appears to be missing the essential step to achieve the correction of the determined phase and thus render the claim vague and indefinite.
Claims 24 essentially recites the same limitation in claim 14 and therefore rejected accordingly.
Regarding claim 13 :
Claim 13 recites ”random noise source comprises a noise shaped random noise source such as a sigma-delta modulator” (emphasis added). The phrase "such as" renders the claim indefinite because it is unclear whether the limitations following the phrase are part of the claimed invention. See MPEP § 2173.05(d).
Corrections/Clarification required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 24-25 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Ono, US 5923715 A
Claim 24. Ono teaches, as best understood in light of the 35 USC 112 rejection, a phase alignment circuitry for aligning a phase of an output signal with a phase of an input clock signal [Fig. 1 PPL, abstract and col. 1, ll. 10-47 and 4, ll. 7-35, input and output clock coincide in phase ], the phase alignment circuitry being configured to: determine a phase difference between a cycle of the input clock signal [reference clock F1] and a cycle of the output signal [F2, [col 2, lines 52-65, phase difference info, col. 6, ll. 1-45 ]; and extend a period of each of one or more subsequent cycles of the output signal by applying a correction step having a randomly or pseudo-randomly selected duration, to align a phase of the output signal with a phase of the input signa [col, 4, ll. 4-63. The variable delay circuit includes inverters having a variable number of connection stages and variable load capacitance circuits to precisely control the delay value by varying the number of inverter connection stages and by controlling the output load capacitance of the inverters].
Claim 25. Ono teaches, teaches phase alignment circuitry [Fig. 1 PPL, abstract and col. 1, ll. 10-27 and 4, ll. 7-35, lock to a reference clock] for aligning a phase of an output signal [F2] with a phase of an input clock signal [reference clock F1] the phase alignment circuitry being configured to: determine a phase difference between a cycle of the input clock signal and a cycle of the output signal [col 2, lines 52-65, phase difference info, col. 6, ll. 1-45 ]; and extend a period of each of one or more subsequent cycles of the output signal by applying a correction step having a duration that does not correspond to the determined phase difference to a cycle of an output clock signal upon which the output signal is based within the period of the next cycle of the output signal, wherein phase alignment circuitry is configured to select the cycle of the output clock signal to which the correction step is applied randomly or pseudo-randomly [ col, 4, ll. 4-63, the control of delay stages of the variable delay circuit 16 is not based upon the phase comparator information. The variable delay circuit includes inverters having a variable number of connection stages and variable load capacitance circuits to precisely control the delay value by varying the number of inverter connection stages and by controlling the output load capacitance of the inverters]
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-11 and 16-23 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Vanderspool, US 5398263 A in view of Yi. 20080112526 A1.
Regarding Claim 1, Vanderspool teaches: circuitry for aligning a phase of an output signal with a phase of an input clock signal [Fig. 4-11 aligns edges of a sample clock (output signal) from divider 725 with the phase of an input clock signal (1pps signal). Abstract, col.8 11.1-5 and claim 1] the circuitry being operable in one of a plurality of phase alignment modes [Fig. 7. Mode control logic 715, col. 8, ll. 39-68], wherein the plurality of phase alignment modes comprises two or more of: a single step alignment mode [col. 8, ll.3 60-63, total sample clock retrogression may occur in no more than one period of the sample clock and col. 8, ll. 39-57] ; a multiple step alignment mode; and a random or pseudo-random step alignment mode [col. 8, ll. 39-57 and col.9 ll. 1-11, in the average mode, the sample clock phase is adjusted by approximately 3% of its period regardless of the phase difference regardless of the phase difference between the sample clock and the time-mark; timing correction is therefore dispersed over a multiple of bit clock periods].
In the alternative, though not explicitly identifying the relationship between the pulse marker 1PPS and edges of the of the input and output clocks, Yi teaches phase detector [Fig. 1-12] having for detecting the phase difference between output and input clock signals [Fig. 1-2, Feedback and Reference] having signal for tracking their rising edge to calculate the phase difference [Fig. 2 and 3, UP, DOWN, delay at either T1-T2 or T2-T3, par. 34-35. See also Fig. 3-12 for the improved fine and coarse markers to edge-to-edge measurements]. It would have been obvious to one having ordinary skills in the art before the effective filing date to realize that the implementation of such signals as shown in Yi are common in the art to measurement of phase differences in a wide range of applications in addition to the coarse phase difference indication to provide a more accurate, integrated phase difference indication [par. 2 and 8]
Claim 2. Vanderspool in view of Yi teaches the circuitry according to claim 1, wherein the output signal comprises a frame synchronisation output signal [Fig. 7, correction signal and advance/retard timing signal from the phase comparator 717], Yi, phase error signal].
Claim 3. Vanderspool in view of Yi teaches the circuitry according to claim 1, wherein the output signal comprises a bit clock output signal [Fig. 5 and 7, bit clock, output of first divider].
Claim 4, Vanderspool in view of Yi teaches the circuitry according to claim 1, wherein the circuitry comprises phase alignment circuitry configured to: determine a phase difference between a cycle of the input clock signal and a cycle of the output signal; [Fig. 7, col. 3, l. 65-col. 4, l. 15, phase offset between 1PPS and sample signal] , and apply one or more correction steps to correct the determined phase difference [Fig. 7, correction signal signal and mode control of mode control logic 715, col. 7, ll. 62-68].
Claim 5. Vanderspool in view of Yi teaches the circuitry according claim 4, wherein the phase alignment circuitry [715-717/721] is configured to count a number of cycles of a master clock signal [Ref Clock A to 521] between an edge of the output signal and a corresponding edge of the input clock signal [Col. 2, ll. 45-62, col. 6, l. 60- col. 7, 12 and abstract, phase comparator (717) measures a number of input clock signal cycles from a predetermined edge of the 1PPS signal to a predetermined edge of the sample clock signal]
Claim 6. Vanderspool in view of Yi teaches the circuitry according to claim 4, wherein: in the single step alignment mode, the phase alignment circuitry is operative to extend a period of a single subsequent cycle of the output signal by a applying a single correction step having a duration corresponding to the determined phase difference [Fig. 7, col. 8, ll. 60-63, total sample clock retrogression may occur in no more than one period of the sample clock and col. 8, ll. 39-57].
Claim 7. Vanderspool in view of Yi teaches the circuitry according to claim 5, wherein the period of the single subsequent cycle is extended by applying the single correction step to a single cycle of an output clock signal upon which the output signal is based. [Fig. 5, to the sample clock output from Programmable Divider 721-725]
Claim 8. Vanderspool in view of Yi teaches the circuitry according to claim 7, wherein the output signal is an output frame synchronisation signal and the output clock signal is an output bit clock signal [Fig. 5 and 7, correction signal and bit clock]
Claim 9. Vanderspool teaches the circuitry according to claim 4, wherein in the multiple step alignment mode the phase alignment circuitry is operable to: extend a period of each of one or more subsequent cycles of the output signal by applying a correction step having a duration that does not correspond to the determined phase difference [col. 8, ll. 39-57 and col.9 ll. 1-11, in the average mode, the sample clock phase is adjusted by approximately 3% of its period regardless of the phase difference regardless of the phase difference].
Claim 10. Vanderspool in view of Yi teaches the circuitry according to claim 9, wherein in the multiple step alignment mode the phase alignment circuitry is operative to: determine a correction step to be applied to a next cycle of the output signal to extend the period of the next cycle, based on a minimum between a predetermined correction step value and a value of a remaining phase difference between the cycle of the input clock signal and a cycle of the output signal. [col. 8, ll. 39-57 and col.9 ll. 1-11, in the average mode, the time correction is dispersed over a multiple of bit clock periods, each subsequent cycle will be the value of the phase difference less the adjustment per previous cycle]
Claim 11. Vanderspool in view of Yi teaches the circuitry according to claim 10, wherein the period of the next cycle of the output signal is extended by applying the determined correction step to a cycle of an output clock signal upon which the output signal is based within the period of the next cycle of the output signal [col. 8, ll. 39-57, col. 9, ll. 1-11, multiple of bit clock periods, bit clock; timing correction is therefore dispersed over a multiple of bit clock periods, see divide control signal operation]
Claim 16. Vanderspool in view of Yi teaches the circuitry according to claim 1, further comprising clock generator circuitry [715-717] configured to receive the input clock [1PPS] signal and a frequency reference signal [signal to 521/721 ]and to generate an output clock signal having a frequency of the input clock signal and jitter characteristics of the frequency reference signal [Fig. 5-7, PPL 700, input at A and outputs to DAC 510/719 via clock divider 71 and jitter and noise , col. 3, ll. 25-55 and col. 9, ll, 50-56].
Claim 17. Vanderspool in view of Yi teaches the circuitry according to claim 16 wherein the clock generator circuitry comprises hybrid phase locked loop circuitry comprising an analog phase locked loop having a feedback path comprising a digital frequency locked loop [ Vanderspool, Col. 10, l. 4-66, D/A converter , Digital PLL 700, a coarse timing adjustment, the selection of which sample clock transition represents a given analog output level, Voltage Controlled Oscillator (VCO) transmitter cabling and internal filtering. Yi, analog, low pass filter (LPF) while the subtractor may be a differential analog-to-digital converter (ADC) which produces a digital difference signal 215 representing the difference between the filter-integrated analog signals]
signal to a predetermined edge of the sample clock signal]
Claim 18. Vanderspool in view of Yi teaches the circuitry according to claim 4, wherein the circuitry is configured to generate a master clock signal [input to 721], and wherein a duration of the one or more correction steps is based on a period of the master clock signal. [Fig. 5 and 7 outputs from dividers 725 (dividers 521-525) , sample clock input to phase comparator 717]
Claim 19. Vanderspool in view of Yi teaches the circuitry according to claim 4, wherein the circuitry is configured to generate a master clock signal [input to 721], and wherein a duration of the one or more correction steps is based on a period of the master clock signal. [Fig. 5 and 7 outputs from dividers 725 (dividers 521-525) , sample clock input to phase comparator 717]
Claim 20-21. Vanderspool in view of Yi teaches a clock generator integrated circuit [PPL 700, Fig. 7] and a host device comprising the circuitry according to the claim 1 [Fig. 1-2 transmission system 250].
Claim 22. Vanderspool in view of Yi teaches a host device comprises an automotive device according [see Fig. 1]
Claim 23 . Vanderspool in view of Yi teaches a clock generator circuit [Fig. 5-7] having a an input for receiving an input clock signal [input to 521/721]; a first output for outputting a bit clock output signal [output of 521] ; and a second output for outputting a frame synchronisation signal [output of 525] , wherein the clock generator integrated circuit is configured to maintain a phase alignment between the input clock signal and the frame synchronisation output signal, and/or between the input clock signal and the bit clock output signal [Fig. 4-11, abstract, col. 3, l. 65-col. 4, l. 29; col. 8, ll. 2-67, phase correction];
Claim(s) 12-16 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Vanderspool view of Yi and further in view of Wendelrup US 5796360.
Claim 12. Vanderspool in view of Yi teaches the circuitry according to claim 11, and both teaches the phase alignment circuitry comprises a random noise source and the ability to remove noise and eliminate jitters [col. 9, ll. 50-64; average incoming time-mark pulses to remove random large time-mark errors and to reduce jitter errors based on the random nature of noise, and modulation timing account for the delay of 1PPS that is affected by noise, see also col. 3, 25-60, col. 9, l. 65 to col. 10, l. 60. Yi, par. 29 and 62].
Vanderpool and Yi do not explicitly teach randomly or pseudo-randomly selecting the cycle of the output clock signal to which the determined correction step. Wendeldrup teaches a phase lock loop circuit having a sigma delta modulator for noise shaping [Fig. 1-2 and background, col. 1, ll. 8-65. It would have been obvious to one having ordinary skills in the art before the effective filing date to implement then most frequenly used noise shaping and modulation technique as discussed by Wendeldrup due to its accurate and inexpensive benefits [Wendelrup, col. 1, ll. 20-54].
Claim 13. Vanderspool, Yi and Wendeldrup as combined teaches the circuitry according to claim 12, and teaches removing random noise and modulation to remove noise as discussed in claim 12 but does not talk about Delta Sigma Modulation. [ Wendelrup, col. 1, ll. 20-54].
Claim 14. Vanderspool, Yi and Wendeldrup as combined teaches the circuitry according to claim 4, wherein in the random or pseudo-random step alignment mode the phase alignment circuitry is operative to: extend a period of each of one or more subsequent cycles of the output signal by applying a correction step having a randomly or pseudo-randomly selected duration [Wendelrup, col. 1, ll. 20-54].
Claim 15. Vanderspool, Yi and Wendeldrup as combined teaches the circuitry according to claim 14, wherein in the random or pseudo-random step alignment mode the phase alignment circuitry is operative to: determine a correction step to be applied to a next cycle of the output signal to extend the period of the next cycle, based on a minimum between a randomly or pseudo-randomly selected correction step duration and a duration of a remaining phase difference between the cycle of the input clock signal and a cycle of the output signal [Wendelrup, col. 1, ll. 20-54].
Conclusion
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/KIM HUYNH/Primary Patent Examiner,
Art Unit 2176