DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statements (IDS) submitted on 10/06/2024 and 02/28/2025 are in compliance with the provisions of 37 CFR 1.97, 1.98, and MPEP § 609. They have been placed in the application file, and the information referred to therein has been considered as to the merits.
Claim Objections
Claims 1, 14, 19, and 20 are objected to because of the following informalities:
Claim 1: Change to “…process instructions in parallel; and…” (page 31).
Claim 14: Change to “…memory external [[of]] to the parallel…” (page 33).
Claim 19: Change to “…generate a respective plurality of test outputs; and…” (page 33).
Claim 20: Change to “…process instructions in parallel; and…” (page 33).
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are found in Claim 20 and are:
…a layout processing system configured to process a computer readable dataset description of a processing unit so as to generate a circuit layout description of an integrated circuit embodying the processing unit; and
an integrated circuit generation system configured to manufacture the processing unit according to the circuit layout description;…
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5 and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation "the one or more predetermined seeds" in page 31. There is insufficient antecedent basis for this limitation in the claim.
Claim 8 recites the limitation "the logic" in page 32. There is insufficient antecedent basis for this limitation in the claim.
In Claim 20, claim limitations:
…a layout processing system configured to process a computer readable dataset description of a processing unit so as to generate a circuit layout description of an integrated circuit embodying the processing unit; and
an integrated circuit generation system configured to manufacture the processing unit according to the circuit layout description;…
invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function.
The closest support for these claim limitations is Fig. 7 and ¶ 0137-0143 of the instant disclosure. However, these sections of the disclosure are completely silent as to what structure(s) is/are used for the aforementioned claimed layout processing system and integrated circuit generation system.
Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 20 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
In Claim 20, claim limitations:
…a layout processing system configured to process a computer readable dataset description of a processing unit so as to generate a circuit layout description of an integrated circuit embodying the processing unit; and
an integrated circuit generation system configured to manufacture the processing unit according to the circuit layout description;…
invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function.
The closest support for these claim limitations is Fig. 7 and ¶ 0137-0143 of the instant disclosure. However, these sections of the disclosure are completely silent as to what structure(s) is/are used for the aforementioned claimed layout processing system and integrated circuit generation system.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 14-16, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Deadman et al. (U.S. Patent No. US 11,467,830 B2), hereinafter “Deadman.”
With regards to Claim 1, Deadman teaches:
a processing unit (Fig. 2 and col. 4, lines 36-53; regarding, e.g., neural processor 2.) configured to perform parallel processing (Fig. 4; col. 6, lines 66 and 67; col. 7, lines 1-3; Fig. 7; and col. 8, lines 47-54.), the processing unit comprising a parallel processing engine (Fig. 2 and col. 4, lines 36-53; regarding, e.g., a MAC Compute Engine [MCE].), the parallel processing engine comprising:
a plurality of processing instances configured to process instructions in parallel (Fig. 2; col. 4, lines 50-64; regarding, e.g., [an] array[s] of MAC units; Fig. 4; col. 6, lines 66 and 67; col. 7, lines 1-3.);
test instruction insertion logic (Fig. 4 and col. 5, lines 41-48; regarding, e.g., the combination of control and sequencing logic unit 41, input buffers 31, input multiplexers 32, and test pattern generator 43.) configured to:
identify an idle cycle of the parallel processing engine (Fig. 4 and col. 5, lines 49-52.), and
insert a test instruction for processing, during the idle cycle, by each of the plurality of processing instances so as to generate a respective plurality of test outputs (Fig. 4 and col. 5, lines 52-64; regarding, e.g., a test pattern signal [a test instruction].); and
check logic (Fig. 4; col. 6, lines 4-14; Fig. 6; and col. 8, lines 8-33; regarding, e.g., all of the comparators 42 attached to each MAC unit.) configured to:
compare:
a test output generated, during the idle cycle, by a first processing instance of the plurality of processing instances (Fig. 4; col. 6, lines 4-14; Fig. 6; and col. 8, lines 8-33; regarding, e.g., an output of one of the MAC units being tested during a same idle clock cycle.), and
a test output generated, during the idle cycle, by a second processing instance of the plurality of processing instances (Fig. 4; col. 6, lines 4-14; Fig. 6; and col. 8, lines 8-33; regarding, e.g., an output of another one of the MAC units being tested during the same idle clock cycle. As interpreted by the Examiner, each output generated by each MAC unit is compared to an expected result; the claim language does not state that the MAC unit outputs must be compared to each other.); and
raise a fault signal if the compared test outputs do not match (Fig. 4; col. 6, lines 4-14; Fig. 6; and col. 8, lines 8-33.).
With regards to Claim 2, Deadman teaches the unit of Claim 1 as referenced above. Deadman further teaches:
wherein an idle cycle is a cycle of the parallel processing engine during which the parallel processing engine is not scheduled to process any other instructions (Fig. 2 and col. 5, lines 37-40.).
With regards to Claim 3, Deadman teaches the unit of Claim 1 as referenced above. Deadman further teaches:
wherein one or more operand values are processed in accordance with the test instruction (Fig. 4; col. 5, lines 65-67; col. 6, lines 1-9; regarding, e.g., relevant inputs generated by the test pattern generator 43 which are multiplied and then added / accumulated; Fig. 3; and col. 5, lines 14-28.), and the test instruction insertion logic is configured to pseudo-randomly generate the one or more operand values (Fig. 4; col. 5, lines 65-67; and col. 6, lines 1-9.).
With regards to Claim 4, Deadman teaches the unit of Claim 3 as referenced above. Deadman further teaches:
wherein the test instruction insertion logic is configured to pseudo-randomly generate the one or more operand values in dependence on one or more predetermined seeds (Fig. 4; col. 5, lines 65-67; and col. 6, lines 1-9; regarding, e.g., a primitive polynomial.).
With regards to Claim 5, Deadman teaches the unit of Claim 3 as referenced above. Deadman further teaches:
wherein the test instruction insertion logic is configured to pseudo-randomly generate the one or more operand values using one or more linear-feedback shift registers (Fig. 4; col. 5, lines 65-67; and col. 6, lines 1-9.) that generate the one or more operand values in dependence on the one or more predetermined seeds (Fig. 4; col. 5, lines 65-67; and col. 6, lines 1-9; regarding, e.g., a primitive polynomial.).
With regards to Claim 14, Deadman teaches the unit of Claim 1 as referenced above. Deadman further teaches:
wherein the plurality of test outputs are not written to a memory external of the parallel processing engine (Fig. 3; col. 5, lines 14-34; Fig. 4; col. 5, lines 65-67; and col. 6, lines 1-9. As interpreted by the Examiner, MAC unit outputs are stored in registers that are only internal to the MCE.).
With regards to Claim 15, Deadman teaches the unit of Claim 1 as referenced above. Deadman further teaches:
the test instruction insertion logic being implemented using fixed function hardware, and/or the check logic being implemented using fixed function hardware (Fig. 6 and col. 8, lines 21-24; regarding, e.g., separate [dedicated] comparators coupled per each individual MAC unit.).
With regards to Claim 16, Deadman teaches the unit of Claim 1 as referenced above. Deadman further teaches:
wherein each processing instance of the plurality of processing instances is identical to each of the other processing instances of the plurality of processing instances (Fig. 4; col. 6, lines 66 and 67; and col. 5, lines 1-3; regarding, e.g., “…In some implementations, each test pattern generator 43 may use the same test pattern and same expected results.”).
With regards to Claim 19, the unit of Claim 1 performs the same steps as the method of Claim 19, and Claim 19 is therefore rejected using the same art and rationale set forth above in the rejection of Claim 1 by the teachings of Deadman.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Deadman, and further in view of Beacom et al. (U.S. Patent No. US 7,272,751 B2), hereinafter “Beacom.”
With regards to Claim 17, Deadman teaches the unit of Claim 1 as referenced above. Deadman does not explicitly teach:
the processing unit being a graphics processing unit (GPU) or a central processing unit (CPU) and/or wherein the parallel processing engine is an integer pipeline, a floating-point pipeline or a complex pipeline in accordance with the unit of Claim 1.
However, Beacom teaches:
the processing unit being a graphics processing unit (GPU) or a central processing unit (CPU) (Fig. 1 and col. 4, lines 15-21.) and/or wherein the parallel processing engine is an integer pipeline, a floating-point pipeline (Fig. 1; Fig. 2; and col. 7, lines 32-37.) or a complex pipeline.
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Deadman with a CPU design employing a type of pipelining and parallelism as taught by Beacom because the use of pipelining and parallelism increases clock speed and/or the average number of operations executed per clock cycle (Beacom: col. 2, lines 8-10).
With regards to Claim 18, Deadman teaches the unit of Claim 1 as referenced above. Deadman does not explicitly teach:
the parallel processing engine being configured to perform Single Instruction Multiple Data (SIMD) processing in accordance with the unit of Claim 1.
However, Beacom teaches:
the parallel processing engine being configured to perform Single Instruction Multiple Data (SIMD) processing (Fig. 1; Fig. 2; and col. 7, lines 24-26.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Deadman with a CPU design employing a type of pipelining and parallelism as taught by Beacom because the use of pipelining and parallelism increases clock speed and/or the average number of operations executed per clock cycle (Beacom: col. 2, lines 8-10).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Deadman, and further in view of McNamara et al. (U.S. Patent No. US 11,288,145 B2), hereinafter “McNamara.”
With regards to Claim 20, Deadman teaches:
wherein the processing unit (Fig. 2 and col. 4, lines 36-53; regarding, e.g., neural processor 2.) is configured to perform parallel processing (Fig. 4; col. 6, lines 66 and 67; col. 7, lines 1-3; Fig. 7; and col. 8, lines 47-54.), the processing unit comprising a parallel processing engine (Fig. 2 and col. 4, lines 36-53; regarding, e.g., a MAC Compute Engine [MCE].), the parallel processing engine comprising:
a plurality of processing instances configured to process instructions in parallel (Fig. 2; col. 4, lines 50-64; regarding, e.g., [an] array[s] of MAC units; Fig. 4; col. 6, lines 66 and 67; col. 7, lines 1-3.);
test instruction insertion logic (Fig. 4 and col. 5, lines 41-48; regarding, e.g., the combination of control and sequencing logic unit 41, input buffers 31, input multiplexers 32, and test pattern generator 43.) configured to:
identify an idle cycle of the parallel processing engine (Fig. 4 and col. 5, lines 49-52.); and
insert a test instruction for processing, during the idle cycle, by each of the plurality of processing instances so as to generate a respective plurality of test outputs (Fig. 4 and col. 5, lines 52-64; regarding, e.g., a test pattern signal [a test instruction].); and
check logic (Fig. 4; col. 6, lines 4-14; Fig. 6; and col. 8, lines 8-33; regarding, e.g., all of the comparators 42 attached to each MAC unit.) configured to:
compare:
a test output generated, during the idle cycle, by a first processing instance of the plurality of processing instances (Fig. 4; col. 6, lines 4-14; Fig. 6; and col. 8, lines 8-33; regarding, e.g., an output of one of the MAC units being tested during a same idle clock cycle.); and
a test output generated, during the idle cycle, by a second processing instance of the plurality of processing instances (Fig. 4; col. 6, lines 4-14; Fig. 6; and col. 8, lines 8-33; regarding, e.g., an output of another one of the MAC units being tested during the same idle clock cycle. As interpreted by the Examiner, each output generated by each MAC unit is compared to an expected result; the claim language does not state that the MAC unit outputs must be compared to each other.); and
raise a fault signal if the compared test outputs do not match (Fig. 4; col. 6, lines 4-14; Fig. 6; and col. 8, lines 8-33.).
Deadman does not explicitly teach:
an integrated circuit manufacturing system comprising:
a layout processing system configured to process a computer readable dataset description of a processing unit so as to generate a circuit layout description of an integrated circuit embodying the processing unit; and
an integrated circuit generation system configured to manufacture the processing unit according to the circuit layout description.
However, McNamara teaches:
an integrated circuit manufacturing system comprising:
a layout processing system configured to process a computer readable dataset description of a processing unit so as to generate a circuit layout description of an integrated circuit embodying the processing unit (Fig. 10 and col. 22, lines 40-55.); and
an integrated circuit generation system configured to manufacture the processing unit according to the circuit layout description (Fig. 10; col. 22, lines 56-67; and col. 23, lines 1-3.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Deadman with an IC manufacturing process as taught by McNamara because implementing an improved manufacture of ICs can include performance improvements that can be traded off against the physical implementation, thereby improving the method of manufacture (McNamara: col. 23, lines 54-64).
Allowable Subject Matter
Claims 6, 7, and 9-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 8 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Shidla et al. (U.S. Patent No. US 7,206,969 B2); teaching a method of compiling a program to be executed on a target microprocessor. A cycle is identified during which a functional unit would otherwise be idle. A diagnostic operation is opportunistically scheduled for execution on the functional unit during that cycle, and a comparison is scheduled to compare a result from executing the diagnostic operation with a corresponding predetermined result.
Hickey et al. (U.S. Patent No. US 7,975,172 B2); teaching a pipelined execution unit that uses the bubbles that occur during execution to selectively repeat operations performed in one or more stages of a multistage execution pipeline to verify the results of such operations during otherwise unused execution cycles for the execution pipeline. Whenever a bubble follows a particular instruction within an execution pipeline, the result of an operation that is performed for that instruction by a particular stage of the execution pipeline may be stored, and the operation may be repeated by the stage in a subsequent execution cycle in which no productive operation would otherwise be performed due to the presence of the bubble. The results of the operations may then be compared and used to either verify the original result or identify a potential error in the execution of the instruction.
Gulati et al. (U.S. Patent No. US 10,628,274 B2); teaching techniques for a self-test of a graphics processing unit (GPU) independent of instructions from another processing device. The GPU may perform the self-test in response to a determination that the GPU enters an idle mode. The self-test may be based on information indicating a safety level, where the safety level indicates how many faults in circuits or memory blocks of the GPU need to be detected.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH KUDIRKA whose telephone number is (571)270-7126. The examiner can normally be reached M-F 7:30am - 5pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached at (571) 272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSEPH R KUDIRKA/Primary Patent Examiner, Art Unit 2114