DETAILED ACTION
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/7/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 8, 10-11, 18 is/are rejected under 35 U.S.C. 102(A)(1) as being anticipated by Tachi (US 20220262720 A1)
Regarding claim 1, Tachi discloses (reproduced Fig. 15’ below)
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A semiconductor device (reproduced Fig. 14 above), comprising: a first conductive pattern (first conductive pattern); a second conductive pattern spaced (second conductive pattern) apart in a first direction (z) from the first conductive pattern, wherein the first direction is perpendicular to an upper surface of the first conductive pattern;
a memory channel structure (50, Fig. 7) that extends in the first conductive pattern and the second conductive pattern in the first direction;
a first connection contact structure (401) that extends in the second conductive pattern in the first direction and is electrically connected to the first conductive pattern; and
a first parity contact structure (402) that extends in the second conductive pattern in the first direction and is electrically connected to the first conductive pattern,
wherein the first connection contact structure includes: a first connection contact (60); and a first connection contact dielectric layer (70) that extends around the first connection contact,
wherein the first parity contact structure includes: a first parity contact (60); and a first parity contact dielectric layer (70) that extends around the first parity contact, wherein the first parity contact dielectric layer includes: a sidewall part (sidewall part) in contact with the upper surface of the first conductive pattern and a first sidewall (sidewall on right side of first parity contact) of the second conductive pattern; and
a connection part (connection part) connected to the sidewall part, wherein a lower surface of the connection part of the first parity contact dielectric layer is in contact with an upper surface of the second conductive pattern.
Regarding claim 2, Tachi discloses the semiconductor device of claim 1, wherein a lower surface of the sidewall part of the first parity contact dielectric layer is in contact with the upper surface of the first conductive pattern, and an outer sidewall of the sidewall part of the first parity contact dielectric layer is in contact with the first sidewall of the second conductive pattern (reproduced Fig. 14 above).
Regarding claim 3, Tachi discloses the semiconductor device of claim 1, wherein an outer sidewall of the first connection contact dielectric layer is in contact with a second sidewall (sidewall on left side of first connection contact) of the second conductive pattern.
Regarding claim 4, Tachi discloses the semiconductor device of claim 1, wherein a length in the first direction of the first connection contact dielectric layer is equal to a length in the first direction of the first parity contact dielectric layer (same depth from top down to top of the first conductive pattern, reproduced Fig. 14 above).
Regarding claim 5, Tachi discloses the semiconductor device of claim 1, further comprising (reproduced Fig. 14’ below):
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a second connection contact (403) structure electrically connected to the second conductive pattern; and
a second parity contact structure (404) electrically connected to the second conductive pattern,
wherein the second connection contact structure includes: a second connection contact (60) in contact with the second conductive pattern; and a second connection contact dielectric layer (70) that extends around the second connection contact,
wherein the second parity contact structure includes: a second parity contact (60) in contact with the second conductive pattern; and a second parity contact dielectric layer (70) that extends around the second parity contact.
Regarding claim 8, Chita discloses (reproduced Fig. 14-2 below)
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A semiconductor device, comprising: a gate stack structure (40) that includes a plurality of conductive patterns including a first conductive pattern (first conductive pattern); a memory channel structure (50, Fig. 7) that extends in the gate stack structure; a first connection contact (first connection contact) structure electrically connected to the first conductive pattern; and a first parity contact structure (first parity contact) electrically connected to the first conductive pattern, wherein the first connection contact structure includes: a first connection contact (60); and a first connection contact dielectric layer (70) that extends around the first connection contact, wherein the first parity contact structure includes: a first parity contact (60); and a first parity contact dielectric layer (70) that extends around the first parity contact, wherein the first parity contact includes a first part (first part) and a second part (second part) on (touching the first part) the first part, and wherein the second part of the first parity contact includes a lower surface that connects a sidewall of the first part of the first parity contact to a sidewall of the second part of the first parity contact.
Regarding claim 10, Tachi discloses the semiconductor device of claim 8, wherein the conductive patterns further include a second conductive pattern (second conductive pattern) on the first conductive pattern, and wherein the first parity contact dielectric layer includes: a first sidewall part (sidewall of first part) in contact with an upper surface of the first conductive pattern and a sidewall of the second conductive pattern; and a connection part (on lower surface of the second part) in contact with an upper surface of the second conductive pattern.
Regarding claim 11, Tachi discloses the semiconductor device of claim 10, wherein the lower surface of the second part of the first parity contact is in contact with an upper surface of the connection part of the first parity contact dielectric layer.
Regarding claim 18, Tachi discloses the semiconductor device of claim 8, further comprising: a separation structure (ST, Fig. 14) between the first parity contact structure and the first connection contact structure (Fig. 14) in a first direction (x), wherein the separation structure extends in the gate stack structure (40) in a second direction (z, Fig. 14), wherein the first direction is parallel with an upper surface of the first conductive pattern, and wherein the second direction is perpendicular to the upper surface of the first conductive pattern (x-direction vx z-direction).
Allowable Subject Matter
Claims 6-7, 9, 12-17 are objected to as being dependent upon a rejected base claims (1 or 8) but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: prior art fails to teach a stepped sidewall of the parity contact on which other features set forth in the above objected claims rely.
Claim 19 is allowed for reciting claim 1 in combination with allowable subject matters in claims 6-7.
Claim 20 is allowable depending on claim 19.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Tokita (US 11355506 B2) discloses a memory device with two contacts of the same depth separated by a separator (Fig. 1F).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T HOANG whose telephone number is (571)272-5622. The examiner can normally be reached M-F 8:00 - 5:00.
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/DTH/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
